Merge branch 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Alex writes:
A few more radeon bug fixes, mostly for SI dpm. At this point dpm is
pretty solid across the majority of asics. I think we mostly just have
corner cases and fixing up some of the trickier features at this point.

* 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon/dpm: fix and enable reclocking on SI
drm/radeon/dpm: disable cac setup on SI
drm/radeon/si: disable cgcg and pg for now
drm/radeon/dpm: fix forcing performance state to low on cayman
drm/radeon/atom: fix fb when fetching engine params
drm/radeon: properly handle cg on asics without UVD
drm/radeon/dpm: fix powertune handling for pci id 0x6835
drm/radeon/dpm: fix si_calculate_memory_refresh_rate()
drm/radeon/dpm: fix display gap programming on SI
drm/radeon: fix audio dto programming on DCE4+

Dave Airlie 12 years ago 782cf7d8 5ae90d8e

+24 -35

5 changed files

expand all

drivers

gpu

drm

radeon

evergreen_hdmi.c

ni_dpm.c

radeon_atombios.c

si.c

si_dpm.c

+1 -1

drivers/gpu/drm/radeon/evergreen_hdmi.c

··· 157 157 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 158 158 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 159 159 */ 160 + WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); 160 161 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); 161 162 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); 162 - WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); 163 163 } 164 164 165 165

+1 -6

drivers/gpu/drm/radeon/ni_dpm.c

··· 1054 1054 int ni_dpm_force_performance_level(struct radeon_device *rdev, 1055 1055 enum radeon_dpm_forced_level level) 1056 1056 { 1057 - struct radeon_ps *rps = rdev->pm.dpm.current_ps; 1058 - struct ni_ps *ps = ni_get_ps(rps); 1059 - u32 levels; 1060 - 1061 1057 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 1062 1058 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) 1063 1059 return -EINVAL; ··· 1064 1068 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 1065 1069 return -EINVAL; 1066 1070 1067 - levels = ps->performance_level_count - 1; 1068 - if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 1071 + if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 1069 1072 return -EINVAL; 1070 1073 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 1071 1074 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)

+1 -1

drivers/gpu/drm/radeon/radeon_atombios.c

··· 2782 2782 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2783 2783 dividers->enable_dithen = (args.v3.ucCntlFlag & 2784 2784 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2785 - dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 2785 + dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 2786 2786 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 2787 2787 dividers->ref_div = args.v3.ucRefDiv; 2788 2788 dividers->vco_mode = (args.v3.ucCntlFlag &

+5 -9

drivers/gpu/drm/radeon/si.c

··· 5215 5215 5216 5216 static void si_init_cg(struct radeon_device *rdev) 5217 5217 { 5218 - bool has_uvd = true; 5219 - 5220 5218 si_enable_mgcg(rdev, true); 5221 - si_enable_cgcg(rdev, true); 5219 + si_enable_cgcg(rdev, false); 5222 5220 /* disable MC LS on Tahiti */ 5223 5221 if (rdev->family == CHIP_TAHITI) 5224 5222 si_enable_mc_ls(rdev, false); 5225 - if (has_uvd) { 5223 + if (rdev->has_uvd) { 5226 5224 si_enable_uvd_mgcg(rdev, true); 5227 5225 si_init_uvd_internal_cg(rdev); 5228 5226 } ··· 5228 5230 5229 5231 static void si_fini_cg(struct radeon_device *rdev) 5230 5232 { 5231 - bool has_uvd = true; 5232 - 5233 - if (has_uvd) 5233 + if (rdev->has_uvd) 5234 5234 si_enable_uvd_mgcg(rdev, false); 5235 5235 si_enable_cgcg(rdev, false); 5236 5236 si_enable_mgcg(rdev, false); ··· 5237 5241 static void si_init_pg(struct radeon_device *rdev) 5238 5242 { 5239 5243 bool has_pg = false; 5240 - 5244 + #if 0 5241 5245 /* only cape verde supports PG */ 5242 5246 if (rdev->family == CHIP_VERDE) 5243 5247 has_pg = true; 5244 - 5248 + #endif 5245 5249 if (has_pg) { 5246 5250 si_init_ao_cu_mask(rdev); 5247 5251 si_init_dma_pg(rdev);

+16 -18

drivers/gpu/drm/radeon/si_dpm.c

··· 37 37 38 38 #define SMC_RAM_END 0x20000 39 39 40 - #define DDR3_DRAM_ROWS 0x2000 41 - 42 40 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 43 41 44 42 static const struct si_cac_config_reg cac_weights_tahiti[] = ··· 1929 1931 si_pi->cac_override = cac_override_pitcairn; 1930 1932 si_pi->powertune_data = &powertune_data_pitcairn; 1931 1933 si_pi->dte_data = dte_data_pitcairn; 1934 + break; 1932 1935 } 1933 1936 } else if (rdev->family == CHIP_VERDE) { 1934 1937 si_pi->lcac_config = lcac_cape_verde; ··· 1940 1941 case 0x683B: 1941 1942 case 0x683F: 1942 1943 case 0x6829: 1944 + case 0x6835: 1943 1945 si_pi->cac_weights = cac_weights_cape_verde_pro; 1944 1946 si_pi->dte_data = dte_data_cape_verde; 1945 1947 break; ··· 2042 2042 ni_pi->enable_sq_ramping = false; 2043 2043 si_pi->enable_dte = false; 2044 2044 2045 - if (si_pi->powertune_data->enable_powertune_by_default) { 2045 + /* XXX: fix me */ 2046 + if (0/*si_pi->powertune_data->enable_powertune_by_default*/) { 2046 2047 ni_pi->enable_power_containment= true; 2047 2048 ni_pi->enable_cac = true; 2048 2049 if (si_pi->dte_data.enable_dte_by_default) { ··· 3238 3237 { 3239 3238 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3240 3239 struct ni_ps *ps = ni_get_ps(rps); 3241 - u32 levels; 3240 + u32 levels = ps->performance_level_count; 3242 3241 3243 3242 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3244 - if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) 3243 + if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3245 3244 return -EINVAL; 3246 3245 3247 3246 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) ··· 3250 3249 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3251 3250 return -EINVAL; 3252 3251 3253 - levels = ps->performance_level_count - 1; 3254 - if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3252 + if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3255 3253 return -EINVAL; 3256 3254 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3257 3255 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3258 3256 return -EINVAL; 3259 3257 3260 - if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) 3258 + if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3261 3259 return -EINVAL; 3262 3260 } 3263 3261 ··· 3620 3620 { 3621 3621 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3622 3622 3623 + tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3624 + tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3625 + DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3626 + 3623 3627 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3624 - tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) | 3628 + tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3625 3629 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3626 3630 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3627 3631 } ··· 4040 4036 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4041 4037 u32 engine_clock) 4042 4038 { 4043 - struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4044 4039 u32 dram_rows; 4045 4040 u32 dram_refresh_rate; 4046 4041 u32 mc_arb_rfsh_rate; 4047 4042 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4048 4043 4049 - if (pi->mem_gddr5) 4050 - dram_rows = 1 << (tmp + 10); 4044 + if (tmp >= 4) 4045 + dram_rows = 16384; 4051 4046 else 4052 - dram_rows = DDR3_DRAM_ROWS; 4047 + dram_rows = 1 << (tmp + 10); 4053 4048 4054 4049 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4055 4050 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; ··· 6016 6013 return ret; 6017 6014 } 6018 6015 6019 - #if 0 6020 - /* XXX */ 6021 6016 ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO); 6022 6017 if (ret) { 6023 6018 DRM_ERROR("si_dpm_force_performance_level failed\n"); 6024 6019 return ret; 6025 6020 } 6026 - #else 6027 - rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 6028 - #endif 6029 6021 6030 6022 return 0; 6031 6023 }