tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'warning-fixes' into next/fixes-non-critical

These are fixes for compiler warnings that for the most
part were introduced during the 3.8 cycle but are otherwise
harmless.

* warning-fixes:
scripts/sortextable: silence script output
ARM: s3c: i2c: add platform_device forward declaration
ARM: mvebu: allow selecting mvebu without Armada XP
ARM: pick Versatile by default for !MMU
ARM: integrator: fix build with INTEGRATOR_AP off
ARM: integrator/versatile: fix NOMMU warnings
ARM: sa1100: don't warn about mach/ide.h
ARM: shmobile: fix defconfig warning on CONFIG_USB
ARM: w90x900: fix legacy assembly syntax
ARM: samsung: fix assembly syntax for new gas
ARM: disable virt_to_bus/virt_to_bus almost everywhere

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 7822eee1 0e55f0b0

+56 -51
+6 -1
arch/arm/Kconfig
··· 261 261 # 262 262 choice 263 263 prompt "ARM system type" 264 - default ARCH_MULTIPLATFORM 264 + default ARCH_VERSATILE if !MMU 265 + default ARCH_MULTIPLATFORM if MMU 265 266 266 267 config ARCH_MULTIPLATFORM 267 268 bool "Allow multiple platforms to be selected" ··· 1450 1449 config ISA_DMA 1451 1450 bool 1452 1451 select ISA_DMA_API 1452 + 1453 + config ARCH_NO_VIRT_TO_BUS 1454 + def_bool y 1455 + depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK 1453 1456 1454 1457 # Select ISA DMA interface 1455 1458 config ISA_DMA_API
-1
arch/arm/configs/marzen_defconfig
··· 83 83 CONFIG_USB_RCAR_PHY=y 84 84 CONFIG_MMC=y 85 85 CONFIG_MMC_SDHI=y 86 - CONFIG_USB=y 87 86 CONFIG_USB_EHCI_HCD=y 88 87 CONFIG_USB_OHCI_HCD=y 89 88 CONFIG_USB_OHCI_HCD_PLATFORM=y
-1
arch/arm/configs/shark_defconfig
··· 73 73 CONFIG_NLS_CODEPAGE_437=m 74 74 CONFIG_NLS_CODEPAGE_850=m 75 75 CONFIG_NLS_ISO8859_1=m 76 - # CONFIG_ENABLE_WARN_DEPRECATED is not set 77 76 # CONFIG_ENABLE_MUST_CHECK is not set 78 77 CONFIG_DEBUG_KERNEL=y 79 78 # CONFIG_SCHED_DEBUG is not set
+1 -1
arch/arm/include/asm/dma.h
··· 105 105 */ 106 106 extern void __set_dma_addr(unsigned int chan, void *addr); 107 107 #define set_dma_addr(chan, addr) \ 108 - __set_dma_addr(chan, bus_to_virt(addr)) 108 + __set_dma_addr(chan, (void *)__bus_to_virt(addr)) 109 109 110 110 /* Set the DMA byte count for this channel 111 111 *
+2
arch/arm/include/asm/memory.h
··· 245 245 #define __bus_to_pfn(x) __phys_to_pfn(x) 246 246 #endif 247 247 248 + #ifdef CONFIG_VIRT_TO_BUS 248 249 static inline __deprecated unsigned long virt_to_bus(void *x) 249 250 { 250 251 return __virt_to_bus((unsigned long)x); ··· 255 254 { 256 255 return (void *)__bus_to_virt(x); 257 256 } 257 + #endif 258 258 259 259 /* 260 260 * Conversion between a struct page and a physical address.
-5
arch/arm/mach-integrator/common.h
··· 1 1 #include <linux/amba/serial.h> 2 - #ifdef CONFIG_ARCH_INTEGRATOR_AP 3 2 extern struct amba_pl010_data ap_uart_data; 4 - #else 5 - /* Not used without Integrator/AP support anyway */ 6 - struct amba_pl010_data ap_uart_data {}; 7 - #endif 8 3 void integrator_init_early(void); 9 4 int integrator_init(bool is_cp); 10 5 void integrator_reserve(void);
+1 -1
arch/arm/mach-integrator/core.c
··· 71 71 * hard-code them. The Integator/CP and forward have proper cell IDs. 72 72 * Else we leave them undefined to the bus driver can autoprobe them. 73 73 */ 74 - if (!is_cp) { 74 + if (!is_cp && IS_ENABLED(CONFIG_ARCH_INTEGRATOR_AP)) { 75 75 rtc_device.periphid = 0x00041030; 76 76 uart0_device.periphid = 0x00041010; 77 77 uart1_device.periphid = 0x00041010;
+1 -1
arch/arm/mach-integrator/integrator_ap.c
··· 94 94 * f1b00000 1b000000 GPIO 95 95 */ 96 96 97 - static struct map_desc ap_io_desc[] __initdata = { 97 + static struct map_desc ap_io_desc[] __initdata __maybe_unused = { 98 98 { 99 99 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), 100 100 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
+1 -1
arch/arm/mach-integrator/integrator_cp.c
··· 78 78 * fcb00000 cb000000 CP system control 79 79 */ 80 80 81 - static struct map_desc intcp_io_desc[] __initdata = { 81 + static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { 82 82 { 83 83 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), 84 84 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
+3 -2
arch/arm/mach-mvebu/Makefile
··· 3 3 4 4 AFLAGS_coherency_ll.o := -Wa,-march=armv7-a 5 5 6 - obj-y += system-controller.o 7 - obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o 6 + obj-y += system-controller.o 7 + obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o 8 + obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o 8 9 obj-$(CONFIG_SMP) += platsmp.o headsmp.o 9 10 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+6 -6
arch/arm/mach-s3c24xx/include/mach/debug-macro.S
··· 40 40 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) 41 41 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) 42 42 bic \rd, \rd, #0xff000 43 - ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] 43 + ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)] 44 44 and \rd, \rd, #0x00ff0000 45 45 teq \rd, #0x00440000 @ is it 2440? 46 46 1004: 47 - ldr \rd, [ \rx, # S3C2410_UFSTAT ] 47 + ldr \rd, [\rx, # S3C2410_UFSTAT] 48 48 moveq \rd, \rd, lsr #SHIFT_2440TXF 49 49 tst \rd, #S3C2410_UFSTAT_TXFULL 50 50 .endm 51 51 52 52 .macro fifo_full_s3c2410 rd, rx 53 - ldr \rd, [ \rx, # S3C2410_UFSTAT ] 53 + ldr \rd, [\rx, # S3C2410_UFSTAT] 54 54 tst \rd, #S3C2410_UFSTAT_TXFULL 55 55 .endm 56 56 ··· 68 68 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) 69 69 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) 70 70 bic \rd, \rd, #0xff000 71 - ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] 71 + ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)] 72 72 and \rd, \rd, #0x00ff0000 73 73 teq \rd, #0x00440000 @ is it 2440? 74 74 75 75 10000: 76 - ldr \rd, [ \rx, # S3C2410_UFSTAT ] 76 + ldr \rd, [\rx, # S3C2410_UFSTAT] 77 77 andne \rd, \rd, #S3C2410_UFSTAT_TXMASK 78 78 andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK 79 79 .endm 80 80 81 81 .macro fifo_level_s3c2410 rd, rx 82 - ldr \rd, [ \rx, # S3C2410_UFSTAT ] 82 + ldr \rd, [\rx, # S3C2410_UFSTAT] 83 83 and \rd, \rd, #S3C2410_UFSTAT_TXMASK 84 84 .endm 85 85
+2 -2
arch/arm/mach-s3c24xx/include/mach/entry-macro.S
··· 31 31 32 32 @@ try the interrupt offset register, since it is there 33 33 34 - ldr \irqstat, [ \base, #INTPND ] 34 + ldr \irqstat, [\base, #INTPND ] 35 35 teq \irqstat, #0 36 36 beq 1002f 37 - ldr \irqnr, [ \base, #INTOFFSET ] 37 + ldr \irqnr, [\base, #INTOFFSET ] 38 38 mov \tmp, #1 39 39 tst \irqstat, \tmp, lsl \irqnr 40 40 bne 1001f
+1 -1
arch/arm/mach-s3c24xx/pm-h1940.S
··· 30 30 31 31 h1940_pm_return: 32 32 mov r0, #S3C2410_PA_GPIO 33 - ldr pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ] 33 + ldr pc, [r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO]
+6 -6
arch/arm/mach-s3c24xx/sleep-s3c2410.S
··· 45 45 ldr r4, =S3C2410_REFRESH 46 46 ldr r5, =S3C24XX_MISCCR 47 47 ldr r6, =S3C2410_CLKCON 48 - ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB) 49 - ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB) 50 - ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB) 48 + ldr r7, [r4] @ get REFRESH (and ensure in TLB) 49 + ldr r8, [r5] @ get MISCCR (and ensure in TLB) 50 + ldr r9, [r6] @ get CLKCON (and ensure in TLB) 51 51 52 52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command 53 53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals ··· 61 61 @@ align next bit of code to cache line 62 62 .align 5 63 63 s3c2410_do_sleep: 64 - streq r7, [ r4 ] @ SDRAM sleep command 65 - streq r8, [ r5 ] @ SDRAM power-down config 66 - streq r9, [ r6 ] @ CPU sleep 64 + streq r7, [r4] @ SDRAM sleep command 65 + streq r8, [r5] @ SDRAM power-down config 66 + streq r9, [r6] @ CPU sleep 67 67 1: beq 1b 68 68 mov pc, r14
+6 -6
arch/arm/mach-s3c24xx/sleep-s3c2412.S
··· 57 57 * retry, as simply returning causes the system to lock. 58 58 */ 59 59 60 - ldrne r9, [ r1 ] 61 - strne r9, [ r1 ] 62 - ldrne r9, [ r2 ] 63 - strne r9, [ r2 ] 64 - ldrne r9, [ r3 ] 65 - strne r9, [ r3 ] 60 + ldrne r9, [r1] 61 + strne r9, [r1] 62 + ldrne r9, [r2] 63 + strne r9, [r2] 64 + ldrne r9, [r3] 65 + strne r9, [r3] 66 66 bne s3c2412_sleep_enter1 67 67 68 68 mov pc, r14
-3
arch/arm/mach-sa1100/lart.c
··· 24 24 25 25 #include "generic.h" 26 26 27 - 28 - #warning "include/asm/arch-sa1100/ide.h needs fixing for lart" 29 - 30 27 static struct mcp_plat_data lart_mcp_data = { 31 28 .mccr0 = MCCR0_ADM, 32 29 .sclk_rate = 11981000,
+5
arch/arm/mach-versatile/Kconfig
··· 25 25 Include support for the ARM(R) Versatile/PB platform, 26 26 using the device tree for discovery 27 27 28 + config MACH_VERSATILE_AUTO 29 + def_bool y 30 + depends on !ARCH_VERSATILE_PB && !MACH_VERSATILE_AB 31 + select MACH_VERSATILE_DT 32 + 28 33 endmenu
+1 -1
arch/arm/mach-versatile/core.c
··· 114 114 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE); 115 115 } 116 116 117 - static struct map_desc versatile_io_desc[] __initdata = { 117 + static struct map_desc versatile_io_desc[] __initdata __maybe_unused = { 118 118 { 119 119 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE), 120 120 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
+2 -2
arch/arm/mach-w90x900/include/mach/entry-macro.S
··· 19 19 20 20 mov \base, #AIC_BA 21 21 22 - ldr \irqnr, [ \base, #AIC_IPER] 23 - ldr \irqnr, [ \base, #AIC_ISNR] 22 + ldr \irqnr, [\base, #AIC_IPER] 23 + ldr \irqnr, [\base, #AIC_ISNR] 24 24 cmp \irqnr, #0 25 25 26 26 .endm
+9 -9
arch/arm/plat-samsung/include/plat/debug-macro.S
··· 14 14 /* The S5PV210/S5PC110 implementations are as belows. */ 15 15 16 16 .macro fifo_level_s5pv210 rd, rx 17 - ldr \rd, [ \rx, # S3C2410_UFSTAT ] 17 + ldr \rd, [\rx, # S3C2410_UFSTAT] 18 18 and \rd, \rd, #S5PV210_UFSTAT_TXMASK 19 19 .endm 20 20 21 21 .macro fifo_full_s5pv210 rd, rx 22 - ldr \rd, [ \rx, # S3C2410_UFSTAT ] 22 + ldr \rd, [\rx, # S3C2410_UFSTAT] 23 23 tst \rd, #S5PV210_UFSTAT_TXFULL 24 24 .endm 25 25 ··· 27 27 * most widely re-used */ 28 28 29 29 .macro fifo_level_s3c2440 rd, rx 30 - ldr \rd, [ \rx, # S3C2410_UFSTAT ] 30 + ldr \rd, [\rx, # S3C2410_UFSTAT] 31 31 and \rd, \rd, #S3C2440_UFSTAT_TXMASK 32 32 .endm 33 33 ··· 36 36 #endif 37 37 38 38 .macro fifo_full_s3c2440 rd, rx 39 - ldr \rd, [ \rx, # S3C2410_UFSTAT ] 39 + ldr \rd, [\rx, # S3C2410_UFSTAT] 40 40 tst \rd, #S3C2440_UFSTAT_TXFULL 41 41 .endm 42 42 ··· 45 45 #endif 46 46 47 47 .macro senduart,rd,rx 48 - strb \rd, [\rx, # S3C2410_UTXH ] 48 + strb \rd, [\rx, # S3C2410_UTXH] 49 49 .endm 50 50 51 51 .macro busyuart, rd, rx 52 - ldr \rd, [ \rx, # S3C2410_UFCON ] 52 + ldr \rd, [\rx, # S3C2410_UFCON] 53 53 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? 54 54 beq 1001f @ 55 55 @ FIFO enabled... ··· 60 60 61 61 1001: 62 62 @ busy waiting for non fifo 63 - ldr \rd, [ \rx, # S3C2410_UTRSTAT ] 63 + ldr \rd, [\rx, # S3C2410_UTRSTAT] 64 64 tst \rd, #S3C2410_UTRSTAT_TXFE 65 65 beq 1001b 66 66 ··· 68 68 .endm 69 69 70 70 .macro waituart,rd,rx 71 - ldr \rd, [ \rx, # S3C2410_UFCON ] 71 + ldr \rd, [\rx, # S3C2410_UFCON] 72 72 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? 73 73 beq 1001f @ 74 74 @ FIFO enabled... ··· 79 79 b 1002f 80 80 1001: 81 81 @ idle waiting for non fifo 82 - ldr \rd, [ \rx, # S3C2410_UTRSTAT ] 82 + ldr \rd, [\rx, # S3C2410_UTRSTAT] 83 83 tst \rd, #S3C2410_UTRSTAT_TXFE 84 84 beq 1001b 85 85
+2
include/linux/platform_data/i2c-s3c2410.h
··· 15 15 16 16 #define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */ 17 17 18 + struct platform_device; 19 + 18 20 /** 19 21 * struct s3c2410_platform_i2c - Platform data for s3c I2C. 20 22 * @bus_num: The bus number to use (if possible).
+1 -1
scripts/sortextable.h
··· 182 182 _r(&sort_needed_sym->st_value) - 183 183 _r(&sort_needed_sec->sh_addr); 184 184 185 - #if 1 185 + #if 0 186 186 printf("sort done marker at %lx\n", 187 187 (unsigned long)((char *)sort_done_location - (char *)ehdr)); 188 188 #endif