Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

x86, AMD, NB: Add multi-domain support

Fix get_node_id to match northbridge IDs from the array of detected
ones, allowing multi-server support such as with Numascale's
NumaConnect, renaming to 'amd_get_node_id' for consistency.

Signed-off-by: Daniel J Blueman <daniel@numascale-asia.com>
Link: http://lkml.kernel.org/r/1353997932-8475-1-git-send-email-daniel@numascale-asia.com
[Boris: shorten lines to fit 80 cols]
Signed-off-by: Borislav Petkov <bp@alien8.de>

authored by

Daniel J Blueman and committed by
Borislav Petkov
772c3ff3 9931faca

+20 -9
+17
arch/x86/include/asm/amd_nb.h
··· 81 81 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL; 82 82 } 83 83 84 + static inline u16 amd_get_node_id(struct pci_dev *pdev) 85 + { 86 + struct pci_dev *misc; 87 + int i; 88 + 89 + for (i = 0; i != amd_nb_num(); i++) { 90 + misc = node_to_amd_nb(i)->misc; 91 + 92 + if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) && 93 + PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn)) 94 + return i; 95 + } 96 + 97 + WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev)); 98 + return 0; 99 + } 100 + 84 101 #else 85 102 86 103 #define amd_nb_num(x) 0
+3 -3
drivers/edac/amd64_edac.c
··· 2474 2474 struct mem_ctl_info *mci = NULL; 2475 2475 struct edac_mc_layer layers[2]; 2476 2476 int err = 0, ret; 2477 - u8 nid = get_node_id(F2); 2477 + u16 nid = amd_get_node_id(F2); 2478 2478 2479 2479 ret = -ENOMEM; 2480 2480 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); ··· 2566 2566 static int amd64_probe_one_instance(struct pci_dev *pdev, 2567 2567 const struct pci_device_id *mc_type) 2568 2568 { 2569 - u8 nid = get_node_id(pdev); 2569 + u16 nid = amd_get_node_id(pdev); 2570 2570 struct pci_dev *F3 = node_to_amd_nb(nid)->misc; 2571 2571 struct ecc_settings *s; 2572 2572 int ret = 0; ··· 2616 2616 { 2617 2617 struct mem_ctl_info *mci; 2618 2618 struct amd64_pvt *pvt; 2619 - u8 nid = get_node_id(pdev); 2619 + u16 nid = amd_get_node_id(pdev); 2620 2620 struct pci_dev *F3 = node_to_amd_nb(nid)->misc; 2621 2621 struct ecc_settings *s = ecc_stngs[nid]; 2622 2622
-6
drivers/edac/amd64_edac.h
··· 292 292 /* MSRs */ 293 293 #define MSR_MCGCTL_NBE BIT(4) 294 294 295 - /* AMD sets the first MC device at device ID 0x18. */ 296 - static inline u8 get_node_id(struct pci_dev *pdev) 297 - { 298 - return PCI_SLOT(pdev->devfn) - 0x18; 299 - } 300 - 301 295 enum amd_families { 302 296 K8_CPUS = 0, 303 297 F10_CPUS,