tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'mips_fixes_5.3_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS fixes from Paul Burton:
"A few MIPS fixes for 5.3:

- Various switch fall through annotations to fixup warnings & errors
resulting from -Wimplicit-fallthrough.

- A fix for systems (at least jazz) using an i8253 PIT as clocksource
when it's not suitably configured.

- Set struct cacheinfo's cpu_map_populated field to true, indicating
that we filled in cache info detected from cop0 registers &
avoiding complaints about that info being (intentionally) missing
in devicetree"

* tag 'mips_fixes_5.3_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
MIPS: BCM63XX: Mark expected switch fall-through
MIPS: OProfile: Mark expected switch fall-throughs
MIPS: Annotate fall-through in Cavium Octeon code
MIPS: Annotate fall-through in kvm/emulate.c
mips: fix cacheinfo
MIPS: kernel: only use i8253 clocksource with periodic clockevent

Linus Torvalds 76d7961f f4eb1423

options
unified split
Changed files
+20 -1
arch
mips
cavium-octeon
octeon-usb.c
kernel
cacheinfo.c
i8253.c
kvm
emulate.c
oprofile
op_model_mipsxx.c
pci
ops-bcm63xx.c
+1
arch/mips/cavium-octeon/octeon-usb.c
··· 398 default: 399 dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n", 400 clock_rate); 401 case 100000000: 402 mpll_mul = 0x19; 403 if (ref_clk_sel < 2)
··· 398 default: 399 dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n", 400 clock_rate); 401 + /* fall through */ 402 case 100000000: 403 mpll_mul = 0x19; 404 if (ref_clk_sel < 2)
+2
arch/mips/kernel/cacheinfo.c
··· 69 if (c->tcache.waysize) 70 populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED); 71 72 return 0; 73 } 74
··· 69 if (c->tcache.waysize) 70 populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED); 71 72 + this_cpu_ci->cpu_map_populated = true; 73 + 74 return 0; 75 } 76
+2 -1
arch/mips/kernel/i8253.c
··· 32 33 static int __init init_pit_clocksource(void) 34 { 35 - if (num_possible_cpus() > 1) /* PIT does not scale! */ 36 return 0; 37 38 return clocksource_i8253_init();
··· 32 33 static int __init init_pit_clocksource(void) 34 { 35 + if (num_possible_cpus() > 1 || /* PIT does not scale! */ 36 + !clockevent_state_periodic(&i8253_clockevent)) 37 return 0; 38 39 return clocksource_i8253_init();
+1
arch/mips/kvm/emulate.c
··· 140 /* These are unconditional and in j_format. */ 141 case jal_op: 142 arch->gprs[31] = instpc + 8; 143 case j_op: 144 epc += 4; 145 epc >>= 28;
··· 140 /* These are unconditional and in j_format. */ 141 case jal_op: 142 arch->gprs[31] = instpc + 8; 143 + /* fall through */ 144 case j_op: 145 epc += 4; 146 epc >>= 28;
+13
arch/mips/oprofile/op_model_mipsxx.c
··· 172 case 4: 173 w_c0_perfctrl3(0); 174 w_c0_perfcntr3(reg.counter[3]); 175 case 3: 176 w_c0_perfctrl2(0); 177 w_c0_perfcntr2(reg.counter[2]); 178 case 2: 179 w_c0_perfctrl1(0); 180 w_c0_perfcntr1(reg.counter[1]); 181 case 1: 182 w_c0_perfctrl0(0); 183 w_c0_perfcntr0(reg.counter[0]); ··· 198 switch (counters) { 199 case 4: 200 w_c0_perfctrl3(WHAT | reg.control[3]); 201 case 3: 202 w_c0_perfctrl2(WHAT | reg.control[2]); 203 case 2: 204 w_c0_perfctrl1(WHAT | reg.control[1]); 205 case 1: 206 w_c0_perfctrl0(WHAT | reg.control[0]); 207 } ··· 221 switch (counters) { 222 case 4: 223 w_c0_perfctrl3(0); 224 case 3: 225 w_c0_perfctrl2(0); 226 case 2: 227 w_c0_perfctrl1(0); 228 case 1: 229 w_c0_perfctrl0(0); 230 } ··· 245 246 switch (counters) { 247 #define HANDLE_COUNTER(n) \ 248 case n + 1: \ 249 control = r_c0_perfctrl ## n(); \ 250 counter = r_c0_perfcntr ## n(); \ ··· 307 case 4: 308 w_c0_perfctrl3(0); 309 w_c0_perfcntr3(0); 310 case 3: 311 w_c0_perfctrl2(0); 312 w_c0_perfcntr2(0); 313 case 2: 314 w_c0_perfctrl1(0); 315 w_c0_perfcntr1(0); 316 case 1: 317 w_c0_perfctrl0(0); 318 w_c0_perfcntr0(0);
··· 172 case 4: 173 w_c0_perfctrl3(0); 174 w_c0_perfcntr3(reg.counter[3]); 175 + /* fall through */ 176 case 3: 177 w_c0_perfctrl2(0); 178 w_c0_perfcntr2(reg.counter[2]); 179 + /* fall through */ 180 case 2: 181 w_c0_perfctrl1(0); 182 w_c0_perfcntr1(reg.counter[1]); 183 + /* fall through */ 184 case 1: 185 w_c0_perfctrl0(0); 186 w_c0_perfcntr0(reg.counter[0]); ··· 195 switch (counters) { 196 case 4: 197 w_c0_perfctrl3(WHAT | reg.control[3]); 198 + /* fall through */ 199 case 3: 200 w_c0_perfctrl2(WHAT | reg.control[2]); 201 + /* fall through */ 202 case 2: 203 w_c0_perfctrl1(WHAT | reg.control[1]); 204 + /* fall through */ 205 case 1: 206 w_c0_perfctrl0(WHAT | reg.control[0]); 207 } ··· 215 switch (counters) { 216 case 4: 217 w_c0_perfctrl3(0); 218 + /* fall through */ 219 case 3: 220 w_c0_perfctrl2(0); 221 + /* fall through */ 222 case 2: 223 w_c0_perfctrl1(0); 224 + /* fall through */ 225 case 1: 226 w_c0_perfctrl0(0); 227 } ··· 236 237 switch (counters) { 238 #define HANDLE_COUNTER(n) \ 239 + /* fall through */ \ 240 case n + 1: \ 241 control = r_c0_perfctrl ## n(); \ 242 counter = r_c0_perfcntr ## n(); \ ··· 297 case 4: 298 w_c0_perfctrl3(0); 299 w_c0_perfcntr3(0); 300 + /* fall through */ 301 case 3: 302 w_c0_perfctrl2(0); 303 w_c0_perfcntr2(0); 304 + /* fall through */ 305 case 2: 306 w_c0_perfctrl1(0); 307 w_c0_perfcntr1(0); 308 + /* fall through */ 309 case 1: 310 w_c0_perfctrl0(0); 311 w_c0_perfcntr0(0);
+1
arch/mips/pci/ops-bcm63xx.c
··· 474 if (PCI_SLOT(devfn) == 0) 475 return bcm_pcie_readl(PCIE_DLSTATUS_REG) 476 & DLSTATUS_PHYLINKUP; 477 default: 478 return false; 479 }
··· 474 if (PCI_SLOT(devfn) == 0) 475 return bcm_pcie_readl(PCIE_DLSTATUS_REG) 476 & DLSTATUS_PHYLINKUP; 477 + /* else, fall through */ 478 default: 479 return false; 480 }