tjh.dev / kernel
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ARM: imx5x: clean up ARCH_MX5X

Move to SOC_SOC_IMX5X. Leave only places which prevent multi-soc
using ARCH_MX5X.

Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

authored by

Richard Zhao and committed by
Sascha Hauer 76851671 48f6b099

+12 -11
+2 -1
arch/arm/mach-mx5/Kconfig
··· 1 1 if ARCH_MX5 2 - # ARCH_MX51 and ARCH_MX50 are left for compatibility 2 + # ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single 3 + # image. So for most time, SOC_IMX50/51/53 should be used. 3 4 4 5 config ARCH_MX50 5 6 bool
+1 -1
arch/arm/plat-mxc/devices/platform-imx-dma.c
··· 194 194 } else 195 195 #endif 196 196 197 - #if defined(CONFIG_ARCH_MX51) 197 + #if defined(CONFIG_SOC_IMX51) 198 198 if (cpu_is_mx51()) { 199 199 imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1; 200 200 ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
+3 -3
arch/arm/plat-mxc/include/mach/irqs.h
··· 23 23 #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS 24 24 25 25 /* these are ordered by size to support multi-SoC kernels */ 26 - #if defined CONFIG_ARCH_MX53 26 + #if defined CONFIG_SOC_IMX53 27 27 #define MXC_GPIO_IRQS (32 * 7) 28 28 #elif defined CONFIG_ARCH_MX2 29 29 #define MXC_GPIO_IRQS (32 * 6) 30 - #elif defined CONFIG_ARCH_MX50 30 + #elif defined CONFIG_SOC_IMX50 31 31 #define MXC_GPIO_IRQS (32 * 6) 32 32 #elif defined CONFIG_ARCH_MX1 33 33 #define MXC_GPIO_IRQS (32 * 4) 34 34 #elif defined CONFIG_ARCH_MX25 35 35 #define MXC_GPIO_IRQS (32 * 4) 36 - #elif defined CONFIG_ARCH_MX51 36 + #elif defined CONFIG_SOC_IMX51 37 37 #define MXC_GPIO_IRQS (32 * 4) 38 38 #elif defined CONFIG_ARCH_MXC91231 39 39 #define MXC_GPIO_IRQS (32 * 4)
+3 -3
arch/arm/plat-mxc/include/mach/mxc.h
··· 127 127 # define cpu_is_mx35() (0) 128 128 #endif 129 129 130 - #ifdef CONFIG_ARCH_MX50 130 + #ifdef CONFIG_SOC_IMX50 131 131 # ifdef mxc_cpu_type 132 132 # undef mxc_cpu_type 133 133 # define mxc_cpu_type __mxc_cpu_type ··· 139 139 # define cpu_is_mx50() (0) 140 140 #endif 141 141 142 - #ifdef CONFIG_ARCH_MX51 142 + #ifdef CONFIG_SOC_IMX51 143 143 # ifdef mxc_cpu_type 144 144 # undef mxc_cpu_type 145 145 # define mxc_cpu_type __mxc_cpu_type ··· 151 151 # define cpu_is_mx51() (0) 152 152 #endif 153 153 154 - #ifdef CONFIG_ARCH_MX53 154 + #ifdef CONFIG_SOC_IMX53 155 155 # ifdef mxc_cpu_type 156 156 # undef mxc_cpu_type 157 157 # define mxc_cpu_type __mxc_cpu_type
+1 -1
drivers/mtd/nand/Kconfig
··· 476 476 477 477 config MTD_NAND_MXC 478 478 tristate "MXC NAND support" 479 - depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX51 479 + depends on IMX_HAVE_PLATFORM_MXC_NAND 480 480 help 481 481 This enables the driver for the NAND flash controller on the 482 482 MXC processors.
+2 -2
drivers/spi/Kconfig
··· 164 164 def_bool y if ARCH_MX31 165 165 166 166 config SPI_IMX_VER_0_7 167 - def_bool y if ARCH_MX25 || ARCH_MX35 || ARCH_MX51 || ARCH_MX53 167 + def_bool y if ARCH_MX25 || ARCH_MX35 || SOC_IMX51 || SOC_IMX53 168 168 169 169 config SPI_IMX_VER_2_3 170 - def_bool y if ARCH_MX51 || ARCH_MX53 170 + def_bool y if SOC_IMX51 || SOC_IMX53 171 171 172 172 config SPI_IMX 173 173 tristate "Freescale i.MX SPI controllers"