-6
arch/mips/bcm47xx/setup.c
-6
arch/mips/bcm47xx/setup.c
···
212
212
*/
213
213
if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
214
214
cpu_wait = NULL;
215
-
216
-
/*
217
-
* BCM47XX Erratum "R10: PCIe Transactions Periodically Fail"
218
-
* Enable ExternalSync for sync instruction to take effect
219
-
*/
220
-
set_c0_config7(MIPS_CONF7_ES);
221
215
break;
222
216
#endif
223
217
}
-3
arch/mips/include/asm/mipsregs.h
-3
arch/mips/include/asm/mipsregs.h
···
681
681
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
682
682
683
683
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
684
-
/* ExternalSync */
685
-
#define MIPS_CONF7_ES (_ULCAST_(1) << 8)
686
684
687
685
#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
688
686
#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
···
2765
2767
__BUILD_SET_C0(cause)
2766
2768
__BUILD_SET_C0(config)
2767
2769
__BUILD_SET_C0(config5)
2768
-
__BUILD_SET_C0(config7)
2769
2770
__BUILD_SET_C0(intcontrol)
2770
2771
__BUILD_SET_C0(intctl)
2771
2772
__BUILD_SET_C0(srsmap)