drm/i915: Remove surplus POSTING_READs before wait_for_vblank

... as wait_for_vblank (and friends) will do a flush of the MMIO writes
anyway.

References: https://bugs.freedesktop.org/show_bug.cgi?id=34601
Cc: Jesse Barnes <[e-mail]>
Signed-off-by: Chris Wilson <[e-mail]>
Reviewed-by: Keith Packard <[e-mail]>
Reviewed-by: Jesse Barnes <[e-mail]>

drivers/gpu/drm/i915/intel_display.c

···
 	val = I915_READ(reg);
 	val |= PIPECONF_ENABLE;
 	I915_WRITE(reg, val);
-	POSTING_READ(reg);
 	intel_wait_for_vblank(dev_priv->dev, pipe);
 }
 
···
 	val = I915_READ(reg);
 	val &= ~PIPECONF_ENABLE;
 	I915_WRITE(reg, val);
-	POSTING_READ(reg);
 	intel_wait_for_pipe_off(dev_priv->dev, pipe);
 }
 
···
 	val = I915_READ(reg);
 	val |= DISPLAY_PLANE_ENABLE;
 	I915_WRITE(reg, val);
-	POSTING_READ(reg);
 	intel_wait_for_vblank(dev_priv->dev, pipe);
 }
 
···
 	val = I915_READ(reg);
 	val &= ~DISPLAY_PLANE_ENABLE;
 	I915_WRITE(reg, val);
-	POSTING_READ(reg);
 	intel_flush_display_plane(dev_priv, plane);
 	intel_wait_for_vblank(dev_priv->dev, pipe);
 }
···
 			return;
 
 		I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
-		POSTING_READ(DPFC_CONTROL);
 		intel_wait_for_vblank(dev, intel_crtc->pipe);
 	}
 
···
 			return;
 
 		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
-		POSTING_READ(ILK_DPFC_CONTROL);
 		intel_wait_for_vblank(dev, intel_crtc->pipe);
 	}
 
···
 
 		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
 		I915_WRITE(dpll_reg, dpll);
-		POSTING_READ(dpll_reg);
 		intel_wait_for_vblank(dev, pipe);
 
 		dpll = I915_READ(dpll_reg);
···
 
 		dpll |= DISPLAY_RATE_SELECT_FPA1;
 		I915_WRITE(dpll_reg, dpll);
-		dpll = I915_READ(dpll_reg);
 		intel_wait_for_vblank(dev, pipe);
 		dpll = I915_READ(dpll_reg);
 		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))