drm/amd/display: Fix rest of pass-by-value structs in DML

+5 -5

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

··· 502 502 /*todo: soc->sr_enter_plus_exit_time??*/ 503 503 dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep; 504 504 505 - dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src); 506 - dml1_extract_rq_regs(dml, rq_regs, rq_param); 505 + dml1_rq_dlg_get_rq_params(dml, &rq_param, &input.pipe.src); 506 + dml1_extract_rq_regs(dml, rq_regs, &rq_param); 507 507 dml1_rq_dlg_get_dlg_params( 508 508 dml, 509 509 dlg_regs, 510 510 ttu_regs, 511 - rq_param.dlg, 512 - dlg_sys_param, 513 - input, 511 + &rq_param.dlg, 512 + &dlg_sys_param, 513 + &input, 514 514 true, 515 515 true, 516 516 v->pte_enable == dcn_bw_yes,

+63 -63

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

··· 37 37 // 38 38 static void dml20_rq_dlg_get_rq_params( 39 39 struct display_mode_lib *mode_lib, 40 - display_rq_params_st * rq_param, 41 - const display_pipe_source_params_st pipe_src_param); 40 + display_rq_params_st *rq_param, 41 + const display_pipe_source_params_st *pipe_src_param); 42 42 43 43 // Function: dml20_rq_dlg_get_dlg_params 44 44 // Calculate deadline related parameters ··· 49 49 const unsigned int pipe_idx, 50 50 display_dlg_regs_st *disp_dlg_regs, 51 51 display_ttu_regs_st *disp_ttu_regs, 52 - const display_rq_dlg_params_st rq_dlg_param, 53 - const display_dlg_sys_params_st dlg_sys_param, 52 + const display_rq_dlg_params_st *rq_dlg_param, 53 + const display_dlg_sys_params_st *dlg_sys_param, 54 54 const bool cstate_en, 55 55 const bool pstate_en); 56 56 /* ··· 188 188 189 189 static void extract_rq_regs(struct display_mode_lib *mode_lib, 190 190 display_rq_regs_st *rq_regs, 191 - const display_rq_params_st rq_param) 191 + const display_rq_params_st *rq_param) 192 192 { 193 193 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 194 194 unsigned int detile_buf_plane1_addr = 0; 195 195 196 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l); 196 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); 197 197 198 - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), 198 + rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 199 199 1) - 3; 200 200 201 - if (rq_param.yuv420) { 202 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c); 203 - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), 201 + if (rq_param->yuv420) { 202 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); 203 + rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 204 204 1) - 3; 205 205 } 206 206 207 - rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); 208 - rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); 207 + rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); 208 + rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); 209 209 210 210 // TODO: take the max between luma, chroma chunk size? 211 211 // okay for now, as we are setting chunk_bytes to 8kb anyways 212 - if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb 212 + if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb 213 213 rq_regs->drq_expansion_mode = 0; 214 214 } else { 215 215 rq_regs->drq_expansion_mode = 2; ··· 218 218 rq_regs->mrq_expansion_mode = 1; 219 219 rq_regs->crq_expansion_mode = 1; 220 220 221 - if (rq_param.yuv420) { 222 - if ((double) rq_param.misc.rq_l.stored_swath_bytes 223 - / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { 221 + if (rq_param->yuv420) { 222 + if ((double) rq_param->misc.rq_l.stored_swath_bytes 223 + / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { 224 224 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma 225 225 } else { 226 226 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), ··· 233 233 234 234 static void handle_det_buf_split(struct display_mode_lib *mode_lib, 235 235 display_rq_params_st *rq_param, 236 - const display_pipe_source_params_st pipe_src_param) 236 + const display_pipe_source_params_st *pipe_src_param) 237 237 { 238 238 unsigned int total_swath_bytes = 0; 239 239 unsigned int swath_bytes_l = 0; ··· 242 242 unsigned int full_swath_bytes_packed_c = 0; 243 243 bool req128_l = false; 244 244 bool req128_c = false; 245 - bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); 246 - bool surf_vert = (pipe_src_param.source_scan == dm_vert); 245 + bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 246 + bool surf_vert = (pipe_src_param->source_scan == dm_vert); 247 247 unsigned int log2_swath_height_l = 0; 248 248 unsigned int log2_swath_height_c = 0; 249 249 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; ··· 685 685 display_data_rq_sizing_params_st *rq_sizing_param, 686 686 display_data_rq_dlg_params_st *rq_dlg_param, 687 687 display_data_rq_misc_params_st *rq_misc_param, 688 - const display_pipe_source_params_st pipe_src_param, 688 + const display_pipe_source_params_st *pipe_src_param, 689 689 bool is_chroma) 690 690 { 691 691 bool mode_422 = false; ··· 697 697 698 698 // TODO check if ppe apply for both luma and chroma in 422 case 699 699 if (is_chroma) { 700 - vp_width = pipe_src_param.viewport_width_c / ppe; 701 - vp_height = pipe_src_param.viewport_height_c; 702 - data_pitch = pipe_src_param.data_pitch_c; 703 - meta_pitch = pipe_src_param.meta_pitch_c; 700 + vp_width = pipe_src_param->viewport_width_c / ppe; 701 + vp_height = pipe_src_param->viewport_height_c; 702 + data_pitch = pipe_src_param->data_pitch_c; 703 + meta_pitch = pipe_src_param->meta_pitch_c; 704 704 } else { 705 - vp_width = pipe_src_param.viewport_width / ppe; 706 - vp_height = pipe_src_param.viewport_height; 707 - data_pitch = pipe_src_param.data_pitch; 708 - meta_pitch = pipe_src_param.meta_pitch; 705 + vp_width = pipe_src_param->viewport_width / ppe; 706 + vp_height = pipe_src_param->viewport_height; 707 + data_pitch = pipe_src_param->data_pitch; 708 + meta_pitch = pipe_src_param->meta_pitch; 709 709 } 710 710 711 711 rq_sizing_param->chunk_bytes = 8192; ··· 728 728 vp_height, 729 729 data_pitch, 730 730 meta_pitch, 731 - pipe_src_param.source_format, 732 - pipe_src_param.sw_mode, 733 - pipe_src_param.macro_tile_size, 734 - pipe_src_param.source_scan, 731 + pipe_src_param->source_format, 732 + pipe_src_param->sw_mode, 733 + pipe_src_param->macro_tile_size, 734 + pipe_src_param->source_scan, 735 735 is_chroma); 736 736 } 737 737 738 738 static void dml20_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 739 739 display_rq_params_st *rq_param, 740 - const display_pipe_source_params_st pipe_src_param) 740 + const display_pipe_source_params_st *pipe_src_param) 741 741 { 742 742 // get param for luma surface 743 - rq_param->yuv420 = pipe_src_param.source_format == dm_420_8 744 - || pipe_src_param.source_format == dm_420_10; 745 - rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10; 743 + rq_param->yuv420 = pipe_src_param->source_format == dm_420_8 744 + || pipe_src_param->source_format == dm_420_10; 745 + rq_param->yuv420_10bpc = pipe_src_param->source_format == dm_420_10; 746 746 747 747 get_surf_rq_param(mode_lib, 748 748 &(rq_param->sizing.rq_l), ··· 751 751 pipe_src_param, 752 752 0); 753 753 754 - if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) { 754 + if (is_dual_plane((enum source_format_class)(pipe_src_param->source_format))) { 755 755 // get param for chroma surface 756 756 get_surf_rq_param(mode_lib, 757 757 &(rq_param->sizing.rq_c), ··· 773 773 display_rq_params_st rq_param = {0}; 774 774 775 775 memset(rq_regs, 0, sizeof(*rq_regs)); 776 - dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param->src); 777 - extract_rq_regs(mode_lib, rq_regs, rq_param); 776 + dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, &pipe_param->src); 777 + extract_rq_regs(mode_lib, rq_regs, &rq_param); 778 778 779 779 print__rq_regs_st(mode_lib, rq_regs); 780 780 } ··· 787 787 const unsigned int pipe_idx, 788 788 display_dlg_regs_st *disp_dlg_regs, 789 789 display_ttu_regs_st *disp_ttu_regs, 790 - const display_rq_dlg_params_st rq_dlg_param, 791 - const display_dlg_sys_params_st dlg_sys_param, 790 + const display_rq_dlg_params_st *rq_dlg_param, 791 + const display_dlg_sys_params_st *dlg_sys_param, 792 792 const bool cstate_en, 793 793 const bool pstate_en) 794 794 { ··· 935 935 * (double) ref_freq_to_pix_freq); 936 936 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); 937 937 938 - min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; 938 + min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; 939 939 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); 940 940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 941 941 ··· 995 995 // vinit_bot_l = scl.vinit_bot; 996 996 // vinit_bot_c = scl.vinit_bot_c; 997 997 998 - // unsigned int swath_height_l = rq_dlg_param.rq_l.swath_height; 999 - swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; 1000 - // unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub; 1001 - dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; 1002 - // unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub; 1003 - // unsigned int meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub; 998 + // unsigned int swath_height_l = rq_dlg_param->rq_l.swath_height; 999 + swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub; 1000 + // unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param->rq_l.dpte_bytes_per_row_ub; 1001 + dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub; 1002 + // unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param->rq_l.meta_pte_bytes_per_frame_ub; 1003 + // unsigned int meta_bytes_per_row_ub_l = rq_dlg_param->rq_l.meta_bytes_per_row_ub; 1004 1004 1005 - // unsigned int swath_height_c = rq_dlg_param.rq_c.swath_height; 1006 - swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; 1007 - // dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub; 1008 - dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; 1005 + // unsigned int swath_height_c = rq_dlg_param->rq_c.swath_height; 1006 + swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub; 1007 + // dpte_bytes_per_row_ub_c = rq_dlg_param->rq_c.dpte_bytes_per_row_ub; 1008 + dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub; 1009 1009 1010 - meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; 1011 - meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; 1010 + meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub; 1011 + meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub; 1012 1012 vupdate_offset = dst->vupdate_offset; 1013 1013 vupdate_width = dst->vupdate_width; 1014 1014 vready_offset = dst->vready_offset; ··· 1137 1137 dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c); 1138 1138 1139 1139 // Active 1140 - req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; 1141 - req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; 1142 - meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; 1143 - meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; 1140 + req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub; 1141 + req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub; 1142 + meta_row_height_l = rq_dlg_param->rq_l.meta_row_height; 1143 + meta_row_height_c = rq_dlg_param->rq_c.meta_row_height; 1144 1144 swath_width_pixels_ub_l = 0; 1145 1145 swath_width_pixels_ub_c = 0; 1146 1146 scaler_rec_in_width_l = 0; 1147 1147 scaler_rec_in_width_c = 0; 1148 - dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; 1149 - dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; 1148 + dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; 1149 + dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; 1150 1150 1151 1151 if (mode_422) { 1152 1152 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element ··· 1584 1584 // system parameter calculation done 1585 1585 1586 1586 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); 1587 - dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src); 1587 + dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe.src); 1588 1588 dml20_rq_dlg_get_dlg_params(mode_lib, 1589 1589 e2e_pipe_param, 1590 1590 num_pipes, 1591 1591 pipe_idx, 1592 1592 dlg_regs, 1593 1593 ttu_regs, 1594 - rq_param.dlg, 1595 - dlg_sys_param, 1594 + &rq_param.dlg, 1595 + &dlg_sys_param, 1596 1596 cstate_en, 1597 1597 pstate_en); 1598 1598 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);

+62 -62

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

··· 38 38 static void dml20v2_rq_dlg_get_rq_params( 39 39 struct display_mode_lib *mode_lib, 40 40 display_rq_params_st * rq_param, 41 - const display_pipe_source_params_st pipe_src_param); 41 + const display_pipe_source_params_st *pipe_src_param); 42 42 43 43 // Function: dml20v2_rq_dlg_get_dlg_params 44 44 // Calculate deadline related parameters ··· 49 49 const unsigned int pipe_idx, 50 50 display_dlg_regs_st *disp_dlg_regs, 51 51 display_ttu_regs_st *disp_ttu_regs, 52 - const display_rq_dlg_params_st rq_dlg_param, 53 - const display_dlg_sys_params_st dlg_sys_param, 52 + const display_rq_dlg_params_st *rq_dlg_param, 53 + const display_dlg_sys_params_st *dlg_sys_param, 54 54 const bool cstate_en, 55 55 const bool pstate_en); 56 56 /* ··· 188 188 189 189 static void extract_rq_regs(struct display_mode_lib *mode_lib, 190 190 display_rq_regs_st *rq_regs, 191 - const display_rq_params_st rq_param) 191 + const display_rq_params_st *rq_param) 192 192 { 193 193 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 194 194 unsigned int detile_buf_plane1_addr = 0; 195 195 196 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l); 196 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); 197 197 198 - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), 198 + rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 199 199 1) - 3; 200 200 201 - if (rq_param.yuv420) { 202 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c); 203 - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), 201 + if (rq_param->yuv420) { 202 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); 203 + rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 204 204 1) - 3; 205 205 } 206 206 207 - rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); 208 - rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); 207 + rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); 208 + rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); 209 209 210 210 // TODO: take the max between luma, chroma chunk size? 211 211 // okay for now, as we are setting chunk_bytes to 8kb anyways 212 - if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb 212 + if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb 213 213 rq_regs->drq_expansion_mode = 0; 214 214 } else { 215 215 rq_regs->drq_expansion_mode = 2; ··· 218 218 rq_regs->mrq_expansion_mode = 1; 219 219 rq_regs->crq_expansion_mode = 1; 220 220 221 - if (rq_param.yuv420) { 222 - if ((double) rq_param.misc.rq_l.stored_swath_bytes 223 - / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { 221 + if (rq_param->yuv420) { 222 + if ((double) rq_param->misc.rq_l.stored_swath_bytes 223 + / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { 224 224 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma 225 225 } else { 226 226 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), ··· 233 233 234 234 static void handle_det_buf_split(struct display_mode_lib *mode_lib, 235 235 display_rq_params_st *rq_param, 236 - const display_pipe_source_params_st pipe_src_param) 236 + const display_pipe_source_params_st *pipe_src_param) 237 237 { 238 238 unsigned int total_swath_bytes = 0; 239 239 unsigned int swath_bytes_l = 0; ··· 242 242 unsigned int full_swath_bytes_packed_c = 0; 243 243 bool req128_l = false; 244 244 bool req128_c = false; 245 - bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); 246 - bool surf_vert = (pipe_src_param.source_scan == dm_vert); 245 + bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 246 + bool surf_vert = (pipe_src_param->source_scan == dm_vert); 247 247 unsigned int log2_swath_height_l = 0; 248 248 unsigned int log2_swath_height_c = 0; 249 249 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; ··· 685 685 display_data_rq_sizing_params_st *rq_sizing_param, 686 686 display_data_rq_dlg_params_st *rq_dlg_param, 687 687 display_data_rq_misc_params_st *rq_misc_param, 688 - const display_pipe_source_params_st pipe_src_param, 688 + const display_pipe_source_params_st *pipe_src_param, 689 689 bool is_chroma) 690 690 { 691 691 bool mode_422 = false; ··· 697 697 698 698 // TODO check if ppe apply for both luma and chroma in 422 case 699 699 if (is_chroma) { 700 - vp_width = pipe_src_param.viewport_width_c / ppe; 701 - vp_height = pipe_src_param.viewport_height_c; 702 - data_pitch = pipe_src_param.data_pitch_c; 703 - meta_pitch = pipe_src_param.meta_pitch_c; 700 + vp_width = pipe_src_param->viewport_width_c / ppe; 701 + vp_height = pipe_src_param->viewport_height_c; 702 + data_pitch = pipe_src_param->data_pitch_c; 703 + meta_pitch = pipe_src_param->meta_pitch_c; 704 704 } else { 705 - vp_width = pipe_src_param.viewport_width / ppe; 706 - vp_height = pipe_src_param.viewport_height; 707 - data_pitch = pipe_src_param.data_pitch; 708 - meta_pitch = pipe_src_param.meta_pitch; 705 + vp_width = pipe_src_param->viewport_width / ppe; 706 + vp_height = pipe_src_param->viewport_height; 707 + data_pitch = pipe_src_param->data_pitch; 708 + meta_pitch = pipe_src_param->meta_pitch; 709 709 } 710 710 711 711 rq_sizing_param->chunk_bytes = 8192; ··· 728 728 vp_height, 729 729 data_pitch, 730 730 meta_pitch, 731 - pipe_src_param.source_format, 732 - pipe_src_param.sw_mode, 733 - pipe_src_param.macro_tile_size, 734 - pipe_src_param.source_scan, 731 + pipe_src_param->source_format, 732 + pipe_src_param->sw_mode, 733 + pipe_src_param->macro_tile_size, 734 + pipe_src_param->source_scan, 735 735 is_chroma); 736 736 } 737 737 738 738 static void dml20v2_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 739 739 display_rq_params_st *rq_param, 740 - const display_pipe_source_params_st pipe_src_param) 740 + const display_pipe_source_params_st *pipe_src_param) 741 741 { 742 742 // get param for luma surface 743 - rq_param->yuv420 = pipe_src_param.source_format == dm_420_8 744 - || pipe_src_param.source_format == dm_420_10; 745 - rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10; 743 + rq_param->yuv420 = pipe_src_param->source_format == dm_420_8 744 + || pipe_src_param->source_format == dm_420_10; 745 + rq_param->yuv420_10bpc = pipe_src_param->source_format == dm_420_10; 746 746 747 747 get_surf_rq_param(mode_lib, 748 748 &(rq_param->sizing.rq_l), ··· 751 751 pipe_src_param, 752 752 0); 753 753 754 - if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) { 754 + if (is_dual_plane((enum source_format_class)(pipe_src_param->source_format))) { 755 755 // get param for chroma surface 756 756 get_surf_rq_param(mode_lib, 757 757 &(rq_param->sizing.rq_c), ··· 773 773 display_rq_params_st rq_param = {0}; 774 774 775 775 memset(rq_regs, 0, sizeof(*rq_regs)); 776 - dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param->src); 777 - extract_rq_regs(mode_lib, rq_regs, rq_param); 776 + dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, &pipe_param->src); 777 + extract_rq_regs(mode_lib, rq_regs, &rq_param); 778 778 779 779 print__rq_regs_st(mode_lib, rq_regs); 780 780 } ··· 787 787 const unsigned int pipe_idx, 788 788 display_dlg_regs_st *disp_dlg_regs, 789 789 display_ttu_regs_st *disp_ttu_regs, 790 - const display_rq_dlg_params_st rq_dlg_param, 791 - const display_dlg_sys_params_st dlg_sys_param, 790 + const display_rq_dlg_params_st *rq_dlg_param, 791 + const display_dlg_sys_params_st *dlg_sys_param, 792 792 const bool cstate_en, 793 793 const bool pstate_en) 794 794 { ··· 935 935 * (double) ref_freq_to_pix_freq); 936 936 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); 937 937 938 - min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; 938 + min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; 939 939 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); 940 940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 941 941 ··· 996 996 // vinit_bot_l = scl.vinit_bot; 997 997 // vinit_bot_c = scl.vinit_bot_c; 998 998 999 - // unsigned int swath_height_l = rq_dlg_param.rq_l.swath_height; 1000 - swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; 1001 - // unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub; 1002 - dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; 1003 - // unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub; 1004 - // unsigned int meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub; 999 + // unsigned int swath_height_l = rq_dlg_param->rq_l.swath_height; 1000 + swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub; 1001 + // unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param->rq_l.dpte_bytes_per_row_ub; 1002 + dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub; 1003 + // unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param->rq_l.meta_pte_bytes_per_frame_ub; 1004 + // unsigned int meta_bytes_per_row_ub_l = rq_dlg_param->rq_l.meta_bytes_per_row_ub; 1005 1005 1006 - // unsigned int swath_height_c = rq_dlg_param.rq_c.swath_height; 1007 - swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; 1008 - // dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub; 1009 - dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; 1006 + // unsigned int swath_height_c = rq_dlg_param->rq_c.swath_height; 1007 + swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub; 1008 + // dpte_bytes_per_row_ub_c = rq_dlg_param->rq_c.dpte_bytes_per_row_ub; 1009 + dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub; 1010 1010 1011 - meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; 1012 - meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; 1011 + meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub; 1012 + meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub; 1013 1013 vupdate_offset = dst->vupdate_offset; 1014 1014 vupdate_width = dst->vupdate_width; 1015 1015 vready_offset = dst->vready_offset; ··· 1138 1138 dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c); 1139 1139 1140 1140 // Active 1141 - req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; 1142 - req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; 1143 - meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; 1144 - meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; 1141 + req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub; 1142 + req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub; 1143 + meta_row_height_l = rq_dlg_param->rq_l.meta_row_height; 1144 + meta_row_height_c = rq_dlg_param->rq_c.meta_row_height; 1145 1145 swath_width_pixels_ub_l = 0; 1146 1146 swath_width_pixels_ub_c = 0; 1147 1147 scaler_rec_in_width_l = 0; 1148 1148 scaler_rec_in_width_c = 0; 1149 - dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; 1150 - dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; 1149 + dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; 1150 + dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; 1151 1151 1152 1152 if (mode_422) { 1153 1153 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element ··· 1585 1585 // system parameter calculation done 1586 1586 1587 1587 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); 1588 - dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src); 1588 + dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe.src); 1589 1589 dml20v2_rq_dlg_get_dlg_params(mode_lib, 1590 1590 e2e_pipe_param, 1591 1591 num_pipes, 1592 1592 pipe_idx, 1593 1593 dlg_regs, 1594 1594 ttu_regs, 1595 - rq_param.dlg, 1596 - dlg_sys_param, 1595 + &rq_param.dlg, 1596 + &dlg_sys_param, 1597 1597 cstate_en, 1598 1598 pstate_en); 1599 1599 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);

+34 -34

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

··· 166 166 static void extract_rq_regs( 167 167 struct display_mode_lib *mode_lib, 168 168 display_rq_regs_st *rq_regs, 169 - const display_rq_params_st rq_param) 169 + const display_rq_params_st *rq_param) 170 170 { 171 171 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 172 172 unsigned int detile_buf_plane1_addr = 0; 173 173 174 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l); 174 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); 175 175 176 176 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor( 177 - dml_log2(rq_param.dlg.rq_l.dpte_row_height), 177 + dml_log2(rq_param->dlg.rq_l.dpte_row_height), 178 178 1) - 3; 179 179 180 - if (rq_param.yuv420) { 181 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c); 180 + if (rq_param->yuv420) { 181 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); 182 182 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor( 183 - dml_log2(rq_param.dlg.rq_c.dpte_row_height), 183 + dml_log2(rq_param->dlg.rq_c.dpte_row_height), 184 184 1) - 3; 185 185 } 186 186 187 - rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); 188 - rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); 187 + rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); 188 + rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); 189 189 190 190 // FIXME: take the max between luma, chroma chunk size? 191 191 // okay for now, as we are setting chunk_bytes to 8kb anyways 192 - if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb 192 + if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb 193 193 rq_regs->drq_expansion_mode = 0; 194 194 } else { 195 195 rq_regs->drq_expansion_mode = 2; ··· 198 198 rq_regs->mrq_expansion_mode = 1; 199 199 rq_regs->crq_expansion_mode = 1; 200 200 201 - if (rq_param.yuv420) { 202 - if ((double) rq_param.misc.rq_l.stored_swath_bytes 203 - / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { 201 + if (rq_param->yuv420) { 202 + if ((double) rq_param->misc.rq_l.stored_swath_bytes 203 + / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { 204 204 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma 205 205 } else { 206 206 detile_buf_plane1_addr = dml_round_to_multiple( ··· 215 215 static void handle_det_buf_split( 216 216 struct display_mode_lib *mode_lib, 217 217 display_rq_params_st *rq_param, 218 - const display_pipe_source_params_st pipe_src_param) 218 + const display_pipe_source_params_st *pipe_src_param) 219 219 { 220 220 unsigned int total_swath_bytes = 0; 221 221 unsigned int swath_bytes_l = 0; ··· 224 224 unsigned int full_swath_bytes_packed_c = 0; 225 225 bool req128_l = false; 226 226 bool req128_c = false; 227 - bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); 228 - bool surf_vert = (pipe_src_param.source_scan == dm_vert); 227 + bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 228 + bool surf_vert = (pipe_src_param->source_scan == dm_vert); 229 229 unsigned int log2_swath_height_l = 0; 230 230 unsigned int log2_swath_height_c = 0; 231 231 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; ··· 806 806 } 807 807 808 808 // calculate how to split the det buffer space between luma and chroma 809 - handle_det_buf_split(mode_lib, rq_param, pipe_param->src); 809 + handle_det_buf_split(mode_lib, rq_param, &pipe_param->src); 810 810 print__rq_params_st(mode_lib, rq_param); 811 811 } 812 812 ··· 819 819 820 820 memset(rq_regs, 0, sizeof(*rq_regs)); 821 821 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param); 822 - extract_rq_regs(mode_lib, rq_regs, rq_param); 822 + extract_rq_regs(mode_lib, rq_regs, &rq_param); 823 823 824 824 print__rq_regs_st(mode_lib, rq_regs); 825 825 } ··· 833 833 const unsigned int pipe_idx, 834 834 display_dlg_regs_st *disp_dlg_regs, 835 835 display_ttu_regs_st *disp_ttu_regs, 836 - const display_rq_dlg_params_st rq_dlg_param, 837 - const display_dlg_sys_params_st dlg_sys_param, 836 + const display_rq_dlg_params_st *rq_dlg_param, 837 + const display_dlg_sys_params_st *dlg_sys_param, 838 838 const bool cstate_en, 839 839 const bool pstate_en) 840 840 { ··· 981 981 * (double) ref_freq_to_pix_freq); 982 982 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); 983 983 984 - min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; 984 + min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; 985 985 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); 986 986 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 987 987 ··· 1042 1042 scl_enable = scl->scl_enable; 1043 1043 1044 1044 line_time_in_us = (htotal / pclk_freq_in_mhz); 1045 - swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; 1046 - dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; 1047 - swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; 1048 - dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; 1045 + swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub; 1046 + dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub; 1047 + swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub; 1048 + dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub; 1049 1049 1050 - meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; 1051 - meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; 1050 + meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub; 1051 + meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub; 1052 1052 vupdate_offset = dst->vupdate_offset; 1053 1053 vupdate_width = dst->vupdate_width; 1054 1054 vready_offset = dst->vready_offset; ··· 1189 1189 dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c); 1190 1190 1191 1191 // Active 1192 - req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; 1193 - req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; 1194 - meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; 1195 - meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; 1192 + req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub; 1193 + req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub; 1194 + meta_row_height_l = rq_dlg_param->rq_l.meta_row_height; 1195 + meta_row_height_c = rq_dlg_param->rq_c.meta_row_height; 1196 1196 swath_width_pixels_ub_l = 0; 1197 1197 swath_width_pixels_ub_c = 0; 1198 1198 scaler_rec_in_width_l = 0; 1199 1199 scaler_rec_in_width_c = 0; 1200 - dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; 1201 - dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; 1200 + dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; 1201 + dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; 1202 1202 1203 1203 if (mode_422) { 1204 1204 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element ··· 1704 1704 pipe_idx, 1705 1705 dlg_regs, 1706 1706 ttu_regs, 1707 - rq_param.dlg, 1708 - dlg_sys_param, 1707 + &rq_param.dlg, 1708 + &dlg_sys_param, 1709 1709 cstate_en, 1710 1710 pstate_en); 1711 1711 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);

+17 -17

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

··· 113 113 114 114 static void extract_rq_regs(struct display_mode_lib *mode_lib, 115 115 display_rq_regs_st *rq_regs, 116 - const display_rq_params_st rq_param) 116 + const display_rq_params_st *rq_param) 117 117 { 118 118 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 119 119 unsigned int detile_buf_plane1_addr = 0; 120 120 121 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l); 121 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); 122 122 123 - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), 123 + rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 124 124 1) - 3; 125 125 126 - if (rq_param.yuv420) { 127 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c); 128 - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), 126 + if (rq_param->yuv420) { 127 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); 128 + rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 129 129 1) - 3; 130 130 } 131 131 132 - rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); 133 - rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); 132 + rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); 133 + rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); 134 134 135 135 // FIXME: take the max between luma, chroma chunk size? 136 136 // okay for now, as we are setting chunk_bytes to 8kb anyways 137 - if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param.yuv420 && rq_param.sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb 137 + if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param->yuv420 && rq_param->sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb 138 138 rq_regs->drq_expansion_mode = 0; 139 139 } else { 140 140 rq_regs->drq_expansion_mode = 2; ··· 143 143 rq_regs->mrq_expansion_mode = 1; 144 144 rq_regs->crq_expansion_mode = 1; 145 145 146 - if (rq_param.yuv420) { 147 - if ((double)rq_param.misc.rq_l.stored_swath_bytes 148 - / (double)rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { 146 + if (rq_param->yuv420) { 147 + if ((double)rq_param->misc.rq_l.stored_swath_bytes 148 + / (double)rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { 149 149 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma 150 150 } else { 151 151 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), ··· 158 158 159 159 static void handle_det_buf_split(struct display_mode_lib *mode_lib, 160 160 display_rq_params_st *rq_param, 161 - const display_pipe_source_params_st pipe_src_param) 161 + const display_pipe_source_params_st *pipe_src_param) 162 162 { 163 163 unsigned int total_swath_bytes = 0; 164 164 unsigned int swath_bytes_l = 0; ··· 167 167 unsigned int full_swath_bytes_packed_c = 0; 168 168 bool req128_l = false; 169 169 bool req128_c = false; 170 - bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); 171 - bool surf_vert = (pipe_src_param.source_scan == dm_vert); 170 + bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 171 + bool surf_vert = (pipe_src_param->source_scan == dm_vert); 172 172 unsigned int log2_swath_height_l = 0; 173 173 unsigned int log2_swath_height_c = 0; 174 174 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; ··· 871 871 } 872 872 873 873 // calculate how to split the det buffer space between luma and chroma 874 - handle_det_buf_split(mode_lib, rq_param, pipe_param->src); 874 + handle_det_buf_split(mode_lib, rq_param, &pipe_param->src); 875 875 print__rq_params_st(mode_lib, rq_param); 876 876 } 877 877 ··· 883 883 884 884 memset(rq_regs, 0, sizeof(*rq_regs)); 885 885 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param); 886 - extract_rq_regs(mode_lib, rq_regs, rq_param); 886 + extract_rq_regs(mode_lib, rq_regs, &rq_param); 887 887 888 888 print__rq_regs_st(mode_lib, rq_regs); 889 889 }

+36 -36

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

··· 196 196 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; 197 197 } 198 198 199 - static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_rq_params_st rq_param) 199 + static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_rq_params_st *rq_param) 200 200 { 201 201 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 202 202 unsigned int detile_buf_plane1_addr = 0; 203 203 204 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l); 204 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); 205 205 206 - rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), 1) - 3; 206 + rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 1) - 3; 207 207 208 - if (rq_param.yuv420) { 209 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c); 210 - rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), 1) - 3; 208 + if (rq_param->yuv420) { 209 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); 210 + rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 1) - 3; 211 211 } 212 212 213 - rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); 214 - rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); 213 + rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); 214 + rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); 215 215 216 216 // FIXME: take the max between luma, chroma chunk size? 217 217 // okay for now, as we are setting chunk_bytes to 8kb anyways 218 - if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param.yuv420 && rq_param.sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb 218 + if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param->yuv420 && rq_param->sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb 219 219 rq_regs->drq_expansion_mode = 0; 220 220 } else { 221 221 rq_regs->drq_expansion_mode = 2; ··· 225 225 rq_regs->crq_expansion_mode = 1; 226 226 227 227 // Note: detile_buf_plane1_addr is in unit of 1KB 228 - if (rq_param.yuv420) { 229 - if ((double) rq_param.misc.rq_l.stored_swath_bytes / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { 228 + if (rq_param->yuv420) { 229 + if ((double) rq_param->misc.rq_l.stored_swath_bytes / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { 230 230 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma 231 231 #ifdef __DML_RQ_DLG_CALC_DEBUG__ 232 232 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr); ··· 244 244 dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes); 245 245 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d\n", __func__, detile_buf_plane1_addr); 246 246 dml_print("DML_DLG: %s: plane1_base_address = %0d\n", __func__, rq_regs->plane1_base_address); 247 - dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param.misc.rq_l.stored_swath_bytes); 248 - dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param.misc.rq_c.stored_swath_bytes); 249 - dml_print("DML_DLG: %s: rq_l.swath_height = %0d\n", __func__, rq_param.dlg.rq_l.swath_height); 250 - dml_print("DML_DLG: %s: rq_c.swath_height = %0d\n", __func__, rq_param.dlg.rq_c.swath_height); 247 + dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_l.stored_swath_bytes); 248 + dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_c.stored_swath_bytes); 249 + dml_print("DML_DLG: %s: rq_l.swath_height = %0d\n", __func__, rq_param->dlg.rq_l.swath_height); 250 + dml_print("DML_DLG: %s: rq_c.swath_height = %0d\n", __func__, rq_param->dlg.rq_c.swath_height); 251 251 #endif 252 252 } 253 253 254 - static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_source_params_st pipe_src_param) 254 + static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_source_params_st *pipe_src_param) 255 255 { 256 256 unsigned int total_swath_bytes = 0; 257 257 unsigned int swath_bytes_l = 0; ··· 260 260 unsigned int full_swath_bytes_packed_c = 0; 261 261 bool req128_l = 0; 262 262 bool req128_c = 0; 263 - bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); 264 - bool surf_vert = (pipe_src_param.source_scan == dm_vert); 263 + bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 264 + bool surf_vert = (pipe_src_param->source_scan == dm_vert); 265 265 unsigned int log2_swath_height_l = 0; 266 266 unsigned int log2_swath_height_c = 0; 267 267 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; ··· 849 849 } 850 850 851 851 // calculate how to split the det buffer space between luma and chroma 852 - handle_det_buf_split(mode_lib, rq_param, pipe_param->src); 852 + handle_det_buf_split(mode_lib, rq_param, &pipe_param->src); 853 853 print__rq_params_st(mode_lib, rq_param); 854 854 } 855 855 ··· 859 859 860 860 memset(rq_regs, 0, sizeof(*rq_regs)); 861 861 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param); 862 - extract_rq_regs(mode_lib, rq_regs, rq_param); 862 + extract_rq_regs(mode_lib, rq_regs, &rq_param); 863 863 864 864 print__rq_regs_st(mode_lib, rq_regs); 865 865 } ··· 943 943 const unsigned int pipe_idx, 944 944 display_dlg_regs_st *disp_dlg_regs, 945 945 display_ttu_regs_st *disp_ttu_regs, 946 - const display_rq_dlg_params_st rq_dlg_param, 947 - const display_dlg_sys_params_st dlg_sys_param, 946 + const display_rq_dlg_params_st *rq_dlg_param, 947 + const display_dlg_sys_params_st *dlg_sys_param, 948 948 const bool cstate_en, 949 949 const bool pstate_en, 950 950 const bool vm_en, ··· 1112 1112 vratio_c = scl->vscl_ratio_c; 1113 1113 scl_enable = scl->scl_enable; 1114 1114 1115 - swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; 1116 - dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; 1117 - swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; 1118 - dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; 1115 + swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub; 1116 + dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub; 1117 + swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub; 1118 + dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub; 1119 1119 1120 - meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; 1121 - meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; 1120 + meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub; 1121 + meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub; 1122 1122 vupdate_offset = dst->vupdate_offset; 1123 1123 vupdate_width = dst->vupdate_width; 1124 1124 vready_offset = dst->vready_offset; ··· 1239 1239 dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c); 1240 1240 1241 1241 // Active 1242 - req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; 1243 - req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; 1244 - meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; 1245 - meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; 1242 + req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub; 1243 + req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub; 1244 + meta_row_height_l = rq_dlg_param->rq_l.meta_row_height; 1245 + meta_row_height_c = rq_dlg_param->rq_c.meta_row_height; 1246 1246 swath_width_pixels_ub_l = 0; 1247 1247 swath_width_pixels_ub_c = 0; 1248 1248 scaler_rec_in_width_l = 0; 1249 1249 scaler_rec_in_width_c = 0; 1250 - dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; 1251 - dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; 1250 + dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; 1251 + dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; 1252 1252 1253 1253 if (mode_422) { 1254 1254 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element ··· 1712 1712 pipe_idx, 1713 1713 dlg_regs, 1714 1714 ttu_regs, 1715 - rq_param.dlg, 1716 - dlg_sys_param, 1715 + &rq_param.dlg, 1716 + &dlg_sys_param, 1717 1717 cstate_en, 1718 1718 pstate_en, 1719 1719 vm_en,

+108 -108

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

··· 231 231 void dml1_extract_rq_regs( 232 232 struct display_mode_lib *mode_lib, 233 233 struct _vcs_dpi_display_rq_regs_st *rq_regs, 234 - const struct _vcs_dpi_display_rq_params_st rq_param) 234 + const struct _vcs_dpi_display_rq_params_st *rq_param) 235 235 { 236 236 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 237 237 unsigned int detile_buf_plane1_addr = 0; 238 238 239 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l); 240 - if (rq_param.yuv420) 241 - extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c); 239 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); 240 + if (rq_param->yuv420) 241 + extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); 242 242 243 - rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); 244 - rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); 243 + rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); 244 + rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); 245 245 246 246 /* TODO: take the max between luma, chroma chunk size? 247 247 * okay for now, as we are setting chunk_bytes to 8kb anyways 248 248 */ 249 - if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { /*32kb */ 249 + if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024) { /*32kb */ 250 250 rq_regs->drq_expansion_mode = 0; 251 251 } else { 252 252 rq_regs->drq_expansion_mode = 2; ··· 255 255 rq_regs->mrq_expansion_mode = 1; 256 256 rq_regs->crq_expansion_mode = 1; 257 257 258 - if (rq_param.yuv420) { 259 - if ((double) rq_param.misc.rq_l.stored_swath_bytes 260 - / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { 258 + if (rq_param->yuv420) { 259 + if ((double) rq_param->misc.rq_l.stored_swath_bytes 260 + / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { 261 261 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); /* half to chroma */ 262 262 } else { 263 263 detile_buf_plane1_addr = dml_round_to_multiple( ··· 272 272 static void handle_det_buf_split( 273 273 struct display_mode_lib *mode_lib, 274 274 struct _vcs_dpi_display_rq_params_st *rq_param, 275 - const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param) 275 + const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param) 276 276 { 277 277 unsigned int total_swath_bytes = 0; 278 278 unsigned int swath_bytes_l = 0; ··· 281 281 unsigned int full_swath_bytes_packed_c = 0; 282 282 bool req128_l = 0; 283 283 bool req128_c = 0; 284 - bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); 285 - bool surf_vert = (pipe_src_param.source_scan == dm_vert); 284 + bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 285 + bool surf_vert = (pipe_src_param->source_scan == dm_vert); 286 286 unsigned int log2_swath_height_l = 0; 287 287 unsigned int log2_swath_height_c = 0; 288 288 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; ··· 556 556 struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing_param, 557 557 struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param, 558 558 struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param, 559 - const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param, 559 + const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param, 560 560 bool is_chroma) 561 561 { 562 562 bool mode_422 = 0; ··· 622 622 623 623 /* TODO check if ppe apply for both luma and chroma in 422 case */ 624 624 if (is_chroma) { 625 - vp_width = pipe_src_param.viewport_width_c / ppe; 626 - vp_height = pipe_src_param.viewport_height_c; 627 - data_pitch = pipe_src_param.data_pitch_c; 628 - meta_pitch = pipe_src_param.meta_pitch_c; 625 + vp_width = pipe_src_param->viewport_width_c / ppe; 626 + vp_height = pipe_src_param->viewport_height_c; 627 + data_pitch = pipe_src_param->data_pitch_c; 628 + meta_pitch = pipe_src_param->meta_pitch_c; 629 629 } else { 630 - vp_width = pipe_src_param.viewport_width / ppe; 631 - vp_height = pipe_src_param.viewport_height; 632 - data_pitch = pipe_src_param.data_pitch; 633 - meta_pitch = pipe_src_param.meta_pitch; 630 + vp_width = pipe_src_param->viewport_width / ppe; 631 + vp_height = pipe_src_param->viewport_height; 632 + data_pitch = pipe_src_param->data_pitch; 633 + meta_pitch = pipe_src_param->meta_pitch; 634 634 } 635 635 636 636 rq_sizing_param->chunk_bytes = 8192; ··· 645 645 646 646 rq_sizing_param->mpte_group_bytes = 2048; 647 647 648 - surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); 649 - surf_vert = (pipe_src_param.source_scan == dm_vert); 648 + surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 649 + surf_vert = (pipe_src_param->source_scan == dm_vert); 650 650 651 651 bytes_per_element = get_bytes_per_element( 652 - (enum source_format_class) pipe_src_param.source_format, 652 + (enum source_format_class) pipe_src_param->source_format, 653 653 is_chroma); 654 654 log2_bytes_per_element = dml_log2(bytes_per_element); 655 655 blk256_width = 0; ··· 671 671 log2_blk256_height = dml_log2((double) blk256_height); 672 672 blk_bytes = 673 673 surf_linear ? 256 : get_blk_size_bytes( 674 - (enum source_macro_tile_size) pipe_src_param.macro_tile_size); 674 + (enum source_macro_tile_size) pipe_src_param->macro_tile_size); 675 675 log2_blk_bytes = dml_log2((double) blk_bytes); 676 676 log2_blk_height = 0; 677 677 log2_blk_width = 0; ··· 682 682 * "/2" is like square root 683 683 * blk is vertical biased 684 684 */ 685 - if (pipe_src_param.sw_mode != dm_sw_linear) 685 + if (pipe_src_param->sw_mode != dm_sw_linear) 686 686 log2_blk_height = log2_blk256_height 687 687 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); 688 688 else ··· 930 930 &func_meta_row_height, 931 931 vp_width, 932 932 data_pitch, 933 - pipe_src_param.source_format, 934 - pipe_src_param.sw_mode, 935 - pipe_src_param.macro_tile_size, 936 - pipe_src_param.source_scan, 933 + pipe_src_param->source_format, 934 + pipe_src_param->sw_mode, 935 + pipe_src_param->macro_tile_size, 936 + pipe_src_param->source_scan, 937 937 is_chroma); 938 938 939 939 /* Just a check to make sure this function and the new one give the same ··· 960 960 void dml1_rq_dlg_get_rq_params( 961 961 struct display_mode_lib *mode_lib, 962 962 struct _vcs_dpi_display_rq_params_st *rq_param, 963 - const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param) 963 + const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param) 964 964 { 965 965 /* get param for luma surface */ 966 - rq_param->yuv420 = pipe_src_param.source_format == dm_420_8 967 - || pipe_src_param.source_format == dm_420_10; 968 - rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10; 966 + rq_param->yuv420 = pipe_src_param->source_format == dm_420_8 967 + || pipe_src_param->source_format == dm_420_10; 968 + rq_param->yuv420_10bpc = pipe_src_param->source_format == dm_420_10; 969 969 970 970 get_surf_rq_param( 971 971 mode_lib, ··· 975 975 pipe_src_param, 976 976 0); 977 977 978 - if (is_dual_plane((enum source_format_class) pipe_src_param.source_format)) { 978 + if (is_dual_plane((enum source_format_class) pipe_src_param->source_format)) { 979 979 /* get param for chroma surface */ 980 980 get_surf_rq_param( 981 981 mode_lib, ··· 998 998 struct display_mode_lib *mode_lib, 999 999 struct _vcs_dpi_display_dlg_regs_st *disp_dlg_regs, 1000 1000 struct _vcs_dpi_display_ttu_regs_st *disp_ttu_regs, 1001 - const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param, 1002 - const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param, 1003 - const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param, 1001 + const struct _vcs_dpi_display_rq_dlg_params_st *rq_dlg_param, 1002 + const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param, 1003 + const struct _vcs_dpi_display_e2e_pipe_params_st *e2e_pipe_param, 1004 1004 const bool cstate_en, 1005 1005 const bool pstate_en, 1006 1006 const bool vm_en, 1007 1007 const bool iflip_en) 1008 1008 { 1009 1009 /* Timing */ 1010 - unsigned int htotal = e2e_pipe_param.pipe.dest.htotal; 1011 - unsigned int hblank_end = e2e_pipe_param.pipe.dest.hblank_end; 1012 - unsigned int vblank_start = e2e_pipe_param.pipe.dest.vblank_start; 1013 - unsigned int vblank_end = e2e_pipe_param.pipe.dest.vblank_end; 1014 - bool interlaced = e2e_pipe_param.pipe.dest.interlaced; 1010 + unsigned int htotal = e2e_pipe_param->pipe.dest.htotal; 1011 + unsigned int hblank_end = e2e_pipe_param->pipe.dest.hblank_end; 1012 + unsigned int vblank_start = e2e_pipe_param->pipe.dest.vblank_start; 1013 + unsigned int vblank_end = e2e_pipe_param->pipe.dest.vblank_end; 1014 + bool interlaced = e2e_pipe_param->pipe.dest.interlaced; 1015 1015 unsigned int min_vblank = mode_lib->ip.min_vblank_lines; 1016 1016 1017 - double pclk_freq_in_mhz = e2e_pipe_param.pipe.dest.pixel_rate_mhz; 1018 - double refclk_freq_in_mhz = e2e_pipe_param.clks_cfg.refclk_mhz; 1019 - double dppclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dppclk_mhz; 1020 - double dispclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dispclk_mhz; 1017 + double pclk_freq_in_mhz = e2e_pipe_param->pipe.dest.pixel_rate_mhz; 1018 + double refclk_freq_in_mhz = e2e_pipe_param->clks_cfg.refclk_mhz; 1019 + double dppclk_freq_in_mhz = e2e_pipe_param->clks_cfg.dppclk_mhz; 1020 + double dispclk_freq_in_mhz = e2e_pipe_param->clks_cfg.dispclk_mhz; 1021 1021 1022 1022 double ref_freq_to_pix_freq; 1023 1023 double prefetch_xy_calc_in_dcfclk; ··· 1160 1160 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */ 1161 1161 1162 1162 prefetch_xy_calc_in_dcfclk = 24.0; /* TODO: ip_param */ 1163 - min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; 1163 + min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; 1164 1164 t_calc_us = prefetch_xy_calc_in_dcfclk / min_dcfclk_mhz; 1165 - min_ttu_vblank = dlg_sys_param.t_urg_wm_us; 1165 + min_ttu_vblank = dlg_sys_param->t_urg_wm_us; 1166 1166 if (cstate_en) 1167 - min_ttu_vblank = dml_max(dlg_sys_param.t_sr_wm_us, min_ttu_vblank); 1167 + min_ttu_vblank = dml_max(dlg_sys_param->t_sr_wm_us, min_ttu_vblank); 1168 1168 if (pstate_en) 1169 - min_ttu_vblank = dml_max(dlg_sys_param.t_mclk_wm_us, min_ttu_vblank); 1169 + min_ttu_vblank = dml_max(dlg_sys_param->t_mclk_wm_us, min_ttu_vblank); 1170 1170 min_ttu_vblank = min_ttu_vblank + t_calc_us; 1171 1171 1172 1172 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; ··· 1197 1197 /* ------------------------- */ 1198 1198 /* Prefetch Calc */ 1199 1199 /* Source */ 1200 - dcc_en = e2e_pipe_param.pipe.src.dcc; 1200 + dcc_en = e2e_pipe_param->pipe.src.dcc; 1201 1201 dual_plane = is_dual_plane( 1202 - (enum source_format_class) e2e_pipe_param.pipe.src.source_format); 1202 + (enum source_format_class) e2e_pipe_param->pipe.src.source_format); 1203 1203 mode_422 = 0; /* TODO */ 1204 - access_dir = (e2e_pipe_param.pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */ 1204 + access_dir = (e2e_pipe_param->pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */ 1205 1205 bytes_per_element_l = get_bytes_per_element( 1206 - (enum source_format_class) e2e_pipe_param.pipe.src.source_format, 1206 + (enum source_format_class) e2e_pipe_param->pipe.src.source_format, 1207 1207 0); 1208 1208 bytes_per_element_c = get_bytes_per_element( 1209 - (enum source_format_class) e2e_pipe_param.pipe.src.source_format, 1209 + (enum source_format_class) e2e_pipe_param->pipe.src.source_format, 1210 1210 1); 1211 - vp_height_l = e2e_pipe_param.pipe.src.viewport_height; 1212 - vp_width_l = e2e_pipe_param.pipe.src.viewport_width; 1213 - vp_height_c = e2e_pipe_param.pipe.src.viewport_height_c; 1214 - vp_width_c = e2e_pipe_param.pipe.src.viewport_width_c; 1211 + vp_height_l = e2e_pipe_param->pipe.src.viewport_height; 1212 + vp_width_l = e2e_pipe_param->pipe.src.viewport_width; 1213 + vp_height_c = e2e_pipe_param->pipe.src.viewport_height_c; 1214 + vp_width_c = e2e_pipe_param->pipe.src.viewport_width_c; 1215 1215 1216 1216 /* Scaling */ 1217 - htaps_l = e2e_pipe_param.pipe.scale_taps.htaps; 1218 - htaps_c = e2e_pipe_param.pipe.scale_taps.htaps_c; 1219 - hratios_l = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio; 1220 - hratios_c = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio_c; 1221 - vratio_l = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio; 1222 - vratio_c = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio_c; 1217 + htaps_l = e2e_pipe_param->pipe.scale_taps.htaps; 1218 + htaps_c = e2e_pipe_param->pipe.scale_taps.htaps_c; 1219 + hratios_l = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio; 1220 + hratios_c = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio_c; 1221 + vratio_l = e2e_pipe_param->pipe.scale_ratio_depth.vscl_ratio; 1222 + vratio_c = e2e_pipe_param->pipe.scale_ratio_depth.vscl_ratio_c; 1223 1223 1224 1224 line_time_in_us = (htotal / pclk_freq_in_mhz); 1225 - vinit_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit; 1226 - vinit_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_c; 1227 - vinit_bot_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot; 1228 - vinit_bot_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot_c; 1225 + vinit_l = e2e_pipe_param->pipe.scale_ratio_depth.vinit; 1226 + vinit_c = e2e_pipe_param->pipe.scale_ratio_depth.vinit_c; 1227 + vinit_bot_l = e2e_pipe_param->pipe.scale_ratio_depth.vinit_bot; 1228 + vinit_bot_c = e2e_pipe_param->pipe.scale_ratio_depth.vinit_bot_c; 1229 1229 1230 - swath_height_l = rq_dlg_param.rq_l.swath_height; 1231 - swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; 1232 - dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub; 1233 - dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; 1234 - meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub; 1235 - meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub; 1230 + swath_height_l = rq_dlg_param->rq_l.swath_height; 1231 + swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub; 1232 + dpte_bytes_per_row_ub_l = rq_dlg_param->rq_l.dpte_bytes_per_row_ub; 1233 + dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub; 1234 + meta_pte_bytes_per_frame_ub_l = rq_dlg_param->rq_l.meta_pte_bytes_per_frame_ub; 1235 + meta_bytes_per_row_ub_l = rq_dlg_param->rq_l.meta_bytes_per_row_ub; 1236 1236 1237 - swath_height_c = rq_dlg_param.rq_c.swath_height; 1238 - swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; 1239 - dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub; 1240 - dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; 1237 + swath_height_c = rq_dlg_param->rq_c.swath_height; 1238 + swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub; 1239 + dpte_bytes_per_row_ub_c = rq_dlg_param->rq_c.dpte_bytes_per_row_ub; 1240 + dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub; 1241 1241 1242 - meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; 1243 - vupdate_offset = e2e_pipe_param.pipe.dest.vupdate_offset; 1244 - vupdate_width = e2e_pipe_param.pipe.dest.vupdate_width; 1245 - vready_offset = e2e_pipe_param.pipe.dest.vready_offset; 1242 + meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub; 1243 + vupdate_offset = e2e_pipe_param->pipe.dest.vupdate_offset; 1244 + vupdate_width = e2e_pipe_param->pipe.dest.vupdate_width; 1245 + vready_offset = e2e_pipe_param->pipe.dest.vready_offset; 1246 1246 1247 1247 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; 1248 1248 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; 1249 1249 pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz 1250 1250 + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; 1251 1251 1252 - vstartup_start = e2e_pipe_param.pipe.dest.vstartup_start; 1252 + vstartup_start = e2e_pipe_param->pipe.dest.vstartup_start; 1253 1253 1254 1254 if (interlaced) 1255 1255 vstartup_start = vstartup_start / 2; ··· 1276 1276 dst_x_after_scaler = 0; 1277 1277 dst_y_after_scaler = 0; 1278 1278 1279 - if (e2e_pipe_param.pipe.src.is_hsplit) 1279 + if (e2e_pipe_param->pipe.src.is_hsplit) 1280 1280 dst_x_after_scaler = pixel_rate_delay_subtotal 1281 - + e2e_pipe_param.pipe.dest.recout_width; 1281 + + e2e_pipe_param->pipe.dest.recout_width; 1282 1282 else 1283 1283 dst_x_after_scaler = pixel_rate_delay_subtotal; 1284 1284 1285 - if (e2e_pipe_param.dout.output_format == dm_420) 1285 + if (e2e_pipe_param->dout.output_format == dm_420) 1286 1286 dst_y_after_scaler = 1; 1287 1287 else 1288 1288 dst_y_after_scaler = 0; ··· 1334 1334 DTRACE( 1335 1335 "DLG: %s: t_srx_delay_us = %3.2f", 1336 1336 __func__, 1337 - (double) dlg_sys_param.t_srx_delay_us); 1337 + (double) dlg_sys_param->t_srx_delay_us); 1338 1338 DTRACE("DLG: %s: line_time_in_us = %3.2f", __func__, (double) line_time_in_us); 1339 1339 DTRACE("DLG: %s: vupdate_offset = %d", __func__, vupdate_offset); 1340 1340 DTRACE("DLG: %s: vupdate_width = %d", __func__, vupdate_width); ··· 1408 1408 DTRACE("DLG: %s: dpte_row_bytes = %d", __func__, dpte_row_bytes); 1409 1409 1410 1410 prefetch_bw = (vm_bytes + 2 * dpte_row_bytes + 2 * meta_row_bytes + sw_bytes) / t_pre_us; 1411 - flip_bw = ((vm_bytes + dpte_row_bytes + meta_row_bytes) * dlg_sys_param.total_flip_bw) 1412 - / (double) dlg_sys_param.total_flip_bytes; 1411 + flip_bw = ((vm_bytes + dpte_row_bytes + meta_row_bytes) * dlg_sys_param->total_flip_bw) 1412 + / (double) dlg_sys_param->total_flip_bytes; 1413 1413 t_vm_us = line_time_in_us / 4.0; 1414 1414 if (vm_en && dcc_en) { 1415 1415 t_vm_us = dml_max( 1416 - dlg_sys_param.t_extra_us, 1416 + dlg_sys_param->t_extra_us, 1417 1417 dml_max((double) vm_bytes / prefetch_bw, t_vm_us)); 1418 1418 1419 1419 if (iflip_en && !dual_plane) { ··· 1423 1423 } 1424 1424 } 1425 1425 1426 - t_r0_us = dml_max(dlg_sys_param.t_extra_us - t_vm_us, line_time_in_us - t_vm_us); 1426 + t_r0_us = dml_max(dlg_sys_param->t_extra_us - t_vm_us, line_time_in_us - t_vm_us); 1427 1427 1428 1428 if (vm_en || dcc_en) { 1429 1429 t_r0_us = dml_max( 1430 1430 (double) (dpte_row_bytes + meta_row_bytes) / prefetch_bw, 1431 - dlg_sys_param.t_extra_us); 1431 + dlg_sys_param->t_extra_us); 1432 1432 t_r0_us = dml_max((double) (line_time_in_us - t_vm_us), t_r0_us); 1433 1433 1434 1434 if (iflip_en && !dual_plane) { ··· 1550 1550 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */ 1551 1551 1552 1552 /* Active */ 1553 - req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; 1554 - req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; 1555 - meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; 1553 + req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub; 1554 + req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub; 1555 + meta_row_height_l = rq_dlg_param->rq_l.meta_row_height; 1556 1556 swath_width_pixels_ub_l = 0; 1557 1557 swath_width_pixels_ub_c = 0; 1558 1558 scaler_rec_in_width_l = 0; 1559 1559 scaler_rec_in_width_c = 0; 1560 - dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; 1561 - dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; 1560 + dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; 1561 + dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; 1562 1562 1563 1563 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l 1564 1564 / (double) vratio_l * dml_pow(2, 2)); ··· 1650 1650 refcyc_per_req_delivery_cur0 = 0.; 1651 1651 1652 1652 full_recout_width = 0; 1653 - if (e2e_pipe_param.pipe.src.is_hsplit) { 1654 - if (e2e_pipe_param.pipe.dest.full_recout_width == 0) { 1653 + if (e2e_pipe_param->pipe.src.is_hsplit) { 1654 + if (e2e_pipe_param->pipe.dest.full_recout_width == 0) { 1655 1655 DTRACE("DLG: %s: Warningfull_recout_width not set in hsplit mode", __func__); 1656 - full_recout_width = e2e_pipe_param.pipe.dest.recout_width * 2; /* assume half split for dcn1 */ 1656 + full_recout_width = e2e_pipe_param->pipe.dest.recout_width * 2; /* assume half split for dcn1 */ 1657 1657 } else 1658 - full_recout_width = e2e_pipe_param.pipe.dest.full_recout_width; 1658 + full_recout_width = e2e_pipe_param->pipe.dest.full_recout_width; 1659 1659 } else 1660 - full_recout_width = e2e_pipe_param.pipe.dest.recout_width; 1660 + full_recout_width = e2e_pipe_param->pipe.dest.recout_width; 1661 1661 1662 1662 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( 1663 1663 mode_lib, ··· 1824 1824 } 1825 1825 1826 1826 /* TTU - Cursor */ 1827 - hratios_cur0 = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio; 1828 - cur0_src_width = e2e_pipe_param.pipe.src.cur0_src_width; /* cursor source width */ 1829 - cur0_bpp = (enum cursor_bpp) e2e_pipe_param.pipe.src.cur0_bpp; 1827 + hratios_cur0 = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio; 1828 + cur0_src_width = e2e_pipe_param->pipe.src.cur0_src_width; /* cursor source width */ 1829 + cur0_bpp = (enum cursor_bpp) e2e_pipe_param->pipe.src.cur0_bpp; 1830 1830 cur0_req_size = 0; 1831 1831 cur0_req_width = 0; 1832 1832 cur0_width_ub = 0.0;

+5 -5

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h

··· 33 33 void dml1_extract_rq_regs( 34 34 struct display_mode_lib *mode_lib, 35 35 struct _vcs_dpi_display_rq_regs_st *rq_regs, 36 - const struct _vcs_dpi_display_rq_params_st rq_param); 36 + const struct _vcs_dpi_display_rq_params_st *rq_param); 37 37 /* Function: dml_rq_dlg_get_rq_params 38 38 * Calculate requestor related parameters that register definition agnostic 39 39 * (i.e. this layer does try to separate real values from register definition) ··· 45 45 void dml1_rq_dlg_get_rq_params( 46 46 struct display_mode_lib *mode_lib, 47 47 struct _vcs_dpi_display_rq_params_st *rq_param, 48 - const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param); 48 + const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param); 49 49 50 50 51 51 /* Function: dml_rq_dlg_get_dlg_params ··· 55 55 struct display_mode_lib *mode_lib, 56 56 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 57 57 struct _vcs_dpi_display_ttu_regs_st *ttu_regs, 58 - const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param, 59 - const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param, 60 - const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param, 58 + const struct _vcs_dpi_display_rq_dlg_params_st *rq_dlg_param, 59 + const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param, 60 + const struct _vcs_dpi_display_e2e_pipe_params_st *e2e_pipe_param, 61 61 const bool cstate_en, 62 62 const bool pstate_en, 63 63 const bool vm_en,