Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

dt-bindings: mtd: Standardize the style in the examples

As recently requested by the binding maintaines, let's use 4 spaces in
the examples.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-mtd/20221114090315.848208-18-miquel.raynal@bootlin.com

+255 -254
+15 -15
Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml
··· 34 34 examples: 35 35 - | 36 36 smcc: memory-controller@e000e000 { 37 - compatible = "arm,pl353-smc-r2p1", "arm,primecell"; 38 - reg = <0xe000e000 0x0001000>; 39 - clock-names = "memclk", "apb_pclk"; 40 - clocks = <&clkc 11>, <&clkc 44>; 41 - ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 42 - 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 43 - 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ 44 - #address-cells = <2>; 45 - #size-cells = <1>; 37 + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; 38 + reg = <0xe000e000 0x0001000>; 39 + clock-names = "memclk", "apb_pclk"; 40 + clocks = <&clkc 11>, <&clkc 44>; 41 + ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 42 + 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 43 + 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ 44 + #address-cells = <2>; 45 + #size-cells = <1>; 46 46 47 - nfc0: nand-controller@0,0 { 48 - compatible = "arm,pl353-nand-r2p1"; 49 - reg = <0 0 0x1000000>; 50 - #address-cells = <1>; 51 - #size-cells = <0>; 52 - }; 47 + nfc0: nand-controller@0,0 { 48 + compatible = "arm,pl353-nand-r2p1"; 49 + reg = <0 0 0x1000000>; 50 + #address-cells = <1>; 51 + #size-cells = <0>; 52 + }; 53 53 };
+40 -40
Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml
··· 184 184 examples: 185 185 - | 186 186 nand-controller@f0442800 { 187 - compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand"; 188 - reg = <0xf0442800 0x600>, 189 - <0xf0443000 0x100>; 190 - reg-names = "nand", "flash-dma"; 191 - interrupt-parent = <&hif_intr2_intc>; 192 - interrupts = <24>, <4>; 187 + compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand"; 188 + reg = <0xf0442800 0x600>, 189 + <0xf0443000 0x100>; 190 + reg-names = "nand", "flash-dma"; 191 + interrupt-parent = <&hif_intr2_intc>; 192 + interrupts = <24>, <4>; 193 + 194 + #address-cells = <1>; 195 + #size-cells = <0>; 196 + 197 + nand@1 { 198 + compatible = "brcm,nandcs"; 199 + reg = <1>; // Chip select 1 200 + nand-on-flash-bbt; 201 + nand-ecc-strength = <12>; 202 + nand-ecc-step-size = <512>; 193 203 194 204 #address-cells = <1>; 195 - #size-cells = <0>; 196 - 197 - nand@1 { 198 - compatible = "brcm,nandcs"; 199 - reg = <1>; // Chip select 1 200 - nand-on-flash-bbt; 201 - nand-ecc-strength = <12>; 202 - nand-ecc-step-size = <512>; 203 - 204 - #address-cells = <1>; 205 - #size-cells = <1>; 206 - }; 205 + #size-cells = <1>; 206 + }; 207 207 }; 208 208 - | 209 209 nand-controller@10000200 { 210 - compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368", 211 - "brcm,brcmnand-v4.0", "brcm,brcmnand"; 212 - reg = <0x10000200 0x180>, 213 - <0x100000b0 0x10>, 214 - <0x10000600 0x200>; 215 - reg-names = "nand", "nand-int-base", "nand-cache"; 216 - interrupt-parent = <&periph_intc>; 217 - interrupts = <50>; 218 - clocks = <&periph_clk 20>; 219 - clock-names = "nand"; 210 + compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368", 211 + "brcm,brcmnand-v4.0", "brcm,brcmnand"; 212 + reg = <0x10000200 0x180>, 213 + <0x100000b0 0x10>, 214 + <0x10000600 0x200>; 215 + reg-names = "nand", "nand-int-base", "nand-cache"; 216 + interrupt-parent = <&periph_intc>; 217 + interrupts = <50>; 218 + clocks = <&periph_clk 20>; 219 + clock-names = "nand"; 220 + 221 + #address-cells = <1>; 222 + #size-cells = <0>; 223 + 224 + nand@0 { 225 + compatible = "brcm,nandcs"; 226 + reg = <0>; 227 + nand-on-flash-bbt; 228 + nand-ecc-strength = <1>; 229 + nand-ecc-step-size = <512>; 220 230 221 231 #address-cells = <1>; 222 - #size-cells = <0>; 223 - 224 - nand@0 { 225 - compatible = "brcm,nandcs"; 226 - reg = <0>; 227 - nand-on-flash-bbt; 228 - nand-ecc-strength = <1>; 229 - nand-ecc-step-size = <512>; 230 - 231 - #address-cells = <1>; 232 - #size-cells = <1>; 233 - }; 232 + #size-cells = <1>; 233 + }; 234 234 };
+1 -1
Documentation/devicetree/bindings/mtd/denali,nand.yaml
··· 145 145 #size-cells = <0>; 146 146 147 147 nand@0 { 148 - reg = <0>; 148 + reg = <0>; 149 149 }; 150 150 };
+61 -61
Documentation/devicetree/bindings/mtd/ingenic,nand.yaml
··· 58 58 - | 59 59 #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 60 60 memory-controller@13410000 { 61 - compatible = "ingenic,jz4780-nemc"; 62 - reg = <0x13410000 0x10000>; 63 - #address-cells = <2>; 64 - #size-cells = <1>; 65 - ranges = <1 0 0x1b000000 0x1000000>, 66 - <2 0 0x1a000000 0x1000000>, 67 - <3 0 0x19000000 0x1000000>, 68 - <4 0 0x18000000 0x1000000>, 69 - <5 0 0x17000000 0x1000000>, 70 - <6 0 0x16000000 0x1000000>; 61 + compatible = "ingenic,jz4780-nemc"; 62 + reg = <0x13410000 0x10000>; 63 + #address-cells = <2>; 64 + #size-cells = <1>; 65 + ranges = <1 0 0x1b000000 0x1000000>, 66 + <2 0 0x1a000000 0x1000000>, 67 + <3 0 0x19000000 0x1000000>, 68 + <4 0 0x18000000 0x1000000>, 69 + <5 0 0x17000000 0x1000000>, 70 + <6 0 0x16000000 0x1000000>; 71 71 72 - clocks = <&cgu JZ4780_CLK_NEMC>; 72 + clocks = <&cgu JZ4780_CLK_NEMC>; 73 73 74 - nand-controller@1 { 75 - compatible = "ingenic,jz4780-nand"; 76 - reg = <1 0 0x1000000>; 74 + nand-controller@1 { 75 + compatible = "ingenic,jz4780-nand"; 76 + reg = <1 0 0x1000000>; 77 77 78 - #address-cells = <1>; 79 - #size-cells = <0>; 78 + #address-cells = <1>; 79 + #size-cells = <0>; 80 80 81 - ecc-engine = <&bch>; 81 + ecc-engine = <&bch>; 82 82 83 - ingenic,nemc-tAS = <10>; 84 - ingenic,nemc-tAH = <5>; 85 - ingenic,nemc-tBP = <10>; 86 - ingenic,nemc-tAW = <15>; 87 - ingenic,nemc-tSTRV = <100>; 83 + ingenic,nemc-tAS = <10>; 84 + ingenic,nemc-tAH = <5>; 85 + ingenic,nemc-tBP = <10>; 86 + ingenic,nemc-tAW = <15>; 87 + ingenic,nemc-tSTRV = <100>; 88 88 89 - pinctrl-names = "default"; 90 - pinctrl-0 = <&pins_nemc>; 89 + pinctrl-names = "default"; 90 + pinctrl-0 = <&pins_nemc>; 91 91 92 - nand@1 { 93 - reg = <1>; 92 + nand@1 { 93 + reg = <1>; 94 94 95 - nand-ecc-step-size = <1024>; 96 - nand-ecc-strength = <24>; 97 - nand-ecc-mode = "hw"; 98 - nand-on-flash-bbt; 95 + nand-ecc-step-size = <1024>; 96 + nand-ecc-strength = <24>; 97 + nand-ecc-mode = "hw"; 98 + nand-on-flash-bbt; 99 99 100 - pinctrl-names = "default"; 101 - pinctrl-0 = <&pins_nemc_cs1>; 100 + pinctrl-names = "default"; 101 + pinctrl-0 = <&pins_nemc_cs1>; 102 102 103 - partitions { 104 - compatible = "fixed-partitions"; 105 - #address-cells = <2>; 106 - #size-cells = <2>; 103 + partitions { 104 + compatible = "fixed-partitions"; 105 + #address-cells = <2>; 106 + #size-cells = <2>; 107 107 108 - partition@0 { 109 - label = "u-boot-spl"; 110 - reg = <0x0 0x0 0x0 0x800000>; 108 + partition@0 { 109 + label = "u-boot-spl"; 110 + reg = <0x0 0x0 0x0 0x800000>; 111 + }; 112 + 113 + partition@800000 { 114 + label = "u-boot"; 115 + reg = <0x0 0x800000 0x0 0x200000>; 116 + }; 117 + 118 + partition@a00000 { 119 + label = "u-boot-env"; 120 + reg = <0x0 0xa00000 0x0 0x200000>; 121 + }; 122 + 123 + partition@c00000 { 124 + label = "boot"; 125 + reg = <0x0 0xc00000 0x0 0x4000000>; 126 + }; 127 + 128 + partition@4c00000 { 129 + label = "system"; 130 + reg = <0x0 0x4c00000 0x1 0xfb400000>; 131 + }; 132 + }; 111 133 }; 112 - 113 - partition@800000 { 114 - label = "u-boot"; 115 - reg = <0x0 0x800000 0x0 0x200000>; 116 - }; 117 - 118 - partition@a00000 { 119 - label = "u-boot-env"; 120 - reg = <0x0 0xa00000 0x0 0x200000>; 121 - }; 122 - 123 - partition@c00000 { 124 - label = "boot"; 125 - reg = <0x0 0xc00000 0x0 0x4000000>; 126 - }; 127 - 128 - partition@4c00000 { 129 - label = "system"; 130 - reg = <0x0 0x4c00000 0x1 0xfb400000>; 131 - }; 132 - }; 133 134 }; 134 - }; 135 135 };
+18 -18
Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml
··· 67 67 examples: 68 68 - | 69 69 nand-controller@e0f00000 { 70 - compatible = "intel,lgm-ebunand"; 71 - reg = <0xe0f00000 0x100>, 72 - <0xe1000000 0x300>, 73 - <0xe1400000 0x8000>, 74 - <0xe1c00000 0x1000>, 75 - <0x17400000 0x4>, 76 - <0x17c00000 0x4>; 77 - reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", 78 - "addr_sel0", "addr_sel1"; 79 - clocks = <&cgu0 125>; 80 - dmas = <&dma0 8>, <&dma0 9>; 81 - dma-names = "tx", "rx"; 82 - #address-cells = <1>; 83 - #size-cells = <0>; 70 + compatible = "intel,lgm-ebunand"; 71 + reg = <0xe0f00000 0x100>, 72 + <0xe1000000 0x300>, 73 + <0xe1400000 0x8000>, 74 + <0xe1c00000 0x1000>, 75 + <0x17400000 0x4>, 76 + <0x17c00000 0x4>; 77 + reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", 78 + "addr_sel0", "addr_sel1"; 79 + clocks = <&cgu0 125>; 80 + dmas = <&dma0 8>, <&dma0 9>; 81 + dma-names = "tx", "rx"; 82 + #address-cells = <1>; 83 + #size-cells = <0>; 84 84 85 - nand@0 { 86 - reg = <0>; 87 - nand-ecc-mode = "hw"; 88 - }; 85 + nand@0 { 86 + reg = <0>; 87 + nand-ecc-mode = "hw"; 88 + }; 89 89 }; 90 90 91 91 ...
+7 -7
Documentation/devicetree/bindings/mtd/microchip,mchp48l640.yaml
··· 34 34 examples: 35 35 - | 36 36 spi { 37 - #address-cells = <1>; 38 - #size-cells = <0>; 37 + #address-cells = <1>; 38 + #size-cells = <0>; 39 39 40 - eeram@0 { 41 - compatible = "microchip,48l640"; 42 - reg = <0>; 43 - spi-max-frequency = <20000000>; 44 - }; 40 + eeram@0 { 41 + compatible = "microchip,48l640"; 42 + reg = <0>; 43 + spi-max-frequency = <20000000>; 44 + }; 45 45 }; 46 46 ...
+14 -14
Documentation/devicetree/bindings/mtd/partitions/qcom,smem-part.yaml
··· 41 41 - | 42 42 /* Example declaring dynamic partition */ 43 43 flash { 44 - partitions { 45 - compatible = "qcom,smem-part"; 44 + partitions { 45 + compatible = "qcom,smem-part"; 46 46 47 - partition-art { 48 - compatible = "nvmem-cells"; 49 - #address-cells = <1>; 50 - #size-cells = <1>; 51 - label = "0:art"; 47 + partition-art { 48 + compatible = "nvmem-cells"; 49 + #address-cells = <1>; 50 + #size-cells = <1>; 51 + label = "0:art"; 52 52 53 - macaddr_art_0: macaddr@0 { 54 - reg = <0x0 0x6>; 55 - }; 53 + macaddr_art_0: macaddr@0 { 54 + reg = <0x0 0x6>; 55 + }; 56 56 57 - macaddr_art_6: macaddr@6 { 58 - reg = <0x6 0x6>; 59 - }; 57 + macaddr_art_6: macaddr@6 { 58 + reg = <0x6 0x6>; 59 + }; 60 + }; 60 61 }; 61 - }; 62 62 };
+57 -57
Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
··· 136 136 - | 137 137 #include <dt-bindings/clock/qcom,gcc-ipq806x.h> 138 138 nand-controller@1ac00000 { 139 - compatible = "qcom,ipq806x-nand"; 140 - reg = <0x1ac00000 0x800>; 139 + compatible = "qcom,ipq806x-nand"; 140 + reg = <0x1ac00000 0x800>; 141 141 142 - clocks = <&gcc EBI2_CLK>, 143 - <&gcc EBI2_AON_CLK>; 144 - clock-names = "core", "aon"; 142 + clocks = <&gcc EBI2_CLK>, 143 + <&gcc EBI2_AON_CLK>; 144 + clock-names = "core", "aon"; 145 145 146 - dmas = <&adm_dma 3>; 147 - dma-names = "rxtx"; 148 - qcom,cmd-crci = <15>; 149 - qcom,data-crci = <3>; 146 + dmas = <&adm_dma 3>; 147 + dma-names = "rxtx"; 148 + qcom,cmd-crci = <15>; 149 + qcom,data-crci = <3>; 150 150 151 - #address-cells = <1>; 152 - #size-cells = <0>; 151 + #address-cells = <1>; 152 + #size-cells = <0>; 153 153 154 - nand@0 { 155 - reg = <0>; 154 + nand@0 { 155 + reg = <0>; 156 156 157 - nand-ecc-strength = <4>; 158 - nand-bus-width = <8>; 157 + nand-ecc-strength = <4>; 158 + nand-bus-width = <8>; 159 159 160 - qcom,boot-partitions = <0x0 0x58a0000>; 160 + qcom,boot-partitions = <0x0 0x58a0000>; 161 161 162 - partitions { 163 - compatible = "fixed-partitions"; 164 - #address-cells = <1>; 165 - #size-cells = <1>; 162 + partitions { 163 + compatible = "fixed-partitions"; 164 + #address-cells = <1>; 165 + #size-cells = <1>; 166 166 167 - partition@0 { 168 - label = "boot-nand"; 169 - reg = <0 0x58a0000>; 170 - }; 167 + partition@0 { 168 + label = "boot-nand"; 169 + reg = <0 0x58a0000>; 170 + }; 171 171 172 - partition@58a0000 { 173 - label = "fs-nand"; 174 - reg = <0x58a0000 0x4000000>; 175 - }; 172 + partition@58a0000 { 173 + label = "fs-nand"; 174 + reg = <0x58a0000 0x4000000>; 175 + }; 176 + }; 176 177 }; 177 - }; 178 178 }; 179 179 180 180 #include <dt-bindings/clock/qcom,gcc-ipq4019.h> 181 181 nand-controller@79b0000 { 182 - compatible = "qcom,ipq4019-nand"; 183 - reg = <0x79b0000 0x1000>; 182 + compatible = "qcom,ipq4019-nand"; 183 + reg = <0x79b0000 0x1000>; 184 184 185 - clocks = <&gcc GCC_QPIC_CLK>, 186 - <&gcc GCC_QPIC_AHB_CLK>; 187 - clock-names = "core", "aon"; 185 + clocks = <&gcc GCC_QPIC_CLK>, 186 + <&gcc GCC_QPIC_AHB_CLK>; 187 + clock-names = "core", "aon"; 188 188 189 - dmas = <&qpicbam 0>, 190 - <&qpicbam 1>, 191 - <&qpicbam 2>; 192 - dma-names = "tx", "rx", "cmd"; 189 + dmas = <&qpicbam 0>, 190 + <&qpicbam 1>, 191 + <&qpicbam 2>; 192 + dma-names = "tx", "rx", "cmd"; 193 193 194 - #address-cells = <1>; 195 - #size-cells = <0>; 194 + #address-cells = <1>; 195 + #size-cells = <0>; 196 196 197 - nand@0 { 198 - reg = <0>; 199 - nand-ecc-strength = <4>; 200 - nand-bus-width = <8>; 197 + nand@0 { 198 + reg = <0>; 199 + nand-ecc-strength = <4>; 200 + nand-bus-width = <8>; 201 201 202 - partitions { 203 - compatible = "fixed-partitions"; 204 - #address-cells = <1>; 205 - #size-cells = <1>; 202 + partitions { 203 + compatible = "fixed-partitions"; 204 + #address-cells = <1>; 205 + #size-cells = <1>; 206 206 207 - partition@0 { 208 - label = "boot-nand"; 209 - reg = <0 0x58a0000>; 210 - }; 207 + partition@0 { 208 + label = "boot-nand"; 209 + reg = <0 0x58a0000>; 210 + }; 211 211 212 - partition@58a0000 { 213 - label = "fs-nand"; 214 - reg = <0x58a0000 0x4000000>; 215 - }; 212 + partition@58a0000 { 213 + label = "fs-nand"; 214 + reg = <0x58a0000 0x4000000>; 215 + }; 216 + }; 216 217 }; 217 - }; 218 218 }; 219 219 220 220 ...
+24 -23
Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
··· 101 101 #include <dt-bindings/interrupt-controller/arm-gic.h> 102 102 #include <dt-bindings/clock/stm32mp1-clks.h> 103 103 #include <dt-bindings/reset/stm32mp1-resets.h> 104 - nand-controller@58002000 { 105 - compatible = "st,stm32mp15-fmc2"; 106 - reg = <0x58002000 0x1000>, 107 - <0x80000000 0x1000>, 108 - <0x88010000 0x1000>, 109 - <0x88020000 0x1000>, 110 - <0x81000000 0x1000>, 111 - <0x89010000 0x1000>, 112 - <0x89020000 0x1000>; 113 - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 114 - dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 115 - <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 116 - <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 117 - dma-names = "tx", "rx", "ecc"; 118 - clocks = <&rcc FMC_K>; 119 - resets = <&rcc FMC_R>; 120 - #address-cells = <1>; 121 - #size-cells = <0>; 122 104 123 - nand@0 { 124 - reg = <0>; 125 - nand-on-flash-bbt; 105 + nand-controller@58002000 { 106 + compatible = "st,stm32mp15-fmc2"; 107 + reg = <0x58002000 0x1000>, 108 + <0x80000000 0x1000>, 109 + <0x88010000 0x1000>, 110 + <0x88020000 0x1000>, 111 + <0x81000000 0x1000>, 112 + <0x89010000 0x1000>, 113 + <0x89020000 0x1000>; 114 + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 115 + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 116 + <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 117 + <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 118 + dma-names = "tx", "rx", "ecc"; 119 + clocks = <&rcc FMC_K>; 120 + resets = <&rcc FMC_R>; 126 121 #address-cells = <1>; 127 - #size-cells = <1>; 128 - }; 122 + #size-cells = <0>; 123 + 124 + nand@0 { 125 + reg = <0>; 126 + nand-on-flash-bbt; 127 + #address-cells = <1>; 128 + #size-cells = <1>; 129 + }; 129 130 }; 130 131 131 132 ...
+18 -18
Documentation/devicetree/bindings/mtd/ti,am654-hbmc.yaml
··· 44 44 examples: 45 45 - | 46 46 bus { 47 - #address-cells = <2>; 48 - #size-cells = <2>; 49 - 50 - hbmc: memory-controller@47034000 { 51 - compatible = "ti,am654-hbmc"; 52 - reg = <0x0 0x47034000 0x0 0x100>, 53 - <0x5 0x00000000 0x1 0x0000000>; 54 - ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */ 55 - <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */ 56 - clocks = <&k3_clks 102 0>; 57 47 #address-cells = <2>; 58 - #size-cells = <1>; 59 - power-domains = <&k3_pds 55>; 60 - mux-controls = <&hbmc_mux 0>; 48 + #size-cells = <2>; 61 49 62 - flash@0,0 { 63 - compatible = "cypress,hyperflash", "cfi-flash"; 64 - reg = <0x0 0x0 0x4000000>; 65 - #address-cells = <1>; 50 + hbmc: memory-controller@47034000 { 51 + compatible = "ti,am654-hbmc"; 52 + reg = <0x0 0x47034000 0x0 0x100>, 53 + <0x5 0x00000000 0x1 0x0000000>; 54 + ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */ 55 + <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */ 56 + clocks = <&k3_clks 102 0>; 57 + #address-cells = <2>; 66 58 #size-cells = <1>; 59 + power-domains = <&k3_pds 55>; 60 + mux-controls = <&hbmc_mux 0>; 61 + 62 + flash@0,0 { 63 + compatible = "cypress,hyperflash", "cfi-flash"; 64 + reg = <0x0 0x0 0x4000000>; 65 + #address-cells = <1>; 66 + #size-cells = <1>; 67 + }; 67 68 }; 68 - }; 69 69 };