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[ARM] Move FLUSH_BASE macros to asm/arch/memory.h

FLUSH_BASE must be visible to arch/arm/mm/init.c in order for the
memory region to be setup. Move these definitions from
asm-arm/arch-*/hardware.h into asm-arm/arch-*/memory.h where mm
stuff can see them.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

authored by

Russell King and committed by
Russell King 74d02fb9 7d129637

+53 -33
+4 -3
arch/arm/mm/init.c
··· 20 20 21 21 #include <asm/mach-types.h> 22 22 #include <asm/setup.h> 23 + #include <asm/sizes.h> 23 24 #include <asm/tlb.h> 24 25 25 26 #include <asm/mach/arch.h> ··· 456 455 #ifdef FLUSH_BASE 457 456 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); 458 457 map.virtual = FLUSH_BASE; 459 - map.length = PGDIR_SIZE; 458 + map.length = SZ_1M; 460 459 map.type = MT_CACHECLEAN; 461 460 create_mapping(&map); 462 461 #endif 463 462 #ifdef FLUSH_BASE_MINICACHE 464 - map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + PGDIR_SIZE); 463 + map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); 465 464 map.virtual = FLUSH_BASE_MINICACHE; 466 - map.length = PGDIR_SIZE; 465 + map.length = SZ_1M; 467 466 map.type = MT_MINICLEAN; 468 467 create_mapping(&map); 469 468 #endif
-4
include/asm-arm/arch-cl7500/hardware.h
··· 53 53 #define SCREEN_END 0xdfc00000 54 54 #define SCREEN_BASE 0xdf800000 55 55 56 - #define FLUSH_BASE 0xdf000000 57 - 58 56 #define VIDC_BASE (void __iomem *)0xe0400000 59 57 #define IOMD_BASE IOMEM(0xe0200000) 60 58 #define IOC_BASE IOMEM(0xe0200000) 61 59 #define FLOPPYDMA_BASE IOMEM(0xe002a000) 62 60 #define PCIO_BASE IOMEM(0xe0010000) 63 - 64 - #define FLUSH_BASE_PHYS 0x00000000 /* ROM */ 65 61 66 62 #define vidc_writel(val) __raw_writel(val, VIDC_BASE) 67 63
+6
include/asm-arm/arch-cl7500/memory.h
··· 26 26 #define __virt_to_bus(x) __virt_to_phys(x) 27 27 #define __bus_to_virt(x) __phys_to_virt(x) 28 28 29 + /* 30 + * Cache flushing area - ROM 31 + */ 32 + #define FLUSH_BASE_PHYS 0x00000000 33 + #define FLUSH_BASE 0xdf000000 34 + 29 35 #endif
-3
include/asm-arm/arch-ebsa110/hardware.h
··· 57 57 /* 58 58 * RAM definitions 59 59 */ 60 - #define FLUSH_BASE_PHYS 0x40000000 61 - #define FLUSH_BASE 0xdf000000 62 - 63 60 #define UNCACHEABLE_ADDR 0xff000000 /* IRQ_STAT */ 64 61 65 62 #endif
+6
include/asm-arm/arch-ebsa110/memory.h
··· 28 28 #define __virt_to_bus(x) (x) 29 29 #define __bus_to_virt(x) (x) 30 30 31 + /* 32 + * Cache flushing area - SRAM 33 + */ 34 + #define FLUSH_BASE_PHYS 0x40000000 35 + #define FLUSH_BASE 0xdf000000 36 + 31 37 #endif
-7
include/asm-arm/arch-ebsa285/hardware.h
··· 48 48 #define PCICFG0_SIZE 0x01000000 49 49 #define PCICFG0_BASE 0xfa000000 50 50 51 - #define FLUSH_SIZE 0x00100000 52 - #define FLUSH_BASE 0xf9000000 53 - 54 51 #define PCIMEM_SIZE 0x01000000 55 52 #define PCIMEM_BASE 0xf0000000 56 53 ··· 57 60 */ 58 61 #define PCIMEM_SIZE 0x80000000 59 62 #define PCIMEM_BASE 0x80000000 60 - 61 - #define FLUSH_SIZE 0x00100000 62 - #define FLUSH_BASE 0x7e000000 63 63 64 64 #define WFLUSH_SIZE 0x01000000 65 65 #define WFLUSH_BASE 0x7d000000 ··· 88 94 #define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) 89 95 #define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) 90 96 91 - #define FLUSH_BASE_PHYS 0x50000000 92 97 #define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) 93 98 94 99
+12
include/asm-arm/arch-ebsa285/memory.h
··· 49 49 #define TASK_SIZE UL(0xbf000000) 50 50 #define PAGE_OFFSET UL(0xc0000000) 51 51 52 + /* 53 + * Cache flushing area. 54 + */ 55 + #define FLUSH_BASE 0xf9000000 56 + 52 57 #elif defined(CONFIG_ARCH_CO285) 53 58 54 59 /* Task size and page offset at 1.5GB */ 55 60 #define TASK_SIZE UL(0x5f000000) 56 61 #define PAGE_OFFSET UL(0x60000000) 62 + 63 + /* 64 + * Cache flushing area. 65 + */ 66 + #define FLUSH_BASE 0x7e000000 57 67 58 68 #else 59 69 ··· 81 71 * space during mmap's. 82 72 */ 83 73 #define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3) 74 + 75 + #define FLUSH_BASE_PHYS 0x50000000 84 76 85 77 #endif
-3
include/asm-arm/arch-l7200/hardware.h
··· 52 52 #define ISA_SIZE 0x20000000 53 53 #define ISA_BASE 0xe0000000 54 54 55 - #define FLUSH_BASE_PHYS 0x40000000 /* ROM */ 56 - #define FLUSH_BASE 0xdf000000 57 - 58 55 #define PCIO_BASE IO_BASE 59 56 60 57 #endif
+6
include/asm-arm/arch-l7200/memory.h
··· 20 20 #define __virt_to_bus(x) __virt_to_phys(x) 21 21 #define __bus_to_virt(x) __phys_to_virt(x) 22 22 23 + /* 24 + * Cache flushing area - ROM 25 + */ 26 + #define FLUSH_BASE_PHYS 0x40000000 27 + #define FLUSH_BASE 0xdf000000 28 + 23 29 #endif
-3
include/asm-arm/arch-rpc/hardware.h
··· 46 46 #define SCREEN_END 0xdfc00000 47 47 #define SCREEN_BASE 0xdf800000 48 48 49 - #define FLUSH_BASE 0xdf000000 50 49 #define UNCACHEABLE_ADDR 0xdf010000 51 50 52 51 /* ··· 57 58 #define IOC_BASE IOMEM(0xe0200000) 58 59 #define PCIO_BASE IOMEM(0xe0010000) 59 60 #define FLOPPYDMA_BASE IOMEM(0xe002a000) 60 - 61 - #define FLUSH_BASE_PHYS 0x00000000 /* ROM */ 62 61 63 62 #define vidc_writel(val) __raw_writel(val, VIDC_BASE) 64 63
+6
include/asm-arm/arch-rpc/memory.h
··· 30 30 #define __virt_to_bus(x) __virt_to_phys(x) 31 31 #define __bus_to_virt(x) __phys_to_virt(x) 32 32 33 + /* 34 + * Cache flushing area - ROM 35 + */ 36 + #define FLUSH_BASE_PHYS 0x00000000 37 + #define FLUSH_BASE 0xdf000000 38 + 33 39 #endif
-4
include/asm-arm/arch-sa1100/hardware.h
··· 14 14 15 15 #include <linux/config.h> 16 16 17 - /* Flushing areas */ 18 - #define FLUSH_BASE_PHYS 0xe0000000 /* SA1100 zero bank */ 19 - #define FLUSH_BASE 0xf5000000 20 - #define FLUSH_BASE_MINICACHE 0xf5800000 21 17 #define UNCACHEABLE_ADDR 0xfa050000 22 18 23 19
+7
include/asm-arm/arch-sa1100/memory.h
··· 91 91 92 92 #endif 93 93 94 + /* 95 + * Cache flushing area - SA1100 zero bank 96 + */ 97 + #define FLUSH_BASE_PHYS 0xe0000000 98 + #define FLUSH_BASE 0xf5000000 99 + #define FLUSH_BASE_MINICACHE 0xf5100000 100 + 94 101 #endif
-6
include/asm-arm/arch-shark/hardware.h
··· 17 17 */ 18 18 #define IO_BASE 0xe0000000 19 19 20 - /* 21 - * RAM definitions 22 - */ 23 - #define FLUSH_BASE_PHYS 0x80000000 24 - 25 20 #else 26 21 27 22 #define IO_BASE 0 ··· 28 33 #define ROMCARD_SIZE 0x08000000 29 34 #define ROMCARD_START 0x10000000 30 35 31 - #define FLUSH_BASE 0xdf000000 32 36 #define PCIO_BASE 0xe0000000 33 37 34 38
+6
include/asm-arm/arch-shark/memory.h
··· 39 39 #define __virt_to_bus(x) __virt_to_phys(x) 40 40 #define __bus_to_virt(x) __phys_to_virt(x) 41 41 42 + /* 43 + * Cache flushing area 44 + */ 45 + #define FLUSH_BASE_PHYS 0x80000000 46 + #define FLUSH_BASE 0xdf000000 47 + 42 48 #endif