tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu/display: Add calcs code for DCN
Bandwidth and scaling calculations for DCN.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Harry Wentland
and committed by
Alex Deucher
74c49c7a
03ea364c
+5805
+3629
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
+3629
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
···
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "dcn_calc_auto.h"
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#include "dcn_calc_math.h"
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/*REVISION#247*/
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void scaler_settings_calculation(struct dcn_bw_internal_vars *v)
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{
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int k;
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/*scaler settings calculation*/
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+
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/*scale ratio calculation*/
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+
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for (k = 0; k <= v->number_of_active_planes - 1; k++) {
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if (v->allow_different_hratio_vratio == dcn_bw_yes) {
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if (v->source_scan[k] == dcn_bw_hor) {
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v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k];
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v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k];
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} else {
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v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k];
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v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k];
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}
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} else {
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if (v->source_scan[k] == dcn_bw_hor) {
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v->h_ratio[k] = dcn_bw_max2(
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v->viewport_width[k] / v->scaler_rec_out_width[k],
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v->viewport_height[k] / v->scaler_recout_height[k]);
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} else {
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v->h_ratio[k] = dcn_bw_max2(
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v->viewport_height[k] / v->scaler_rec_out_width[k],
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v->viewport_width[k] / v->scaler_recout_height[k]);
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}
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v->v_ratio[k] = v->h_ratio[k];
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}
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if (v->interlace_output[k] == 1.0) {
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v->v_ratio[k] = 2.0 * v->v_ratio[k];
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}
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if ((v->underscan_output[k] == 1.0)) {
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v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor;
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v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor;
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}
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}
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/*scaler taps calculation*/
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for (k = 0; k <= v->number_of_active_planes - 1; k++) {
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if (v->h_ratio[k] > 1.0) {
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v->acceptable_quality_hta_ps = dcn_bw_min2(
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v->max_hscl_taps,
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2.0 * dcn_bw_ceil2(v->h_ratio[k], 1.0));
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} else if (v->h_ratio[k] < 1.0) {
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v->acceptable_quality_hta_ps = 4.0;
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} else {
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v->acceptable_quality_hta_ps = 1.0;
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}
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if (v->ta_pscalculation == dcn_bw_override) {
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v->htaps[k] = v->override_hta_ps[k];
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} else {
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v->htaps[k] = v->acceptable_quality_hta_ps;
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}
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if (v->v_ratio[k] > 1.0) {
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v->acceptable_quality_vta_ps = dcn_bw_min2(
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v->max_vscl_taps,
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2.0 * dcn_bw_ceil2(v->v_ratio[k], 1.0));
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} else if (v->v_ratio[k] < 1.0) {
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v->acceptable_quality_vta_ps = 4.0;
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} else {
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v->acceptable_quality_vta_ps = 1.0;
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}
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if (v->ta_pscalculation == dcn_bw_override) {
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v->vtaps[k] = v->override_vta_ps[k];
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} else {
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v->vtaps[k] = v->acceptable_quality_vta_ps;
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}
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if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64
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|| v->source_pixel_format[k] == dcn_bw_rgb_sub_32
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|| v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
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v->vta_pschroma[k] = 0.0;
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v->hta_pschroma[k] = 0.0;
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} else {
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if (v->ta_pscalculation == dcn_bw_override) {
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v->vta_pschroma[k] = v->override_vta_pschroma[k];
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v->hta_pschroma[k] = v->override_hta_pschroma[k];
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} else {
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v->vta_pschroma[k] = v->acceptable_quality_vta_ps;
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v->hta_pschroma[k] = v->acceptable_quality_hta_ps;
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}
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}
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}
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}
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void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
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{
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int i, j, k;
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/*mode support, voltage state and soc configuration*/
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/*scale ratio support check*/
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v->scale_ratio_support = dcn_bw_yes;
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for (k = 0; k <= v->number_of_active_planes - 1; k++) {
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if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio
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|| v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k]
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|| (v->source_pixel_format[k] != dcn_bw_rgb_sub_64
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&& v->source_pixel_format[k] != dcn_bw_rgb_sub_32
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&& v->source_pixel_format[k] != dcn_bw_rgb_sub_16
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&& (v->h_ratio[k] / 2.0 > v->hta_pschroma[k]
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|| v->v_ratio[k] / 2.0
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> v->vta_pschroma[k]))) {
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v->scale_ratio_support = dcn_bw_no;
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}
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}
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/*source format, pixel format and scan support check*/
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v->source_format_pixel_and_scan_support = dcn_bw_yes;
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for (k = 0; k <= v->number_of_active_planes - 1; k++) {
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if ((v->source_surface_mode[k] == dcn_bw_sw_linear
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&& v->source_scan[k] != dcn_bw_hor)
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|| ((v->source_surface_mode[k] == dcn_bw_sw_4_kb_d
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|| v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x
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|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_d
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|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t
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|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x
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|| v->source_surface_mode[k] == dcn_bw_sw_var_d
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|| v->source_surface_mode[k] == dcn_bw_sw_var_d_x)
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&& v->source_pixel_format[k] != dcn_bw_rgb_sub_64)) {
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v->source_format_pixel_and_scan_support = dcn_bw_no;
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}
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}
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/*bandwidth support check*/
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for (k = 0; k <= v->number_of_active_planes - 1; k++) {
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if (v->source_scan[k] == dcn_bw_hor) {
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v->swath_width_ysingle_dpp[k] = v->viewport_width[k];
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} else {
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v->swath_width_ysingle_dpp[k] = v->viewport_height[k];
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}
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if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
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v->byte_per_pixel_in_dety[k] = 8.0;
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v->byte_per_pixel_in_detc[k] = 0.0;
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} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
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v->byte_per_pixel_in_dety[k] = 4.0;
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v->byte_per_pixel_in_detc[k] = 0.0;
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} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
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v->byte_per_pixel_in_dety[k] = 2.0;
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v->byte_per_pixel_in_detc[k] = 0.0;
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} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
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v->byte_per_pixel_in_dety[k] = 1.0;
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v->byte_per_pixel_in_detc[k] = 2.0;
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} else {
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v->byte_per_pixel_in_dety[k] = 4.0f / 3;
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v->byte_per_pixel_in_detc[k] = 8.0f / 3;
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}
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}
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v->total_read_bandwidth_consumed_gbyte_per_second = 0.0;
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for (k = 0; k <= v->number_of_active_planes - 1; k++) {
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v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k]
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* (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) * v->v_ratio[k]
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+ dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0
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* v->v_ratio[k] / 2)
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/ (v->htotal[k] / v->pixel_clock[k]);
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if (v->dcc_enable[k] == dcn_bw_yes) {
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v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
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}
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if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor
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&& (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s
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|| v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x
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|| v->source_surface_mode[k] == dcn_bw_sw_4_kb_d
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|| v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) {
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v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 64);
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} else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor
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&& (v->source_pixel_format[k] == dcn_bw_rgb_sub_64
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|| v->source_pixel_format[k] == dcn_bw_rgb_sub_32)
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&& (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s
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|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t
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|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x
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|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_d
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|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t
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|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) {
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v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
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} else if (v->pte_enable == dcn_bw_yes) {
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v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 512);
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}
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v->total_read_bandwidth_consumed_gbyte_per_second =
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v->total_read_bandwidth_consumed_gbyte_per_second
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+ v->read_bandwidth[k] / 1000.0;
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}
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v->total_write_bandwidth_consumed_gbyte_per_second = 0.0;
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for (k = 0; k <= v->number_of_active_planes - 1; k++) {
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if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
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v->write_bandwidth[k] = v->scaler_rec_out_width[k]
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/ (v->htotal[k] / v->pixel_clock[k]) * 4.0;
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} else if (v->output[k] == dcn_bw_writeback) {
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v->write_bandwidth[k] = v->scaler_rec_out_width[k]
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/ (v->htotal[k] / v->pixel_clock[k]) * 1.5;
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} else {
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v->write_bandwidth[k] = 0.0;
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}
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v->total_write_bandwidth_consumed_gbyte_per_second =
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v->total_write_bandwidth_consumed_gbyte_per_second
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+ v->write_bandwidth[k] / 1000.0;
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}
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v->total_bandwidth_consumed_gbyte_per_second =
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v->total_read_bandwidth_consumed_gbyte_per_second
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+ v->total_write_bandwidth_consumed_gbyte_per_second;
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v->dcc_enabled_in_any_plane = dcn_bw_no;
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for (k = 0; k <= v->number_of_active_planes - 1; k++) {
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if (v->dcc_enable[k] == dcn_bw_yes) {
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v->dcc_enabled_in_any_plane = dcn_bw_yes;
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}
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}
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for (i = 0; i <= number_of_states_plus_one; i++) {
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v->return_bw_todcn_per_state =
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dcn_bw_min2(
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v->return_bus_width * v->dcfclk_per_state[i],
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+
v->fabric_and_dram_bandwidth_per_state[i] * 1000.0
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* v->percent_of_ideal_drambw_received_after_urg_latency
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+
/ 100.0);
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v->return_bw_per_state[i] = v->return_bw_todcn_per_state;
241
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if (v->dcc_enabled_in_any_plane == dcn_bw_yes
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&& v->return_bw_todcn_per_state
243
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> v->dcfclk_per_state[i] * v->return_bus_width
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/ 4.0) {
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v->return_bw_per_state[i] =
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+
dcn_bw_min2(
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+
v->return_bw_per_state[i],
248
+
v->return_bw_todcn_per_state * 4.0
249
+
* (1.0
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+
- v->urgent_latency
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+
/ ((v->rob_buffer_size_in_kbyte
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+
- v->pixel_chunk_size_in_kbyte)
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+
* 1024.0
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+
/ (v->return_bw_todcn_per_state
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+
- v->dcfclk_per_state[i]
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+
* v->return_bus_width
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+
/ 4.0)
258
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+ v->urgent_latency)));
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}
260
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v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i]
261
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* v->urgent_latency
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+
/ (v->return_bw_todcn_per_state * v->urgent_latency
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+
+ (v->rob_buffer_size_in_kbyte
264
+
- v->pixel_chunk_size_in_kbyte)
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+
* 1024.0);
266
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if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0
267
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&& v->critical_point < 4.0) {
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v->return_bw_per_state[i] =
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+
dcn_bw_min2(
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+
v->return_bw_per_state[i],
271
+
dcn_bw_pow(
272
+
4.0
273
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* v->return_bw_todcn_per_state
274
+
* (v->rob_buffer_size_in_kbyte
275
+
- v->pixel_chunk_size_in_kbyte)
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+
* 1024.0
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+
* v->return_bus_width
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+
* v->dcfclk_per_state[i]
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+
* v->urgent_latency
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+
/ (v->return_bw_todcn_per_state
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+
* v->urgent_latency
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+
+ (v->rob_buffer_size_in_kbyte
283
+
- v->pixel_chunk_size_in_kbyte)
284
+
* 1024.0),
285
+
2));
286
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}
287
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v->return_bw_todcn_per_state = dcn_bw_min2(
288
+
v->return_bus_width * v->dcfclk_per_state[i],
289
+
v->fabric_and_dram_bandwidth_per_state[i] * 1000.0);
290
+
if (v->dcc_enabled_in_any_plane == dcn_bw_yes
291
+
&& v->return_bw_todcn_per_state
292
+
> v->dcfclk_per_state[i] * v->return_bus_width
293
+
/ 4.0) {
294
+
v->return_bw_per_state[i] =
295
+
dcn_bw_min2(
296
+
v->return_bw_per_state[i],
297
+
v->return_bw_todcn_per_state * 4.0
298
+
* (1.0
299
+
- v->urgent_latency
300
+
/ ((v->rob_buffer_size_in_kbyte
301
+
- v->pixel_chunk_size_in_kbyte)
302
+
* 1024.0
303
+
/ (v->return_bw_todcn_per_state
304
+
- v->dcfclk_per_state[i]
305
+
* v->return_bus_width
306
+
/ 4.0)
307
+
+ v->urgent_latency)));
308
+
}
309
+
v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i]
310
+
* v->urgent_latency
311
+
/ (v->return_bw_todcn_per_state * v->urgent_latency
312
+
+ (v->rob_buffer_size_in_kbyte
313
+
- v->pixel_chunk_size_in_kbyte)
314
+
* 1024.0);
315
+
if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0
316
+
&& v->critical_point < 4.0) {
317
+
v->return_bw_per_state[i] =
318
+
dcn_bw_min2(
319
+
v->return_bw_per_state[i],
320
+
dcn_bw_pow(
321
+
4.0
322
+
* v->return_bw_todcn_per_state
323
+
* (v->rob_buffer_size_in_kbyte
324
+
- v->pixel_chunk_size_in_kbyte)
325
+
* 1024.0
326
+
* v->return_bus_width
327
+
* v->dcfclk_per_state[i]
328
+
* v->urgent_latency
329
+
/ (v->return_bw_todcn_per_state
330
+
* v->urgent_latency
331
+
+ (v->rob_buffer_size_in_kbyte
332
+
- v->pixel_chunk_size_in_kbyte)
333
+
* 1024.0),
334
+
2));
335
+
}
336
+
}
337
+
for (i = 0; i <= number_of_states_plus_one; i++) {
338
+
if ((v->total_read_bandwidth_consumed_gbyte_per_second * 1000.0
339
+
<= v->return_bw_per_state[i])
340
+
&& (v->total_bandwidth_consumed_gbyte_per_second * 1000.0
341
+
<= v->fabric_and_dram_bandwidth_per_state[i]
342
+
* 1000.0
343
+
* v->percent_of_ideal_drambw_received_after_urg_latency
344
+
/ 100.0)) {
345
+
v->bandwidth_support[i] = dcn_bw_yes;
346
+
} else {
347
+
v->bandwidth_support[i] = dcn_bw_no;
348
+
}
349
+
}
350
+
/*writeback latency support check*/
351
+
352
+
v->writeback_latency_support = dcn_bw_yes;
353
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
354
+
if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444
355
+
&& v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])
356
+
* 4.0
357
+
> (v->writeback_luma_buffer_size
358
+
+ v->writeback_chroma_buffer_size)
359
+
* 1024.0 / v->write_back_latency) {
360
+
v->writeback_latency_support = dcn_bw_no;
361
+
} else if (v->output[k] == dcn_bw_writeback
362
+
&& v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])
363
+
> dcn_bw_min2(
364
+
v->writeback_luma_buffer_size,
365
+
2.0
366
+
* v->writeback_chroma_buffer_size)
367
+
* 1024.0 / v->write_back_latency) {
368
+
v->writeback_latency_support = dcn_bw_no;
369
+
}
370
+
}
371
+
/*re-ordering buffer support check*/
372
+
373
+
for (i = 0; i <= number_of_states_plus_one; i++) {
374
+
v->urgent_round_trip_and_out_of_order_latency_per_state[i] =
375
+
(v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk_per_state[i]
376
+
+ v->urgent_out_of_order_return_per_channel
377
+
* v->number_of_channels
378
+
/ v->return_bw_per_state[i];
379
+
if ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0
380
+
/ v->return_bw_per_state[i]
381
+
> v->urgent_round_trip_and_out_of_order_latency_per_state[i]) {
382
+
v->rob_support[i] = dcn_bw_yes;
383
+
} else {
384
+
v->rob_support[i] = dcn_bw_no;
385
+
}
386
+
}
387
+
/*display io support check*/
388
+
389
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
390
+
if (v->output[k] == dcn_bw_dp && v->dsc_capability == dcn_bw_yes) {
391
+
if (v->output_format[k] == dcn_bw_420) {
392
+
v->required_output_bw = v->pixel_clock[k] / 2.0;
393
+
} else {
394
+
v->required_output_bw = v->pixel_clock[k];
395
+
}
396
+
} else if (v->output_format[k] == dcn_bw_420) {
397
+
v->required_output_bw = v->pixel_clock[k] * 3.0 / 2.0;
398
+
} else {
399
+
v->required_output_bw = v->pixel_clock[k] * 3.0;
400
+
}
401
+
if (v->output[k] == dcn_bw_hdmi) {
402
+
v->required_phyclk[k] = v->required_output_bw / 3.0;
403
+
} else if (v->output[k] == dcn_bw_dp) {
404
+
v->required_phyclk[k] = v->required_output_bw / 4.0;
405
+
} else {
406
+
v->required_phyclk[k] = 0.0;
407
+
}
408
+
}
409
+
for (i = 0; i <= number_of_states_plus_one; i++) {
410
+
v->dio_support[i] = dcn_bw_yes;
411
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
412
+
if (v->required_phyclk[k] > v->phyclk_per_state[i]
413
+
|| (v->output[k] == dcn_bw_hdmi
414
+
&& v->required_phyclk[k] > 600.0)) {
415
+
v->dio_support[i] = dcn_bw_no;
416
+
}
417
+
}
418
+
}
419
+
/*total available writeback support check*/
420
+
421
+
v->total_number_of_active_writeback = 0.0;
422
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
423
+
if (v->output[k] == dcn_bw_writeback) {
424
+
v->total_number_of_active_writeback = v->total_number_of_active_writeback
425
+
+ 1.0;
426
+
}
427
+
}
428
+
if (v->total_number_of_active_writeback <= v->max_num_writeback) {
429
+
v->total_available_writeback_support = dcn_bw_yes;
430
+
} else {
431
+
v->total_available_writeback_support = dcn_bw_no;
432
+
}
433
+
/*maximum dispclk/dppclk support check*/
434
+
435
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
436
+
if (v->h_ratio[k] > 1.0) {
437
+
v->pscl_factor[k] = dcn_bw_min2(
438
+
v->max_dchub_topscl_throughput,
439
+
v->max_pscl_tolb_throughput * v->h_ratio[k]
440
+
/ dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
441
+
} else {
442
+
v->pscl_factor[k] = dcn_bw_min2(
443
+
v->max_dchub_topscl_throughput,
444
+
v->max_pscl_tolb_throughput);
445
+
}
446
+
if (v->byte_per_pixel_in_detc[k] == 0.0) {
447
+
v->pscl_factor_chroma[k] = 0.0;
448
+
v->min_dppclk_using_single_dpp[k] =
449
+
v->pixel_clock[k]
450
+
* dcn_bw_max3(
451
+
v->vtaps[k] / 6.0
452
+
* dcn_bw_min2(
453
+
1.0,
454
+
v->h_ratio[k]),
455
+
v->h_ratio[k]
456
+
* v->v_ratio[k]
457
+
/ v->pscl_factor[k],
458
+
1.0);
459
+
} else {
460
+
if (v->h_ratio[k] / 2.0 > 1.0) {
461
+
v->pscl_factor_chroma[k] =
462
+
dcn_bw_min2(
463
+
v->max_dchub_topscl_throughput,
464
+
v->max_pscl_tolb_throughput
465
+
* v->h_ratio[k]
466
+
/ 2.0
467
+
/ dcn_bw_ceil2(
468
+
v->hta_pschroma[k]
469
+
/ 6.0,
470
+
1.0));
471
+
} else {
472
+
v->pscl_factor_chroma[k] = dcn_bw_min2(
473
+
v->max_dchub_topscl_throughput,
474
+
v->max_pscl_tolb_throughput);
475
+
}
476
+
v->min_dppclk_using_single_dpp[k] =
477
+
v->pixel_clock[k]
478
+
* dcn_bw_max5(
479
+
v->vtaps[k] / 6.0
480
+
* dcn_bw_min2(
481
+
1.0,
482
+
v->h_ratio[k]),
483
+
v->h_ratio[k]
484
+
* v->v_ratio[k]
485
+
/ v->pscl_factor[k],
486
+
v->vta_pschroma[k] / 6.0
487
+
* dcn_bw_min2(
488
+
1.0,
489
+
v->h_ratio[k]
490
+
/ 2.0),
491
+
v->h_ratio[k]
492
+
* v->v_ratio[k]
493
+
/ 4.0
494
+
/ v->pscl_factor_chroma[k],
495
+
1.0);
496
+
}
497
+
}
498
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
499
+
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64
500
+
|| v->source_pixel_format[k] == dcn_bw_rgb_sub_32
501
+
|| v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
502
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
503
+
v->read256_block_height_y[k] = 1.0;
504
+
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
505
+
v->read256_block_height_y[k] = 4.0;
506
+
} else {
507
+
v->read256_block_height_y[k] = 8.0;
508
+
}
509
+
v->read256_block_width_y[k] = 256.0
510
+
/ dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0)
511
+
/ v->read256_block_height_y[k];
512
+
v->read256_block_height_c[k] = 0.0;
513
+
v->read256_block_width_c[k] = 0.0;
514
+
} else {
515
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
516
+
v->read256_block_height_y[k] = 1.0;
517
+
v->read256_block_height_c[k] = 1.0;
518
+
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
519
+
v->read256_block_height_y[k] = 16.0;
520
+
v->read256_block_height_c[k] = 8.0;
521
+
} else {
522
+
v->read256_block_height_y[k] = 8.0;
523
+
v->read256_block_height_c[k] = 8.0;
524
+
}
525
+
v->read256_block_width_y[k] = 256.0
526
+
/ dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0)
527
+
/ v->read256_block_height_y[k];
528
+
v->read256_block_width_c[k] = 256.0
529
+
/ dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0)
530
+
/ v->read256_block_height_c[k];
531
+
}
532
+
if (v->source_scan[k] == dcn_bw_hor) {
533
+
v->max_swath_height_y[k] = v->read256_block_height_y[k];
534
+
v->max_swath_height_c[k] = v->read256_block_height_c[k];
535
+
} else {
536
+
v->max_swath_height_y[k] = v->read256_block_width_y[k];
537
+
v->max_swath_height_c[k] = v->read256_block_width_c[k];
538
+
}
539
+
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64
540
+
|| v->source_pixel_format[k] == dcn_bw_rgb_sub_32
541
+
|| v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
542
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear
543
+
|| (v->source_pixel_format[k] == dcn_bw_rgb_sub_64
544
+
&& (v->source_surface_mode[k]
545
+
== dcn_bw_sw_4_kb_s
546
+
|| v->source_surface_mode[k]
547
+
== dcn_bw_sw_4_kb_s_x
548
+
|| v->source_surface_mode[k]
549
+
== dcn_bw_sw_64_kb_s
550
+
|| v->source_surface_mode[k]
551
+
== dcn_bw_sw_64_kb_s_t
552
+
|| v->source_surface_mode[k]
553
+
== dcn_bw_sw_64_kb_s_x
554
+
|| v->source_surface_mode[k]
555
+
== dcn_bw_sw_var_s
556
+
|| v->source_surface_mode[k]
557
+
== dcn_bw_sw_var_s_x)
558
+
&& v->source_scan[k] == dcn_bw_hor)) {
559
+
v->min_swath_height_y[k] = v->max_swath_height_y[k];
560
+
} else {
561
+
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
562
+
}
563
+
v->min_swath_height_c[k] = v->max_swath_height_c[k];
564
+
} else {
565
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
566
+
v->min_swath_height_y[k] = v->max_swath_height_y[k];
567
+
v->min_swath_height_c[k] = v->max_swath_height_c[k];
568
+
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8
569
+
&& v->source_scan[k] == dcn_bw_hor) {
570
+
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
571
+
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed
572
+
== dcn_bw_yes) {
573
+
v->min_swath_height_c[k] = v->max_swath_height_c[k];
574
+
} else {
575
+
v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
576
+
}
577
+
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10
578
+
&& v->source_scan[k] == dcn_bw_hor) {
579
+
v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
580
+
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed
581
+
== dcn_bw_yes) {
582
+
v->min_swath_height_y[k] = v->max_swath_height_y[k];
583
+
} else {
584
+
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
585
+
}
586
+
} else {
587
+
v->min_swath_height_y[k] = v->max_swath_height_y[k];
588
+
v->min_swath_height_c[k] = v->max_swath_height_c[k];
589
+
}
590
+
}
591
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
592
+
v->maximum_swath_width = 8192.0;
593
+
} else {
594
+
v->maximum_swath_width = 5120.0;
595
+
}
596
+
v->number_of_dpp_required_for_det_size =
597
+
dcn_bw_ceil2(
598
+
v->swath_width_ysingle_dpp[k]
599
+
/ dcn_bw_min2(
600
+
v->maximum_swath_width,
601
+
v->det_buffer_size_in_kbyte
602
+
* 1024.0
603
+
/ 2.0
604
+
/ (v->byte_per_pixel_in_dety[k]
605
+
* v->min_swath_height_y[k]
606
+
+ v->byte_per_pixel_in_detc[k]
607
+
/ 2.0
608
+
* v->min_swath_height_c[k])),
609
+
1.0);
610
+
if (v->byte_per_pixel_in_detc[k] == 0.0) {
611
+
v->number_of_dpp_required_for_lb_size = dcn_bw_ceil2(
612
+
(v->vtaps[k]
613
+
+ dcn_bw_max2(
614
+
dcn_bw_ceil2(v->v_ratio[k], 1.0)
615
+
- 2,
616
+
0.0))
617
+
* v->swath_width_ysingle_dpp[k]
618
+
/ dcn_bw_max2(v->h_ratio[k], 1.0)
619
+
* v->lb_bit_per_pixel[k]
620
+
/ v->line_buffer_size,
621
+
1.0);
622
+
} else {
623
+
v->number_of_dpp_required_for_lb_size =
624
+
dcn_bw_max2(
625
+
dcn_bw_ceil2(
626
+
(v->vtaps[k]
627
+
+ dcn_bw_max2(
628
+
dcn_bw_ceil2(
629
+
v->v_ratio[k],
630
+
1.0)
631
+
- 2,
632
+
0.0))
633
+
* v->swath_width_ysingle_dpp[k]
634
+
/ dcn_bw_max2(
635
+
v->h_ratio[k],
636
+
1.0)
637
+
* v->lb_bit_per_pixel[k]
638
+
/ v->line_buffer_size,
639
+
1.0),
640
+
dcn_bw_ceil2(
641
+
(v->vta_pschroma[k]
642
+
+ dcn_bw_max2(
643
+
dcn_bw_ceil2(
644
+
v->v_ratio[k]
645
+
/ 2.0,
646
+
1.0)
647
+
- 2,
648
+
0.0))
649
+
* v->swath_width_ysingle_dpp[k]
650
+
/ 2.0
651
+
/ dcn_bw_max2(
652
+
v->h_ratio[k]
653
+
/ 2.0,
654
+
1.0)
655
+
* v->lb_bit_per_pixel[k]
656
+
/ v->line_buffer_size,
657
+
1.0));
658
+
}
659
+
v->number_of_dpp_required_for_det_and_lb_size[k] = dcn_bw_max2(
660
+
v->number_of_dpp_required_for_det_size,
661
+
v->number_of_dpp_required_for_lb_size);
662
+
}
663
+
for (i = 0; i <= number_of_states_plus_one; i++) {
664
+
for (j = 0; j <= 1; j++) {
665
+
v->total_number_of_active_dpp[i][j] = 0.0;
666
+
v->required_dispclk[i][j] = 0.0;
667
+
v->dispclk_dppclk_support[i][j] = dcn_bw_yes;
668
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
669
+
v->min_dispclk_using_single_dpp = dcn_bw_max2(
670
+
v->pixel_clock[k],
671
+
v->min_dppclk_using_single_dpp[k] * (j + 1))
672
+
* (1.0 + v->downspreading / 100.0);
673
+
if (v->odm_capability == dcn_bw_yes) {
674
+
v->min_dispclk_using_dual_dpp = dcn_bw_max2(
675
+
v->pixel_clock[k] / 2.0,
676
+
v->min_dppclk_using_single_dpp[k] / 2.0
677
+
* (j + 1))
678
+
* (1.0 + v->downspreading / 100.0);
679
+
} else {
680
+
v->min_dispclk_using_dual_dpp = dcn_bw_max2(
681
+
v->pixel_clock[k],
682
+
v->min_dppclk_using_single_dpp[k] / 2.0
683
+
* (j + 1))
684
+
* (1.0 + v->downspreading / 100.0);
685
+
}
686
+
if (i < number_of_states) {
687
+
v->min_dispclk_using_single_dpp =
688
+
v->min_dispclk_using_single_dpp
689
+
* (1.0
690
+
+ v->dispclk_ramping_margin
691
+
/ 100.0);
692
+
v->min_dispclk_using_dual_dpp =
693
+
v->min_dispclk_using_dual_dpp
694
+
* (1.0
695
+
+ v->dispclk_ramping_margin
696
+
/ 100.0);
697
+
}
698
+
if (v->min_dispclk_using_single_dpp
699
+
<= dcn_bw_min2(
700
+
v->max_dispclk[i],
701
+
(j + 1) * v->max_dppclk[i])
702
+
&& v->number_of_dpp_required_for_det_and_lb_size[k]
703
+
<= 1.0) {
704
+
v->no_of_dpp[i][j][k] = 1.0;
705
+
v->required_dispclk[i][j] = dcn_bw_max2(
706
+
v->required_dispclk[i][j],
707
+
v->min_dispclk_using_single_dpp);
708
+
} else if (v->min_dispclk_using_dual_dpp
709
+
<= dcn_bw_min2(
710
+
v->max_dispclk[i],
711
+
(j + 1) * v->max_dppclk[i])) {
712
+
v->no_of_dpp[i][j][k] = 2.0;
713
+
v->required_dispclk[i][j] = dcn_bw_max2(
714
+
v->required_dispclk[i][j],
715
+
v->min_dispclk_using_dual_dpp);
716
+
} else {
717
+
v->no_of_dpp[i][j][k] = 2.0;
718
+
v->required_dispclk[i][j] = dcn_bw_max2(
719
+
v->required_dispclk[i][j],
720
+
v->min_dispclk_using_dual_dpp);
721
+
v->dispclk_dppclk_support[i][j] = dcn_bw_no;
722
+
}
723
+
v->total_number_of_active_dpp[i][j] =
724
+
v->total_number_of_active_dpp[i][j]
725
+
+ v->no_of_dpp[i][j][k];
726
+
}
727
+
if (v->total_number_of_active_dpp[i][j] > v->max_num_dpp) {
728
+
v->total_number_of_active_dpp[i][j] = 0.0;
729
+
v->required_dispclk[i][j] = 0.0;
730
+
v->dispclk_dppclk_support[i][j] = dcn_bw_yes;
731
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
732
+
v->min_dispclk_using_single_dpp = dcn_bw_max2(
733
+
v->pixel_clock[k],
734
+
v->min_dppclk_using_single_dpp[k] * (j + 1))
735
+
* (1.0 + v->downspreading / 100.0);
736
+
v->min_dispclk_using_dual_dpp = dcn_bw_max2(
737
+
v->pixel_clock[k],
738
+
v->min_dppclk_using_single_dpp[k] / 2.0
739
+
* (j + 1))
740
+
* (1.0 + v->downspreading / 100.0);
741
+
if (i < number_of_states) {
742
+
v->min_dispclk_using_single_dpp =
743
+
v->min_dispclk_using_single_dpp
744
+
* (1.0
745
+
+ v->dispclk_ramping_margin
746
+
/ 100.0);
747
+
v->min_dispclk_using_dual_dpp =
748
+
v->min_dispclk_using_dual_dpp
749
+
* (1.0
750
+
+ v->dispclk_ramping_margin
751
+
/ 100.0);
752
+
}
753
+
if (v->number_of_dpp_required_for_det_and_lb_size[k]
754
+
<= 1.0) {
755
+
v->no_of_dpp[i][j][k] = 1.0;
756
+
v->required_dispclk[i][j] = dcn_bw_max2(
757
+
v->required_dispclk[i][j],
758
+
v->min_dispclk_using_single_dpp);
759
+
if (v->min_dispclk_using_single_dpp
760
+
> dcn_bw_min2(
761
+
v->max_dispclk[i],
762
+
(j + 1)
763
+
* v->max_dppclk[i])) {
764
+
v->dispclk_dppclk_support[i][j] = dcn_bw_no;
765
+
}
766
+
} else {
767
+
v->no_of_dpp[i][j][k] = 2.0;
768
+
v->required_dispclk[i][j] = dcn_bw_max2(
769
+
v->required_dispclk[i][j],
770
+
v->min_dispclk_using_dual_dpp);
771
+
if (v->min_dispclk_using_dual_dpp
772
+
> dcn_bw_min2(
773
+
v->max_dispclk[i],
774
+
(j + 1)
775
+
* v->max_dppclk[i])) {
776
+
v->dispclk_dppclk_support[i][j] = dcn_bw_no;
777
+
}
778
+
}
779
+
v->total_number_of_active_dpp[i][j] =
780
+
v->total_number_of_active_dpp[i][j]
781
+
+ v->no_of_dpp[i][j][k];
782
+
}
783
+
}
784
+
}
785
+
}
786
+
/*viewport size check*/
787
+
788
+
v->viewport_size_support = dcn_bw_yes;
789
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
790
+
if (v->number_of_dpp_required_for_det_and_lb_size[k] > 2.0) {
791
+
v->viewport_size_support = dcn_bw_no;
792
+
}
793
+
}
794
+
/*total available pipes support check*/
795
+
796
+
for (i = 0; i <= number_of_states_plus_one; i++) {
797
+
for (j = 0; j <= 1; j++) {
798
+
if (v->total_number_of_active_dpp[i][j] <= v->max_num_dpp) {
799
+
v->total_available_pipes_support[i][j] = dcn_bw_yes;
800
+
} else {
801
+
v->total_available_pipes_support[i][j] = dcn_bw_no;
802
+
}
803
+
}
804
+
}
805
+
/*urgent latency support check*/
806
+
807
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
808
+
for (i = 0; i <= number_of_states_plus_one; i++) {
809
+
for (j = 0; j <= 1; j++) {
810
+
v->swath_width_yper_state[i][j][k] = v->swath_width_ysingle_dpp[k]
811
+
/ v->no_of_dpp[i][j][k];
812
+
v->swath_width_granularity_y = 256.0
813
+
/ dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0)
814
+
/ v->max_swath_height_y[k];
815
+
v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(
816
+
v->swath_width_yper_state[i][j][k] - 1.0,
817
+
v->swath_width_granularity_y)
818
+
+ v->swath_width_granularity_y)
819
+
* v->byte_per_pixel_in_dety[k]
820
+
* v->max_swath_height_y[k];
821
+
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
822
+
v->rounded_up_max_swath_size_bytes_y = dcn_bw_ceil2(
823
+
v->rounded_up_max_swath_size_bytes_y,
824
+
256.0) + 256;
825
+
}
826
+
if (v->max_swath_height_c[k] > 0.0) {
827
+
v->swath_width_granularity_c =
828
+
256.0
829
+
/ dcn_bw_ceil2(
830
+
v->byte_per_pixel_in_detc[k],
831
+
2.0)
832
+
/ v->max_swath_height_c[k];
833
+
}
834
+
v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(
835
+
v->swath_width_yper_state[i][j][k] / 2.0 - 1.0,
836
+
v->swath_width_granularity_c)
837
+
+ v->swath_width_granularity_c)
838
+
* v->byte_per_pixel_in_detc[k]
839
+
* v->max_swath_height_c[k];
840
+
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
841
+
v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(
842
+
v->rounded_up_max_swath_size_bytes_c,
843
+
256.0) + 256;
844
+
}
845
+
if (v->rounded_up_max_swath_size_bytes_y
846
+
+ v->rounded_up_max_swath_size_bytes_c
847
+
<= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) {
848
+
v->swath_height_yper_state[i][j][k] =
849
+
v->max_swath_height_y[k];
850
+
v->swath_height_cper_state[i][j][k] =
851
+
v->max_swath_height_c[k];
852
+
} else {
853
+
v->swath_height_yper_state[i][j][k] =
854
+
v->min_swath_height_y[k];
855
+
v->swath_height_cper_state[i][j][k] =
856
+
v->min_swath_height_c[k];
857
+
}
858
+
if (v->byte_per_pixel_in_detc[k] == 0.0) {
859
+
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0
860
+
/ v->byte_per_pixel_in_dety[k]
861
+
/ v->swath_width_yper_state[i][j][k];
862
+
v->lines_in_det_chroma = 0.0;
863
+
} else if (v->swath_height_yper_state[i][j][k]
864
+
<= v->swath_height_cper_state[i][j][k]) {
865
+
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0
866
+
/ 2.0 / v->byte_per_pixel_in_dety[k]
867
+
/ v->swath_width_yper_state[i][j][k];
868
+
v->lines_in_det_chroma =
869
+
v->det_buffer_size_in_kbyte * 1024.0 / 2.0
870
+
/ v->byte_per_pixel_in_detc[k]
871
+
/ (v->swath_width_yper_state[i][j][k]
872
+
/ 2.0);
873
+
} else {
874
+
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0
875
+
* 2.0 / 3.0 / v->byte_per_pixel_in_dety[k]
876
+
/ v->swath_width_yper_state[i][j][k];
877
+
v->lines_in_det_chroma =
878
+
v->det_buffer_size_in_kbyte * 1024.0 / 3.0
879
+
/ v->byte_per_pixel_in_dety[k]
880
+
/ (v->swath_width_yper_state[i][j][k]
881
+
/ 2.0);
882
+
}
883
+
v->effective_lb_latency_hiding_source_lines_luma =
884
+
dcn_bw_min2(
885
+
v->max_line_buffer_lines,
886
+
dcn_bw_floor2(
887
+
v->line_buffer_size
888
+
/ v->lb_bit_per_pixel[k]
889
+
/ (v->swath_width_yper_state[i][j][k]
890
+
/ dcn_bw_max2(
891
+
v->h_ratio[k],
892
+
1.0)),
893
+
1.0))
894
+
- (v->vtaps[k] - 1.0);
895
+
v->effective_lb_latency_hiding_source_lines_chroma =
896
+
dcn_bw_min2(
897
+
v->max_line_buffer_lines,
898
+
dcn_bw_floor2(
899
+
v->line_buffer_size
900
+
/ v->lb_bit_per_pixel[k]
901
+
/ (v->swath_width_yper_state[i][j][k]
902
+
/ 2.0
903
+
/ dcn_bw_max2(
904
+
v->h_ratio[k]
905
+
/ 2.0,
906
+
1.0)),
907
+
1.0))
908
+
- (v->vta_pschroma[k] - 1.0);
909
+
v->effective_detlb_lines_luma =
910
+
dcn_bw_floor2(
911
+
v->lines_in_det_luma
912
+
+ dcn_bw_min2(
913
+
v->lines_in_det_luma
914
+
* v->required_dispclk[i][j]
915
+
* v->byte_per_pixel_in_dety[k]
916
+
* v->pscl_factor[k]
917
+
/ v->return_bw_per_state[i],
918
+
v->effective_lb_latency_hiding_source_lines_luma),
919
+
v->swath_height_yper_state[i][j][k]);
920
+
v->effective_detlb_lines_chroma =
921
+
dcn_bw_floor2(
922
+
v->lines_in_det_chroma
923
+
+ dcn_bw_min2(
924
+
v->lines_in_det_chroma
925
+
* v->required_dispclk[i][j]
926
+
* v->byte_per_pixel_in_detc[k]
927
+
* v->pscl_factor_chroma[k]
928
+
/ v->return_bw_per_state[i],
929
+
v->effective_lb_latency_hiding_source_lines_chroma),
930
+
v->swath_height_cper_state[i][j][k]);
931
+
if (v->byte_per_pixel_in_detc[k] == 0.0) {
932
+
v->urgent_latency_support_us_per_state[i][j][k] =
933
+
v->effective_detlb_lines_luma
934
+
* (v->htotal[k]
935
+
/ v->pixel_clock[k])
936
+
/ v->v_ratio[k]
937
+
- v->effective_detlb_lines_luma
938
+
* v->swath_width_yper_state[i][j][k]
939
+
* dcn_bw_ceil2(
940
+
v->byte_per_pixel_in_dety[k],
941
+
1.0)
942
+
/ (v->return_bw_per_state[i]
943
+
/ v->no_of_dpp[i][j][k]);
944
+
} else {
945
+
v->urgent_latency_support_us_per_state[i][j][k] =
946
+
dcn_bw_min2(
947
+
v->effective_detlb_lines_luma
948
+
* (v->htotal[k]
949
+
/ v->pixel_clock[k])
950
+
/ v->v_ratio[k]
951
+
- v->effective_detlb_lines_luma
952
+
* v->swath_width_yper_state[i][j][k]
953
+
* dcn_bw_ceil2(
954
+
v->byte_per_pixel_in_dety[k],
955
+
1.0)
956
+
/ (v->return_bw_per_state[i]
957
+
/ v->no_of_dpp[i][j][k]),
958
+
v->effective_detlb_lines_chroma
959
+
* (v->htotal[k]
960
+
/ v->pixel_clock[k])
961
+
/ (v->v_ratio[k]
962
+
/ 2.0)
963
+
- v->effective_detlb_lines_chroma
964
+
* v->swath_width_yper_state[i][j][k]
965
+
/ 2.0
966
+
* dcn_bw_ceil2(
967
+
v->byte_per_pixel_in_detc[k],
968
+
2.0)
969
+
/ (v->return_bw_per_state[i]
970
+
/ v->no_of_dpp[i][j][k]));
971
+
}
972
+
}
973
+
}
974
+
}
975
+
for (i = 0; i <= number_of_states_plus_one; i++) {
976
+
for (j = 0; j <= 1; j++) {
977
+
v->urgent_latency_support[i][j] = dcn_bw_yes;
978
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
979
+
if (v->urgent_latency_support_us_per_state[i][j][k]
980
+
< v->urgent_latency / 1.0) {
981
+
v->urgent_latency_support[i][j] = dcn_bw_no;
982
+
}
983
+
}
984
+
}
985
+
}
986
+
/*prefetch check*/
987
+
988
+
for (i = 0; i <= number_of_states_plus_one; i++) {
989
+
for (j = 0; j <= 1; j++) {
990
+
v->total_number_of_dcc_active_dpp[i][j] = 0.0;
991
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
992
+
if (v->dcc_enable[k] == dcn_bw_yes) {
993
+
v->total_number_of_dcc_active_dpp[i][j] =
994
+
v->total_number_of_dcc_active_dpp[i][j]
995
+
+ v->no_of_dpp[i][j][k];
996
+
}
997
+
}
998
+
}
999
+
}
1000
+
for (i = 0; i <= number_of_states_plus_one; i++) {
1001
+
for (j = 0; j <= 1; j++) {
1002
+
v->projected_dcfclk_deep_sleep = 8.0;
1003
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1004
+
v->projected_dcfclk_deep_sleep = dcn_bw_max2(
1005
+
v->projected_dcfclk_deep_sleep,
1006
+
v->pixel_clock[k] / 16.0);
1007
+
if (v->byte_per_pixel_in_detc[k] == 0.0) {
1008
+
if (v->v_ratio[k] <= 1.0) {
1009
+
v->projected_dcfclk_deep_sleep =
1010
+
dcn_bw_max2(
1011
+
v->projected_dcfclk_deep_sleep,
1012
+
1.1
1013
+
* dcn_bw_ceil2(
1014
+
v->byte_per_pixel_in_dety[k],
1015
+
1.0)
1016
+
/ 64.0
1017
+
* v->h_ratio[k]
1018
+
* v->pixel_clock[k]
1019
+
/ v->no_of_dpp[i][j][k]);
1020
+
} else {
1021
+
v->projected_dcfclk_deep_sleep =
1022
+
dcn_bw_max2(
1023
+
v->projected_dcfclk_deep_sleep,
1024
+
1.1
1025
+
* dcn_bw_ceil2(
1026
+
v->byte_per_pixel_in_dety[k],
1027
+
1.0)
1028
+
/ 64.0
1029
+
* v->pscl_factor[k]
1030
+
* v->required_dispclk[i][j]
1031
+
/ (1
1032
+
+ j));
1033
+
}
1034
+
} else {
1035
+
if (v->v_ratio[k] <= 1.0) {
1036
+
v->projected_dcfclk_deep_sleep =
1037
+
dcn_bw_max2(
1038
+
v->projected_dcfclk_deep_sleep,
1039
+
1.1
1040
+
* dcn_bw_ceil2(
1041
+
v->byte_per_pixel_in_dety[k],
1042
+
1.0)
1043
+
/ 32.0
1044
+
* v->h_ratio[k]
1045
+
* v->pixel_clock[k]
1046
+
/ v->no_of_dpp[i][j][k]);
1047
+
} else {
1048
+
v->projected_dcfclk_deep_sleep =
1049
+
dcn_bw_max2(
1050
+
v->projected_dcfclk_deep_sleep,
1051
+
1.1
1052
+
* dcn_bw_ceil2(
1053
+
v->byte_per_pixel_in_dety[k],
1054
+
1.0)
1055
+
/ 32.0
1056
+
* v->pscl_factor[k]
1057
+
* v->required_dispclk[i][j]
1058
+
/ (1
1059
+
+ j));
1060
+
}
1061
+
if (v->v_ratio[k] / 2.0 <= 1.0) {
1062
+
v->projected_dcfclk_deep_sleep =
1063
+
dcn_bw_max2(
1064
+
v->projected_dcfclk_deep_sleep,
1065
+
1.1
1066
+
* dcn_bw_ceil2(
1067
+
v->byte_per_pixel_in_detc[k],
1068
+
2.0)
1069
+
/ 32.0
1070
+
* v->h_ratio[k]
1071
+
/ 2.0
1072
+
* v->pixel_clock[k]
1073
+
/ v->no_of_dpp[i][j][k]);
1074
+
} else {
1075
+
v->projected_dcfclk_deep_sleep =
1076
+
dcn_bw_max2(
1077
+
v->projected_dcfclk_deep_sleep,
1078
+
1.1
1079
+
* dcn_bw_ceil2(
1080
+
v->byte_per_pixel_in_detc[k],
1081
+
2.0)
1082
+
/ 32.0
1083
+
* v->pscl_factor_chroma[k]
1084
+
* v->required_dispclk[i][j]
1085
+
/ (1
1086
+
+ j));
1087
+
}
1088
+
}
1089
+
}
1090
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1091
+
if (v->dcc_enable[k] == dcn_bw_yes) {
1092
+
v->meta_req_height_y = 8.0 * v->read256_block_height_y[k];
1093
+
v->meta_req_width_y =
1094
+
64.0 * 256.0
1095
+
/ dcn_bw_ceil2(
1096
+
v->byte_per_pixel_in_dety[k],
1097
+
1.0)
1098
+
/ v->meta_req_height_y;
1099
+
v->meta_surface_width_y = dcn_bw_ceil2(
1100
+
v->viewport_width[k] / v->no_of_dpp[i][j][k]
1101
+
- 1.0,
1102
+
v->meta_req_width_y) + v->meta_req_width_y;
1103
+
v->meta_surface_height_y = dcn_bw_ceil2(
1104
+
v->viewport_height[k] - 1.0,
1105
+
v->meta_req_height_y)
1106
+
+ v->meta_req_height_y;
1107
+
if (v->pte_enable == dcn_bw_yes) {
1108
+
v->meta_pte_bytes_per_frame_y =
1109
+
(dcn_bw_ceil2(
1110
+
(v->meta_surface_width_y
1111
+
* v->meta_surface_height_y
1112
+
* dcn_bw_ceil2(
1113
+
v->byte_per_pixel_in_dety[k],
1114
+
1.0)
1115
+
/ 256.0
1116
+
- 4096.0)
1117
+
/ 8.0
1118
+
/ 4096.0,
1119
+
1.0) + 1) * 64.0;
1120
+
} else {
1121
+
v->meta_pte_bytes_per_frame_y = 0.0;
1122
+
}
1123
+
if (v->source_scan[k] == dcn_bw_hor) {
1124
+
v->meta_row_bytes_y =
1125
+
v->meta_surface_width_y
1126
+
* v->meta_req_height_y
1127
+
* dcn_bw_ceil2(
1128
+
v->byte_per_pixel_in_dety[k],
1129
+
1.0)
1130
+
/ 256.0;
1131
+
} else {
1132
+
v->meta_row_bytes_y =
1133
+
v->meta_surface_height_y
1134
+
* v->meta_req_width_y
1135
+
* dcn_bw_ceil2(
1136
+
v->byte_per_pixel_in_dety[k],
1137
+
1.0)
1138
+
/ 256.0;
1139
+
}
1140
+
} else {
1141
+
v->meta_pte_bytes_per_frame_y = 0.0;
1142
+
v->meta_row_bytes_y = 0.0;
1143
+
}
1144
+
if (v->pte_enable == dcn_bw_yes) {
1145
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
1146
+
v->macro_tile_block_size_bytes_y = 256.0;
1147
+
v->macro_tile_block_height_y = 1.0;
1148
+
} else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s
1149
+
|| v->source_surface_mode[k]
1150
+
== dcn_bw_sw_4_kb_s_x
1151
+
|| v->source_surface_mode[k]
1152
+
== dcn_bw_sw_4_kb_d
1153
+
|| v->source_surface_mode[k]
1154
+
== dcn_bw_sw_4_kb_d_x) {
1155
+
v->macro_tile_block_size_bytes_y = 4096.0;
1156
+
v->macro_tile_block_height_y = 4.0
1157
+
* v->read256_block_height_y[k];
1158
+
} else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s
1159
+
|| v->source_surface_mode[k]
1160
+
== dcn_bw_sw_64_kb_s_t
1161
+
|| v->source_surface_mode[k]
1162
+
== dcn_bw_sw_64_kb_s_x
1163
+
|| v->source_surface_mode[k]
1164
+
== dcn_bw_sw_64_kb_d
1165
+
|| v->source_surface_mode[k]
1166
+
== dcn_bw_sw_64_kb_d_t
1167
+
|| v->source_surface_mode[k]
1168
+
== dcn_bw_sw_64_kb_d_x) {
1169
+
v->macro_tile_block_size_bytes_y = 64.0 * 1024;
1170
+
v->macro_tile_block_height_y = 16.0
1171
+
* v->read256_block_height_y[k];
1172
+
} else {
1173
+
v->macro_tile_block_size_bytes_y = 256.0 * 1024;
1174
+
v->macro_tile_block_height_y = 32.0
1175
+
* v->read256_block_height_y[k];
1176
+
}
1177
+
if (v->macro_tile_block_size_bytes_y <= 65536.0) {
1178
+
v->data_pte_req_height_y =
1179
+
v->macro_tile_block_height_y;
1180
+
} else {
1181
+
v->data_pte_req_height_y = 16.0
1182
+
* v->read256_block_height_y[k];
1183
+
}
1184
+
v->data_pte_req_width_y =
1185
+
4096.0
1186
+
/ dcn_bw_ceil2(
1187
+
v->byte_per_pixel_in_dety[k],
1188
+
1.0)
1189
+
/ v->data_pte_req_height_y
1190
+
* 8;
1191
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
1192
+
v->dpte_bytes_per_row_y =
1193
+
64.0
1194
+
* (dcn_bw_ceil2(
1195
+
(v->viewport_width[k]
1196
+
/ v->no_of_dpp[i][j][k]
1197
+
* dcn_bw_min2(
1198
+
128.0,
1199
+
dcn_bw_pow(
1200
+
2.0,
1201
+
dcn_bw_floor2(
1202
+
dcn_bw_log(
1203
+
v->pte_buffer_size_in_requests
1204
+
* v->data_pte_req_width_y
1205
+
/ (v->viewport_width[k]
1206
+
/ v->no_of_dpp[i][j][k]),
1207
+
2.0),
1208
+
1.0)))
1209
+
- 1.0)
1210
+
/ v->data_pte_req_width_y,
1211
+
1.0)
1212
+
+ 1);
1213
+
} else if (v->source_scan[k] == dcn_bw_hor) {
1214
+
v->dpte_bytes_per_row_y =
1215
+
64.0
1216
+
* (dcn_bw_ceil2(
1217
+
(v->viewport_width[k]
1218
+
/ v->no_of_dpp[i][j][k]
1219
+
- 1.0)
1220
+
/ v->data_pte_req_width_y,
1221
+
1.0)
1222
+
+ 1);
1223
+
} else {
1224
+
v->dpte_bytes_per_row_y =
1225
+
64.0
1226
+
* (dcn_bw_ceil2(
1227
+
(v->viewport_height[k]
1228
+
- 1.0)
1229
+
/ v->data_pte_req_height_y,
1230
+
1.0)
1231
+
+ 1);
1232
+
}
1233
+
} else {
1234
+
v->dpte_bytes_per_row_y = 0.0;
1235
+
}
1236
+
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64
1237
+
&& v->source_pixel_format[k] != dcn_bw_rgb_sub_32
1238
+
&& v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
1239
+
if (v->dcc_enable[k] == dcn_bw_yes) {
1240
+
v->meta_req_height_c = 8.0
1241
+
* v->read256_block_height_c[k];
1242
+
v->meta_req_width_c =
1243
+
64.0 * 256.0
1244
+
/ dcn_bw_ceil2(
1245
+
v->byte_per_pixel_in_detc[k],
1246
+
2.0)
1247
+
/ v->meta_req_height_c;
1248
+
v->meta_surface_width_c =
1249
+
dcn_bw_ceil2(
1250
+
v->viewport_width[k]
1251
+
/ v->no_of_dpp[i][j][k]
1252
+
/ 2.0
1253
+
- 1.0,
1254
+
v->meta_req_width_c)
1255
+
+ v->meta_req_width_c;
1256
+
v->meta_surface_height_c = dcn_bw_ceil2(
1257
+
v->viewport_height[k] / 2.0 - 1.0,
1258
+
v->meta_req_height_c)
1259
+
+ v->meta_req_height_c;
1260
+
if (v->pte_enable == dcn_bw_yes) {
1261
+
v->meta_pte_bytes_per_frame_c =
1262
+
(dcn_bw_ceil2(
1263
+
(v->meta_surface_width_c
1264
+
* v->meta_surface_height_c
1265
+
* dcn_bw_ceil2(
1266
+
v->byte_per_pixel_in_detc[k],
1267
+
2.0)
1268
+
/ 256.0
1269
+
- 4096.0)
1270
+
/ 8.0
1271
+
/ 4096.0,
1272
+
1.0) + 1)
1273
+
* 64.0;
1274
+
} else {
1275
+
v->meta_pte_bytes_per_frame_c = 0.0;
1276
+
}
1277
+
if (v->source_scan[k] == dcn_bw_hor) {
1278
+
v->meta_row_bytes_c =
1279
+
v->meta_surface_width_c
1280
+
* v->meta_req_height_c
1281
+
* dcn_bw_ceil2(
1282
+
v->byte_per_pixel_in_detc[k],
1283
+
2.0)
1284
+
/ 256.0;
1285
+
} else {
1286
+
v->meta_row_bytes_c =
1287
+
v->meta_surface_height_c
1288
+
* v->meta_req_width_c
1289
+
* dcn_bw_ceil2(
1290
+
v->byte_per_pixel_in_detc[k],
1291
+
2.0)
1292
+
/ 256.0;
1293
+
}
1294
+
} else {
1295
+
v->meta_pte_bytes_per_frame_c = 0.0;
1296
+
v->meta_row_bytes_c = 0.0;
1297
+
}
1298
+
if (v->pte_enable == dcn_bw_yes) {
1299
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
1300
+
v->macro_tile_block_size_bytes_c = 256.0;
1301
+
v->macro_tile_block_height_c = 1.0;
1302
+
} else if (v->source_surface_mode[k]
1303
+
== dcn_bw_sw_4_kb_s
1304
+
|| v->source_surface_mode[k]
1305
+
== dcn_bw_sw_4_kb_s_x
1306
+
|| v->source_surface_mode[k]
1307
+
== dcn_bw_sw_4_kb_d
1308
+
|| v->source_surface_mode[k]
1309
+
== dcn_bw_sw_4_kb_d_x) {
1310
+
v->macro_tile_block_size_bytes_c = 4096.0;
1311
+
v->macro_tile_block_height_c =
1312
+
4.0
1313
+
* v->read256_block_height_c[k];
1314
+
} else if (v->source_surface_mode[k]
1315
+
== dcn_bw_sw_64_kb_s
1316
+
|| v->source_surface_mode[k]
1317
+
== dcn_bw_sw_64_kb_s_t
1318
+
|| v->source_surface_mode[k]
1319
+
== dcn_bw_sw_64_kb_s_x
1320
+
|| v->source_surface_mode[k]
1321
+
== dcn_bw_sw_64_kb_d
1322
+
|| v->source_surface_mode[k]
1323
+
== dcn_bw_sw_64_kb_d_t
1324
+
|| v->source_surface_mode[k]
1325
+
== dcn_bw_sw_64_kb_d_x) {
1326
+
v->macro_tile_block_size_bytes_c = 64.0
1327
+
* 1024;
1328
+
v->macro_tile_block_height_c =
1329
+
16.0
1330
+
* v->read256_block_height_c[k];
1331
+
} else {
1332
+
v->macro_tile_block_size_bytes_c = 256.0
1333
+
* 1024;
1334
+
v->macro_tile_block_height_c =
1335
+
32.0
1336
+
* v->read256_block_height_c[k];
1337
+
}
1338
+
v->macro_tile_block_width_c =
1339
+
v->macro_tile_block_size_bytes_c
1340
+
/ dcn_bw_ceil2(
1341
+
v->byte_per_pixel_in_detc[k],
1342
+
2.0)
1343
+
/ v->macro_tile_block_height_c;
1344
+
if (v->macro_tile_block_size_bytes_c <= 65536.0) {
1345
+
v->data_pte_req_height_c =
1346
+
v->macro_tile_block_height_c;
1347
+
} else {
1348
+
v->data_pte_req_height_c =
1349
+
16.0
1350
+
* v->read256_block_height_c[k];
1351
+
}
1352
+
v->data_pte_req_width_c =
1353
+
4096.0
1354
+
/ dcn_bw_ceil2(
1355
+
v->byte_per_pixel_in_detc[k],
1356
+
2.0)
1357
+
/ v->data_pte_req_height_c
1358
+
* 8;
1359
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
1360
+
v->dpte_bytes_per_row_c =
1361
+
64.0
1362
+
* (dcn_bw_ceil2(
1363
+
(v->viewport_width[k]
1364
+
/ v->no_of_dpp[i][j][k]
1365
+
/ 2.0
1366
+
* dcn_bw_min2(
1367
+
128.0,
1368
+
dcn_bw_pow(
1369
+
2.0,
1370
+
dcn_bw_floor2(
1371
+
dcn_bw_log(
1372
+
v->pte_buffer_size_in_requests
1373
+
* v->data_pte_req_width_c
1374
+
/ (v->viewport_width[k]
1375
+
/ v->no_of_dpp[i][j][k]
1376
+
/ 2.0),
1377
+
2.0),
1378
+
1.0)))
1379
+
- 1.0)
1380
+
/ v->data_pte_req_width_c,
1381
+
1.0)
1382
+
+ 1);
1383
+
} else if (v->source_scan[k] == dcn_bw_hor) {
1384
+
v->dpte_bytes_per_row_c =
1385
+
64.0
1386
+
* (dcn_bw_ceil2(
1387
+
(v->viewport_width[k]
1388
+
/ v->no_of_dpp[i][j][k]
1389
+
/ 2.0
1390
+
- 1.0)
1391
+
/ v->data_pte_req_width_c,
1392
+
1.0)
1393
+
+ 1);
1394
+
} else {
1395
+
v->dpte_bytes_per_row_c =
1396
+
64.0
1397
+
* (dcn_bw_ceil2(
1398
+
(v->viewport_height[k]
1399
+
/ 2.0
1400
+
- 1.0)
1401
+
/ v->data_pte_req_height_c,
1402
+
1.0)
1403
+
+ 1);
1404
+
}
1405
+
} else {
1406
+
v->dpte_bytes_per_row_c = 0.0;
1407
+
}
1408
+
} else {
1409
+
v->dpte_bytes_per_row_c = 0.0;
1410
+
v->meta_pte_bytes_per_frame_c = 0.0;
1411
+
v->meta_row_bytes_c = 0.0;
1412
+
}
1413
+
v->dpte_bytes_per_row[k] = v->dpte_bytes_per_row_y
1414
+
+ v->dpte_bytes_per_row_c;
1415
+
v->meta_pte_bytes_per_frame[k] = v->meta_pte_bytes_per_frame_y
1416
+
+ v->meta_pte_bytes_per_frame_c;
1417
+
v->meta_row_bytes[k] = v->meta_row_bytes_y + v->meta_row_bytes_c;
1418
+
v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0
1419
+
+ v->interlace_output[k] * 0.5 * v->v_ratio[k])
1420
+
/ 2.0;
1421
+
v->prefill_y[k] = dcn_bw_floor2(v->v_init_y, 1.0);
1422
+
v->max_num_sw_y[k] =
1423
+
dcn_bw_ceil2(
1424
+
(v->prefill_y[k] - 1.0)
1425
+
/ v->swath_height_yper_state[i][j][k],
1426
+
1.0) + 1;
1427
+
if (v->prefill_y[k] > 1.0) {
1428
+
v->max_partial_sw_y = dcn_bw_mod(
1429
+
(v->prefill_y[k] - 2.0),
1430
+
v->swath_height_yper_state[i][j][k]);
1431
+
} else {
1432
+
v->max_partial_sw_y =
1433
+
dcn_bw_mod(
1434
+
(v->prefill_y[k]
1435
+
+ v->swath_height_yper_state[i][j][k]
1436
+
- 2.0),
1437
+
v->swath_height_yper_state[i][j][k]);
1438
+
}
1439
+
v->max_partial_sw_y = dcn_bw_max2(1.0, v->max_partial_sw_y);
1440
+
v->prefetch_lines_y[k] = v->max_num_sw_y[k]
1441
+
* v->swath_height_yper_state[i][j][k]
1442
+
+ v->max_partial_sw_y;
1443
+
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64
1444
+
&& v->source_pixel_format[k] != dcn_bw_rgb_sub_32
1445
+
&& v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
1446
+
v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0
1447
+
+ v->interlace_output[k] * 0.5
1448
+
* v->v_ratio[k] / 2.0)
1449
+
/ 2.0;
1450
+
v->prefill_c[k] = dcn_bw_floor2(v->v_init_c, 1.0);
1451
+
v->max_num_sw_c[k] =
1452
+
dcn_bw_ceil2(
1453
+
(v->prefill_c[k] - 1.0)
1454
+
/ v->swath_height_cper_state[i][j][k],
1455
+
1.0) + 1;
1456
+
if (v->prefill_c[k] > 1.0) {
1457
+
v->max_partial_sw_c =
1458
+
dcn_bw_mod(
1459
+
(v->prefill_c[k]
1460
+
- 2.0),
1461
+
v->swath_height_cper_state[i][j][k]);
1462
+
} else {
1463
+
v->max_partial_sw_c =
1464
+
dcn_bw_mod(
1465
+
(v->prefill_c[k]
1466
+
+ v->swath_height_cper_state[i][j][k]
1467
+
- 2.0),
1468
+
v->swath_height_cper_state[i][j][k]);
1469
+
}
1470
+
v->max_partial_sw_c = dcn_bw_max2(1.0, v->max_partial_sw_c);
1471
+
v->prefetch_lines_c[k] = v->max_num_sw_c[k]
1472
+
* v->swath_height_cper_state[i][j][k]
1473
+
+ v->max_partial_sw_c;
1474
+
} else {
1475
+
v->prefetch_lines_c[k] = 0.0;
1476
+
}
1477
+
v->dst_x_after_scaler = 90.0 * v->pixel_clock[k]
1478
+
/ (v->required_dispclk[i][j] / (j + 1))
1479
+
+ 42.0 * v->pixel_clock[k]
1480
+
/ v->required_dispclk[i][j];
1481
+
if (v->no_of_dpp[i][j][k] > 1.0) {
1482
+
v->dst_x_after_scaler = v->dst_x_after_scaler
1483
+
+ v->scaler_rec_out_width[k] / 2.0;
1484
+
}
1485
+
if (v->output_format[k] == dcn_bw_420) {
1486
+
v->dst_y_after_scaler = 1.0;
1487
+
} else {
1488
+
v->dst_y_after_scaler = 0.0;
1489
+
}
1490
+
v->time_calc = 24.0 / v->projected_dcfclk_deep_sleep;
1491
+
v->v_update_offset[k] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
1492
+
v->total_repeater_delay = v->max_inter_dcn_tile_repeaters
1493
+
* (2.0 / (v->required_dispclk[i][j] / (j + 1))
1494
+
+ 3.0 / v->required_dispclk[i][j]);
1495
+
v->v_update_width[k] = (14.0 / v->projected_dcfclk_deep_sleep
1496
+
+ 12.0 / (v->required_dispclk[i][j] / (j + 1))
1497
+
+ v->total_repeater_delay) * v->pixel_clock[k];
1498
+
v->v_ready_offset[k] =
1499
+
dcn_bw_max2(
1500
+
150.0
1501
+
/ (v->required_dispclk[i][j]
1502
+
/ (j
1503
+
+ 1)),
1504
+
v->total_repeater_delay
1505
+
+ 20.0
1506
+
/ v->projected_dcfclk_deep_sleep
1507
+
+ 10.0
1508
+
/ (v->required_dispclk[i][j]
1509
+
/ (j
1510
+
+ 1)))
1511
+
* v->pixel_clock[k];
1512
+
v->time_setup = (v->v_update_offset[k] + v->v_update_width[k]
1513
+
+ v->v_ready_offset[k]) / v->pixel_clock[k];
1514
+
v->extra_latency =
1515
+
v->urgent_round_trip_and_out_of_order_latency_per_state[i]
1516
+
+ (v->total_number_of_active_dpp[i][j]
1517
+
* v->pixel_chunk_size_in_kbyte
1518
+
+ v->total_number_of_dcc_active_dpp[i][j]
1519
+
* v->meta_chunk_size)
1520
+
* 1024.0
1521
+
/ v->return_bw_per_state[i];
1522
+
if (v->pte_enable == dcn_bw_yes) {
1523
+
v->extra_latency = v->extra_latency
1524
+
+ v->total_number_of_active_dpp[i][j]
1525
+
* v->pte_chunk_size * 1024.0
1526
+
/ v->return_bw_per_state[i];
1527
+
}
1528
+
if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one
1529
+
== dcn_bw_yes) {
1530
+
v->maximum_vstartup = v->vtotal[k] - v->vactive[k] - 1.0;
1531
+
} else {
1532
+
v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0;
1533
+
}
1534
+
v->line_times_for_prefetch[k] = v->maximum_vstartup
1535
+
- v->urgent_latency
1536
+
/ (v->htotal[k] / v->pixel_clock[k])
1537
+
- (v->time_calc + v->time_setup)
1538
+
/ (v->htotal[k] / v->pixel_clock[k])
1539
+
- (v->dst_y_after_scaler
1540
+
+ v->dst_x_after_scaler
1541
+
/ v->htotal[k]);
1542
+
v->line_times_for_prefetch[k] = dcn_bw_floor2(
1543
+
4.0 * (v->line_times_for_prefetch[k] + 0.125),
1544
+
1.0) / 4;
1545
+
v->prefetch_bw[k] =
1546
+
(v->meta_pte_bytes_per_frame[k]
1547
+
+ 2.0 * v->meta_row_bytes[k]
1548
+
+ 2.0 * v->dpte_bytes_per_row[k]
1549
+
+ v->prefetch_lines_y[k]
1550
+
* v->swath_width_yper_state[i][j][k]
1551
+
* dcn_bw_ceil2(
1552
+
v->byte_per_pixel_in_dety[k],
1553
+
1.0)
1554
+
+ v->prefetch_lines_c[k]
1555
+
* v->swath_width_yper_state[i][j][k]
1556
+
/ 2.0
1557
+
* dcn_bw_ceil2(
1558
+
v->byte_per_pixel_in_detc[k],
1559
+
2.0))
1560
+
/ (v->line_times_for_prefetch[k]
1561
+
* v->htotal[k]
1562
+
/ v->pixel_clock[k]);
1563
+
}
1564
+
v->bw_available_for_immediate_flip = v->return_bw_per_state[i];
1565
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1566
+
v->bw_available_for_immediate_flip =
1567
+
v->bw_available_for_immediate_flip
1568
+
- dcn_bw_max2(
1569
+
v->read_bandwidth[k],
1570
+
v->prefetch_bw[k]);
1571
+
}
1572
+
v->total_immediate_flip_bytes[k] = 0.0;
1573
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1574
+
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
1575
+
&& v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
1576
+
v->total_immediate_flip_bytes[k] =
1577
+
v->total_immediate_flip_bytes[k]
1578
+
+ v->meta_pte_bytes_per_frame[k]
1579
+
+ v->meta_row_bytes[k]
1580
+
+ v->dpte_bytes_per_row[k];
1581
+
}
1582
+
}
1583
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1584
+
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
1585
+
v->time_for_meta_pte_with_immediate_flip =
1586
+
dcn_bw_max5(
1587
+
v->meta_pte_bytes_per_frame[k]
1588
+
/ v->prefetch_bw[k],
1589
+
v->meta_pte_bytes_per_frame[k]
1590
+
* v->total_immediate_flip_bytes[k]
1591
+
/ (v->bw_available_for_immediate_flip
1592
+
* (v->meta_pte_bytes_per_frame[k]
1593
+
+ v->meta_row_bytes[k]
1594
+
+ v->dpte_bytes_per_row[k])),
1595
+
v->extra_latency,
1596
+
v->urgent_latency,
1597
+
v->htotal[k]
1598
+
/ v->pixel_clock[k]
1599
+
/ 4.0);
1600
+
v->time_for_meta_pte_without_immediate_flip = dcn_bw_max3(
1601
+
v->meta_pte_bytes_per_frame[k]
1602
+
/ v->prefetch_bw[k],
1603
+
v->extra_latency,
1604
+
v->htotal[k] / v->pixel_clock[k] / 4.0);
1605
+
} else {
1606
+
v->time_for_meta_pte_with_immediate_flip = v->htotal[k]
1607
+
/ v->pixel_clock[k] / 4.0;
1608
+
v->time_for_meta_pte_without_immediate_flip = v->htotal[k]
1609
+
/ v->pixel_clock[k] / 4.0;
1610
+
}
1611
+
if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
1612
+
v->time_for_meta_and_dpte_row_with_immediate_flip =
1613
+
dcn_bw_max5(
1614
+
(v->meta_row_bytes[k]
1615
+
+ v->dpte_bytes_per_row[k])
1616
+
/ v->prefetch_bw[k],
1617
+
(v->meta_row_bytes[k]
1618
+
+ v->dpte_bytes_per_row[k])
1619
+
* v->total_immediate_flip_bytes[k]
1620
+
/ (v->bw_available_for_immediate_flip
1621
+
* (v->meta_pte_bytes_per_frame[k]
1622
+
+ v->meta_row_bytes[k]
1623
+
+ v->dpte_bytes_per_row[k])),
1624
+
v->htotal[k]
1625
+
/ v->pixel_clock[k]
1626
+
- v->time_for_meta_pte_with_immediate_flip,
1627
+
v->extra_latency,
1628
+
2.0 * v->urgent_latency);
1629
+
v->time_for_meta_and_dpte_row_without_immediate_flip =
1630
+
dcn_bw_max3(
1631
+
(v->meta_row_bytes[k]
1632
+
+ v->dpte_bytes_per_row[k])
1633
+
/ v->prefetch_bw[k],
1634
+
v->htotal[k]
1635
+
/ v->pixel_clock[k]
1636
+
- v->time_for_meta_pte_without_immediate_flip,
1637
+
v->extra_latency);
1638
+
} else {
1639
+
v->time_for_meta_and_dpte_row_with_immediate_flip =
1640
+
dcn_bw_max2(
1641
+
v->htotal[k]
1642
+
/ v->pixel_clock[k]
1643
+
- v->time_for_meta_pte_with_immediate_flip,
1644
+
v->extra_latency
1645
+
- v->time_for_meta_pte_with_immediate_flip);
1646
+
v->time_for_meta_and_dpte_row_without_immediate_flip =
1647
+
dcn_bw_max2(
1648
+
v->htotal[k]
1649
+
/ v->pixel_clock[k]
1650
+
- v->time_for_meta_pte_without_immediate_flip,
1651
+
v->extra_latency
1652
+
- v->time_for_meta_pte_without_immediate_flip);
1653
+
}
1654
+
v->lines_for_meta_pte_with_immediate_flip[k] =
1655
+
dcn_bw_floor2(
1656
+
4.0
1657
+
* (v->time_for_meta_pte_with_immediate_flip
1658
+
/ (v->htotal[k]
1659
+
/ v->pixel_clock[k])
1660
+
+ 0.125),
1661
+
1.0) / 4;
1662
+
v->lines_for_meta_pte_without_immediate_flip[k] =
1663
+
dcn_bw_floor2(
1664
+
4.0
1665
+
* (v->time_for_meta_pte_without_immediate_flip
1666
+
/ (v->htotal[k]
1667
+
/ v->pixel_clock[k])
1668
+
+ 0.125),
1669
+
1.0) / 4;
1670
+
v->lines_for_meta_and_dpte_row_with_immediate_flip[k] =
1671
+
dcn_bw_floor2(
1672
+
4.0
1673
+
* (v->time_for_meta_and_dpte_row_with_immediate_flip
1674
+
/ (v->htotal[k]
1675
+
/ v->pixel_clock[k])
1676
+
+ 0.125),
1677
+
1.0) / 4;
1678
+
v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =
1679
+
dcn_bw_floor2(
1680
+
4.0
1681
+
* (v->time_for_meta_and_dpte_row_without_immediate_flip
1682
+
/ (v->htotal[k]
1683
+
/ v->pixel_clock[k])
1684
+
+ 0.125),
1685
+
1.0) / 4;
1686
+
v->line_times_to_request_prefetch_pixel_data_with_immediate_flip =
1687
+
v->line_times_for_prefetch[k]
1688
+
- v->lines_for_meta_pte_with_immediate_flip[k]
1689
+
- v->lines_for_meta_and_dpte_row_with_immediate_flip[k];
1690
+
v->line_times_to_request_prefetch_pixel_data_without_immediate_flip =
1691
+
v->line_times_for_prefetch[k]
1692
+
- v->lines_for_meta_pte_without_immediate_flip[k]
1693
+
- v->lines_for_meta_and_dpte_row_without_immediate_flip[k];
1694
+
if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
1695
+
> 0.0) {
1696
+
v->v_ratio_pre_ywith_immediate_flip[i][j][k] =
1697
+
v->prefetch_lines_y[k]
1698
+
/ v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
1699
+
if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
1700
+
if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
1701
+
- (v->prefill_y[k] - 3.0) / 2.0
1702
+
> 0.0) {
1703
+
v->v_ratio_pre_ywith_immediate_flip[i][j][k] =
1704
+
dcn_bw_max2(
1705
+
v->v_ratio_pre_ywith_immediate_flip[i][j][k],
1706
+
(v->max_num_sw_y[k]
1707
+
* v->swath_height_yper_state[i][j][k])
1708
+
/ (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
1709
+
- (v->prefill_y[k]
1710
+
- 3.0)
1711
+
/ 2.0));
1712
+
} else {
1713
+
v->v_ratio_pre_ywith_immediate_flip[i][j][k] =
1714
+
999999.0;
1715
+
}
1716
+
}
1717
+
v->v_ratio_pre_cwith_immediate_flip[i][j][k] =
1718
+
v->prefetch_lines_c[k]
1719
+
/ v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
1720
+
if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
1721
+
if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
1722
+
- (v->prefill_c[k] - 3.0) / 2.0
1723
+
> 0.0) {
1724
+
v->v_ratio_pre_cwith_immediate_flip[i][j][k] =
1725
+
dcn_bw_max2(
1726
+
v->v_ratio_pre_cwith_immediate_flip[i][j][k],
1727
+
(v->max_num_sw_c[k]
1728
+
* v->swath_height_cper_state[i][j][k])
1729
+
/ (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
1730
+
- (v->prefill_c[k]
1731
+
- 3.0)
1732
+
/ 2.0));
1733
+
} else {
1734
+
v->v_ratio_pre_cwith_immediate_flip[i][j][k] =
1735
+
999999.0;
1736
+
}
1737
+
}
1738
+
v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] =
1739
+
v->no_of_dpp[i][j][k]
1740
+
* (v->prefetch_lines_y[k]
1741
+
/ v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
1742
+
* dcn_bw_ceil2(
1743
+
v->byte_per_pixel_in_dety[k],
1744
+
1.0)
1745
+
+ v->prefetch_lines_c[k]
1746
+
/ v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
1747
+
* dcn_bw_ceil2(
1748
+
v->byte_per_pixel_in_detc[k],
1749
+
2.0)
1750
+
/ 2.0)
1751
+
* v->swath_width_yper_state[i][j][k]
1752
+
/ (v->htotal[k]
1753
+
/ v->pixel_clock[k]);
1754
+
} else {
1755
+
v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0;
1756
+
v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0;
1757
+
v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] =
1758
+
999999.0;
1759
+
}
1760
+
if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
1761
+
> 0.0) {
1762
+
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =
1763
+
v->prefetch_lines_y[k]
1764
+
/ v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
1765
+
if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
1766
+
if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
1767
+
- (v->prefill_y[k] - 3.0) / 2.0
1768
+
> 0.0) {
1769
+
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =
1770
+
dcn_bw_max2(
1771
+
v->v_ratio_pre_ywithout_immediate_flip[i][j][k],
1772
+
(v->max_num_sw_y[k]
1773
+
* v->swath_height_yper_state[i][j][k])
1774
+
/ (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
1775
+
- (v->prefill_y[k]
1776
+
- 3.0)
1777
+
/ 2.0));
1778
+
} else {
1779
+
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =
1780
+
999999.0;
1781
+
}
1782
+
}
1783
+
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =
1784
+
v->prefetch_lines_c[k]
1785
+
/ v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
1786
+
if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
1787
+
if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
1788
+
- (v->prefill_c[k] - 3.0) / 2.0
1789
+
> 0.0) {
1790
+
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =
1791
+
dcn_bw_max2(
1792
+
v->v_ratio_pre_cwithout_immediate_flip[i][j][k],
1793
+
(v->max_num_sw_c[k]
1794
+
* v->swath_height_cper_state[i][j][k])
1795
+
/ (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
1796
+
- (v->prefill_c[k]
1797
+
- 3.0)
1798
+
/ 2.0));
1799
+
} else {
1800
+
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =
1801
+
999999.0;
1802
+
}
1803
+
}
1804
+
v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] =
1805
+
v->no_of_dpp[i][j][k]
1806
+
* (v->prefetch_lines_y[k]
1807
+
/ v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
1808
+
* dcn_bw_ceil2(
1809
+
v->byte_per_pixel_in_dety[k],
1810
+
1.0)
1811
+
+ v->prefetch_lines_c[k]
1812
+
/ v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
1813
+
* dcn_bw_ceil2(
1814
+
v->byte_per_pixel_in_detc[k],
1815
+
2.0)
1816
+
/ 2.0)
1817
+
* v->swath_width_yper_state[i][j][k]
1818
+
/ (v->htotal[k]
1819
+
/ v->pixel_clock[k]);
1820
+
} else {
1821
+
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0;
1822
+
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0;
1823
+
v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] =
1824
+
999999.0;
1825
+
}
1826
+
}
1827
+
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = 0.0;
1828
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1829
+
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
1830
+
&& v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
1831
+
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip =
1832
+
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip
1833
+
+ dcn_bw_max2(
1834
+
v->read_bandwidth[k],
1835
+
v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k])
1836
+
+ dcn_bw_max2(
1837
+
v->meta_pte_bytes_per_frame[k]
1838
+
/ (v->lines_for_meta_pte_with_immediate_flip[k]
1839
+
* v->htotal[k]
1840
+
/ v->pixel_clock[k]),
1841
+
(v->meta_row_bytes[k]
1842
+
+ v->dpte_bytes_per_row[k])
1843
+
/ (v->lines_for_meta_and_dpte_row_with_immediate_flip[k]
1844
+
* v->htotal[k]
1845
+
/ v->pixel_clock[k]));
1846
+
} else {
1847
+
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip =
1848
+
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip
1849
+
+ dcn_bw_max2(
1850
+
v->read_bandwidth[k],
1851
+
v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
1852
+
}
1853
+
}
1854
+
v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = 0.0;
1855
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1856
+
v->maximum_read_bandwidth_with_prefetch_without_immediate_flip =
1857
+
v->maximum_read_bandwidth_with_prefetch_without_immediate_flip
1858
+
+ dcn_bw_max2(
1859
+
v->read_bandwidth[k],
1860
+
v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
1861
+
}
1862
+
v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes;
1863
+
if (v->maximum_read_bandwidth_with_prefetch_with_immediate_flip
1864
+
> v->return_bw_per_state[i]) {
1865
+
v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no;
1866
+
}
1867
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1868
+
if (v->line_times_for_prefetch[k] < 2.0
1869
+
|| v->lines_for_meta_pte_with_immediate_flip[k]
1870
+
>= 8.0
1871
+
|| v->lines_for_meta_and_dpte_row_with_immediate_flip[k]
1872
+
>= 16.0) {
1873
+
v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no;
1874
+
}
1875
+
}
1876
+
v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes;
1877
+
if (v->maximum_read_bandwidth_with_prefetch_without_immediate_flip
1878
+
> v->return_bw_per_state[i]) {
1879
+
v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no;
1880
+
}
1881
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1882
+
if (v->line_times_for_prefetch[k] < 2.0
1883
+
|| v->lines_for_meta_pte_without_immediate_flip[k]
1884
+
>= 8.0
1885
+
|| v->lines_for_meta_and_dpte_row_without_immediate_flip[k]
1886
+
>= 16.0) {
1887
+
v->prefetch_supported_without_immediate_flip[i][j] =
1888
+
dcn_bw_no;
1889
+
}
1890
+
}
1891
+
}
1892
+
}
1893
+
for (i = 0; i <= number_of_states_plus_one; i++) {
1894
+
for (j = 0; j <= 1; j++) {
1895
+
v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes;
1896
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1897
+
if ((((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
1898
+
&& v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)
1899
+
&& (v->v_ratio_pre_ywith_immediate_flip[i][j][k]
1900
+
> 4.0
1901
+
|| v->v_ratio_pre_cwith_immediate_flip[i][j][k]
1902
+
> 4.0))
1903
+
|| ((v->source_pixel_format[k]
1904
+
== dcn_bw_yuv420_sub_8
1905
+
|| v->source_pixel_format[k]
1906
+
== dcn_bw_yuv420_sub_10)
1907
+
&& (v->v_ratio_pre_ywithout_immediate_flip[i][j][k]
1908
+
> 4.0
1909
+
|| v->v_ratio_pre_cwithout_immediate_flip[i][j][k]
1910
+
> 4.0)))) {
1911
+
v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] =
1912
+
dcn_bw_no;
1913
+
}
1914
+
}
1915
+
v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes;
1916
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1917
+
if ((v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0
1918
+
|| v->v_ratio_pre_cwithout_immediate_flip[i][j][k]
1919
+
> 4.0)) {
1920
+
v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] =
1921
+
dcn_bw_no;
1922
+
}
1923
+
}
1924
+
}
1925
+
}
1926
+
/*mode support, voltage state and soc configuration*/
1927
+
1928
+
for (i = number_of_states_plus_one; i >= 0; i--) {
1929
+
for (j = 0; j <= 1; j++) {
1930
+
if (v->scale_ratio_support == dcn_bw_yes
1931
+
&& v->source_format_pixel_and_scan_support == dcn_bw_yes
1932
+
&& v->viewport_size_support == dcn_bw_yes
1933
+
&& v->bandwidth_support[i] == dcn_bw_yes
1934
+
&& v->dio_support[i] == dcn_bw_yes
1935
+
&& v->urgent_latency_support[i][j] == dcn_bw_yes
1936
+
&& v->rob_support[i] == dcn_bw_yes
1937
+
&& v->dispclk_dppclk_support[i][j] == dcn_bw_yes
1938
+
&& v->total_available_pipes_support[i][j] == dcn_bw_yes
1939
+
&& v->total_available_writeback_support == dcn_bw_yes
1940
+
&& v->writeback_latency_support == dcn_bw_yes) {
1941
+
if (v->prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes
1942
+
&& v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j]
1943
+
== dcn_bw_yes) {
1944
+
v->mode_support_with_immediate_flip[i][j] = dcn_bw_yes;
1945
+
} else {
1946
+
v->mode_support_with_immediate_flip[i][j] = dcn_bw_no;
1947
+
}
1948
+
if (v->prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes
1949
+
&& v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j]
1950
+
== dcn_bw_yes) {
1951
+
v->mode_support_without_immediate_flip[i][j] = dcn_bw_yes;
1952
+
} else {
1953
+
v->mode_support_without_immediate_flip[i][j] = dcn_bw_no;
1954
+
}
1955
+
} else {
1956
+
v->mode_support_with_immediate_flip[i][j] = dcn_bw_no;
1957
+
v->mode_support_without_immediate_flip[i][j] = dcn_bw_no;
1958
+
}
1959
+
}
1960
+
}
1961
+
for (i = number_of_states_plus_one; i >= 0; i--) {
1962
+
if ((i == number_of_states_plus_one
1963
+
|| v->mode_support_with_immediate_flip[i][1] == dcn_bw_yes
1964
+
|| v->mode_support_with_immediate_flip[i][0] == dcn_bw_yes)
1965
+
&& i >= v->voltage_override_level) {
1966
+
v->voltage_level_with_immediate_flip = i;
1967
+
}
1968
+
}
1969
+
for (i = number_of_states_plus_one; i >= 0; i--) {
1970
+
if ((i == number_of_states_plus_one
1971
+
|| v->mode_support_without_immediate_flip[i][1] == dcn_bw_yes
1972
+
|| v->mode_support_without_immediate_flip[i][0] == dcn_bw_yes)
1973
+
&& i >= v->voltage_override_level) {
1974
+
v->voltage_level_without_immediate_flip = i;
1975
+
}
1976
+
}
1977
+
if (v->voltage_level_with_immediate_flip == number_of_states_plus_one) {
1978
+
v->immediate_flip_supported = dcn_bw_no;
1979
+
v->voltage_level = v->voltage_level_without_immediate_flip;
1980
+
} else {
1981
+
v->immediate_flip_supported = dcn_bw_yes;
1982
+
v->voltage_level = v->voltage_level_with_immediate_flip;
1983
+
}
1984
+
v->dcfclk = v->dcfclk_per_state[v->voltage_level];
1985
+
v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
1986
+
for (j = 0; j <= 1; j++) {
1987
+
v->required_dispclk_per_ratio[j] = v->required_dispclk[v->voltage_level][j];
1988
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1989
+
v->dpp_per_plane_per_ratio[j][k] = v->no_of_dpp[v->voltage_level][j][k];
1990
+
}
1991
+
v->dispclk_dppclk_support_per_ratio[j] =
1992
+
v->dispclk_dppclk_support[v->voltage_level][j];
1993
+
}
1994
+
v->max_phyclk = v->phyclk_per_state[v->voltage_level];
1995
+
}
1996
+
void display_pipe_configuration(struct dcn_bw_internal_vars *v)
1997
+
{
1998
+
int j, k;
1999
+
/*display pipe configuration*/
2000
+
2001
+
for (j = 0; j <= 1; j++) {
2002
+
v->total_number_of_active_dpp_per_ratio[j] = 0.0;
2003
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2004
+
v->total_number_of_active_dpp_per_ratio[j] =
2005
+
v->total_number_of_active_dpp_per_ratio[j]
2006
+
+ v->dpp_per_plane_per_ratio[j][k];
2007
+
}
2008
+
}
2009
+
if ((v->dispclk_dppclk_support_per_ratio[0] == dcn_bw_yes
2010
+
&& v->dispclk_dppclk_support_per_ratio[1] == dcn_bw_no)
2011
+
|| (v->dispclk_dppclk_support_per_ratio[0]
2012
+
== v->dispclk_dppclk_support_per_ratio[1]
2013
+
&& (v->total_number_of_active_dpp_per_ratio[0]
2014
+
< v->total_number_of_active_dpp_per_ratio[1]
2015
+
|| (((v->total_number_of_active_dpp_per_ratio[0]
2016
+
== v->total_number_of_active_dpp_per_ratio[1])
2017
+
&& v->required_dispclk_per_ratio[0]
2018
+
<= 0.5
2019
+
* v->required_dispclk_per_ratio[1]))))) {
2020
+
v->dispclk_dppclk_ratio = 1;
2021
+
v->final_error_message = v->error_message[0];
2022
+
} else {
2023
+
v->dispclk_dppclk_ratio = 2;
2024
+
v->final_error_message = v->error_message[1];
2025
+
}
2026
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2027
+
v->dpp_per_plane[k] = v->dpp_per_plane_per_ratio[v->dispclk_dppclk_ratio - 1][k];
2028
+
}
2029
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2030
+
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
2031
+
v->byte_per_pix_dety = 8.0;
2032
+
v->byte_per_pix_detc = 0.0;
2033
+
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
2034
+
v->byte_per_pix_dety = 4.0;
2035
+
v->byte_per_pix_detc = 0.0;
2036
+
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
2037
+
v->byte_per_pix_dety = 2.0;
2038
+
v->byte_per_pix_detc = 0.0;
2039
+
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
2040
+
v->byte_per_pix_dety = 1.0;
2041
+
v->byte_per_pix_detc = 2.0;
2042
+
} else {
2043
+
v->byte_per_pix_dety = 4.0f / 3;
2044
+
v->byte_per_pix_detc = 8.0f / 3;
2045
+
}
2046
+
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64
2047
+
|| v->source_pixel_format[k] == dcn_bw_rgb_sub_32
2048
+
|| v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
2049
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
2050
+
v->read256_bytes_block_height_y = 1.0;
2051
+
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
2052
+
v->read256_bytes_block_height_y = 4.0;
2053
+
} else {
2054
+
v->read256_bytes_block_height_y = 8.0;
2055
+
}
2056
+
v->read256_bytes_block_width_y = 256.0 / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0)
2057
+
/ v->read256_bytes_block_height_y;
2058
+
v->read256_bytes_block_height_c = 0.0;
2059
+
v->read256_bytes_block_width_c = 0.0;
2060
+
} else {
2061
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
2062
+
v->read256_bytes_block_height_y = 1.0;
2063
+
v->read256_bytes_block_height_c = 1.0;
2064
+
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
2065
+
v->read256_bytes_block_height_y = 16.0;
2066
+
v->read256_bytes_block_height_c = 8.0;
2067
+
} else {
2068
+
v->read256_bytes_block_height_y = 8.0;
2069
+
v->read256_bytes_block_height_c = 8.0;
2070
+
}
2071
+
v->read256_bytes_block_width_y = 256.0 / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0)
2072
+
/ v->read256_bytes_block_height_y;
2073
+
v->read256_bytes_block_width_c = 256.0 / dcn_bw_ceil2(v->byte_per_pix_detc, 2.0)
2074
+
/ v->read256_bytes_block_height_c;
2075
+
}
2076
+
if (v->source_scan[k] == dcn_bw_hor) {
2077
+
v->maximum_swath_height_y = v->read256_bytes_block_height_y;
2078
+
v->maximum_swath_height_c = v->read256_bytes_block_height_c;
2079
+
} else {
2080
+
v->maximum_swath_height_y = v->read256_bytes_block_width_y;
2081
+
v->maximum_swath_height_c = v->read256_bytes_block_width_c;
2082
+
}
2083
+
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64
2084
+
|| v->source_pixel_format[k] == dcn_bw_rgb_sub_32
2085
+
|| v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
2086
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear
2087
+
|| (v->source_pixel_format[k] == dcn_bw_rgb_sub_64
2088
+
&& (v->source_surface_mode[k]
2089
+
== dcn_bw_sw_4_kb_s
2090
+
|| v->source_surface_mode[k]
2091
+
== dcn_bw_sw_4_kb_s_x
2092
+
|| v->source_surface_mode[k]
2093
+
== dcn_bw_sw_64_kb_s
2094
+
|| v->source_surface_mode[k]
2095
+
== dcn_bw_sw_64_kb_s_t
2096
+
|| v->source_surface_mode[k]
2097
+
== dcn_bw_sw_64_kb_s_x
2098
+
|| v->source_surface_mode[k]
2099
+
== dcn_bw_sw_var_s
2100
+
|| v->source_surface_mode[k]
2101
+
== dcn_bw_sw_var_s_x)
2102
+
&& v->source_scan[k] == dcn_bw_hor)) {
2103
+
v->minimum_swath_height_y = v->maximum_swath_height_y;
2104
+
} else {
2105
+
v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
2106
+
}
2107
+
v->minimum_swath_height_c = v->maximum_swath_height_c;
2108
+
} else {
2109
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
2110
+
v->minimum_swath_height_y = v->maximum_swath_height_y;
2111
+
v->minimum_swath_height_c = v->maximum_swath_height_c;
2112
+
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8
2113
+
&& v->source_scan[k] == dcn_bw_hor) {
2114
+
v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
2115
+
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed
2116
+
== dcn_bw_yes) {
2117
+
v->minimum_swath_height_c = v->maximum_swath_height_c;
2118
+
} else {
2119
+
v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0;
2120
+
}
2121
+
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10
2122
+
&& v->source_scan[k] == dcn_bw_hor) {
2123
+
v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0;
2124
+
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed
2125
+
== dcn_bw_yes) {
2126
+
v->minimum_swath_height_y = v->maximum_swath_height_y;
2127
+
} else {
2128
+
v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
2129
+
}
2130
+
} else {
2131
+
v->minimum_swath_height_y = v->maximum_swath_height_y;
2132
+
v->minimum_swath_height_c = v->maximum_swath_height_c;
2133
+
}
2134
+
}
2135
+
if (v->source_scan[k] == dcn_bw_hor) {
2136
+
v->swath_width = v->viewport_width[k] / v->dpp_per_plane[k];
2137
+
} else {
2138
+
v->swath_width = v->viewport_height[k] / v->dpp_per_plane[k];
2139
+
}
2140
+
v->swath_width_granularity_y = 256.0 / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0)
2141
+
/ v->maximum_swath_height_y;
2142
+
v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(
2143
+
v->swath_width - 1.0,
2144
+
v->swath_width_granularity_y) + v->swath_width_granularity_y)
2145
+
* v->byte_per_pix_dety * v->maximum_swath_height_y;
2146
+
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
2147
+
v->rounded_up_max_swath_size_bytes_y = dcn_bw_ceil2(
2148
+
v->rounded_up_max_swath_size_bytes_y,
2149
+
256.0) + 256;
2150
+
}
2151
+
if (v->maximum_swath_height_c > 0.0) {
2152
+
v->swath_width_granularity_c = 256.0 / dcn_bw_ceil2(v->byte_per_pix_detc, 2.0)
2153
+
/ v->maximum_swath_height_c;
2154
+
}
2155
+
v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(
2156
+
v->swath_width / 2.0 - 1.0,
2157
+
v->swath_width_granularity_c) + v->swath_width_granularity_c)
2158
+
* v->byte_per_pix_detc * v->maximum_swath_height_c;
2159
+
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
2160
+
v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(
2161
+
v->rounded_up_max_swath_size_bytes_c,
2162
+
256.0) + 256;
2163
+
}
2164
+
if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c
2165
+
<= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) {
2166
+
v->swath_height_y[k] = v->maximum_swath_height_y;
2167
+
v->swath_height_c[k] = v->maximum_swath_height_c;
2168
+
} else {
2169
+
v->swath_height_y[k] = v->minimum_swath_height_y;
2170
+
v->swath_height_c[k] = v->minimum_swath_height_c;
2171
+
}
2172
+
if (v->swath_height_c[k] == 0.0) {
2173
+
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0;
2174
+
v->det_buffer_size_c[k] = 0.0;
2175
+
} else if (v->swath_height_y[k] <= v->swath_height_c[k]) {
2176
+
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
2177
+
v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
2178
+
} else {
2179
+
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0;
2180
+
v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 3.0;
2181
+
}
2182
+
}
2183
+
}
2184
+
void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(
2185
+
struct dcn_bw_internal_vars *v)
2186
+
{
2187
+
int k;
2188
+
/*dispclk and dppclk calculation*/
2189
+
2190
+
v->dispclk_with_ramping = 0.0;
2191
+
v->dispclk_without_ramping = 0.0;
2192
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2193
+
if (v->h_ratio[k] > 1.0) {
2194
+
v->pscl_throughput[k] = dcn_bw_min2(
2195
+
v->max_dchub_topscl_throughput,
2196
+
v->max_pscl_tolb_throughput * v->h_ratio[k]
2197
+
/ dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
2198
+
} else {
2199
+
v->pscl_throughput[k] = dcn_bw_min2(
2200
+
v->max_dchub_topscl_throughput,
2201
+
v->max_pscl_tolb_throughput);
2202
+
}
2203
+
v->dppclk_using_single_dpp_luma = v->pixel_clock[k]
2204
+
* dcn_bw_max3(
2205
+
v->vtaps[k] / 6.0 * dcn_bw_min2(1.0, v->h_ratio[k]),
2206
+
v->h_ratio[k] * v->v_ratio[k]
2207
+
/ v->pscl_throughput[k],
2208
+
1.0);
2209
+
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
2210
+
&& v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
2211
+
v->pscl_throughput_chroma[k] = 0.0;
2212
+
v->dppclk_using_single_dpp = v->dppclk_using_single_dpp_luma;
2213
+
} else {
2214
+
if (v->h_ratio[k] > 1.0) {
2215
+
v->pscl_throughput_chroma[k] =
2216
+
dcn_bw_min2(
2217
+
v->max_dchub_topscl_throughput,
2218
+
v->max_pscl_tolb_throughput
2219
+
* v->h_ratio[k]
2220
+
/ 2.0
2221
+
/ dcn_bw_ceil2(
2222
+
v->hta_pschroma[k]
2223
+
/ 6.0,
2224
+
1.0));
2225
+
} else {
2226
+
v->pscl_throughput_chroma[k] = dcn_bw_min2(
2227
+
v->max_dchub_topscl_throughput,
2228
+
v->max_pscl_tolb_throughput);
2229
+
}
2230
+
v->dppclk_using_single_dpp_chroma =
2231
+
v->pixel_clock[k]
2232
+
* dcn_bw_max3(
2233
+
v->vta_pschroma[k] / 6.0
2234
+
* dcn_bw_min2(
2235
+
1.0,
2236
+
v->h_ratio[k]
2237
+
/ 2.0),
2238
+
v->h_ratio[k]
2239
+
* v->v_ratio[k]
2240
+
/ 4.0
2241
+
/ v->pscl_throughput_chroma[k],
2242
+
1.0);
2243
+
v->dppclk_using_single_dpp = dcn_bw_max2(
2244
+
v->dppclk_using_single_dpp_luma,
2245
+
v->dppclk_using_single_dpp_chroma);
2246
+
}
2247
+
if (v->odm_capable == dcn_bw_yes) {
2248
+
v->dispclk_with_ramping =
2249
+
dcn_bw_max2(
2250
+
v->dispclk_with_ramping,
2251
+
dcn_bw_max2(
2252
+
v->dppclk_using_single_dpp
2253
+
/ v->dpp_per_plane[k]
2254
+
* v->dispclk_dppclk_ratio,
2255
+
v->pixel_clock[k]
2256
+
/ v->dpp_per_plane[k])
2257
+
* (1.0
2258
+
+ v->downspreading
2259
+
/ 100.0)
2260
+
* (1.0
2261
+
+ v->dispclk_ramping_margin
2262
+
/ 100.0));
2263
+
v->dispclk_without_ramping = dcn_bw_max2(
2264
+
v->dispclk_without_ramping,
2265
+
dcn_bw_max2(
2266
+
v->dppclk_using_single_dpp
2267
+
/ v->dpp_per_plane[k]
2268
+
* v->dispclk_dppclk_ratio,
2269
+
v->pixel_clock[k] / v->dpp_per_plane[k])
2270
+
* (1.0 + v->downspreading / 100.0));
2271
+
} else {
2272
+
v->dispclk_with_ramping =
2273
+
dcn_bw_max2(
2274
+
v->dispclk_with_ramping,
2275
+
dcn_bw_max2(
2276
+
v->dppclk_using_single_dpp
2277
+
/ v->dpp_per_plane[k]
2278
+
* v->dispclk_dppclk_ratio,
2279
+
v->pixel_clock[k])
2280
+
* (1.0
2281
+
+ v->downspreading
2282
+
/ 100.0)
2283
+
* (1.0
2284
+
+ v->dispclk_ramping_margin
2285
+
/ 100.0));
2286
+
v->dispclk_without_ramping = dcn_bw_max2(
2287
+
v->dispclk_without_ramping,
2288
+
dcn_bw_max2(
2289
+
v->dppclk_using_single_dpp
2290
+
/ v->dpp_per_plane[k]
2291
+
* v->dispclk_dppclk_ratio,
2292
+
v->pixel_clock[k])
2293
+
* (1.0 + v->downspreading / 100.0));
2294
+
}
2295
+
}
2296
+
if (v->dispclk_without_ramping > v->max_dispclk[number_of_states]) {
2297
+
v->dispclk = v->dispclk_without_ramping;
2298
+
} else if (v->dispclk_with_ramping > v->max_dispclk[number_of_states]) {
2299
+
v->dispclk = v->max_dispclk[number_of_states];
2300
+
} else {
2301
+
v->dispclk = v->dispclk_with_ramping;
2302
+
}
2303
+
v->dppclk = v->dispclk / v->dispclk_dppclk_ratio;
2304
+
/*urgent watermark*/
2305
+
2306
+
v->return_bandwidth_to_dcn = dcn_bw_min2(
2307
+
v->return_bus_width * v->dcfclk,
2308
+
v->fabric_and_dram_bandwidth * 1000.0
2309
+
* v->percent_of_ideal_drambw_received_after_urg_latency
2310
+
/ 100.0);
2311
+
v->dcc_enabled_any_plane = dcn_bw_no;
2312
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2313
+
if (v->dcc_enable[k] == dcn_bw_yes) {
2314
+
v->dcc_enabled_any_plane = dcn_bw_yes;
2315
+
}
2316
+
}
2317
+
v->return_bw = v->return_bandwidth_to_dcn;
2318
+
if (v->dcc_enabled_any_plane == dcn_bw_yes
2319
+
&& v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
2320
+
v->return_bw =
2321
+
dcn_bw_min2(
2322
+
v->return_bw,
2323
+
v->return_bandwidth_to_dcn * 4.0
2324
+
* (1.0
2325
+
- v->urgent_latency
2326
+
/ ((v->rob_buffer_size_in_kbyte
2327
+
- v->pixel_chunk_size_in_kbyte)
2328
+
* 1024.0
2329
+
/ (v->return_bandwidth_to_dcn
2330
+
- v->dcfclk
2331
+
* v->return_bus_width
2332
+
/ 4.0)
2333
+
+ v->urgent_latency)));
2334
+
}
2335
+
v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency
2336
+
/ (v->return_bandwidth_to_dcn * v->urgent_latency
2337
+
+ (v->rob_buffer_size_in_kbyte
2338
+
- v->pixel_chunk_size_in_kbyte) * 1024.0);
2339
+
if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0
2340
+
&& v->critical_compression < 4.0) {
2341
+
v->return_bw =
2342
+
dcn_bw_min2(
2343
+
v->return_bw,
2344
+
dcn_bw_pow(
2345
+
4.0 * v->return_bandwidth_to_dcn
2346
+
* (v->rob_buffer_size_in_kbyte
2347
+
- v->pixel_chunk_size_in_kbyte)
2348
+
* 1024.0
2349
+
* v->return_bus_width
2350
+
* v->dcfclk
2351
+
* v->urgent_latency
2352
+
/ (v->return_bandwidth_to_dcn
2353
+
* v->urgent_latency
2354
+
+ (v->rob_buffer_size_in_kbyte
2355
+
- v->pixel_chunk_size_in_kbyte)
2356
+
* 1024.0),
2357
+
2));
2358
+
}
2359
+
v->return_bandwidth_to_dcn = dcn_bw_min2(
2360
+
v->return_bus_width * v->dcfclk,
2361
+
v->fabric_and_dram_bandwidth * 1000.0);
2362
+
if (v->dcc_enabled_any_plane == dcn_bw_yes
2363
+
&& v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
2364
+
v->return_bw =
2365
+
dcn_bw_min2(
2366
+
v->return_bw,
2367
+
v->return_bandwidth_to_dcn * 4.0
2368
+
* (1.0
2369
+
- v->urgent_latency
2370
+
/ ((v->rob_buffer_size_in_kbyte
2371
+
- v->pixel_chunk_size_in_kbyte)
2372
+
* 1024.0
2373
+
/ (v->return_bandwidth_to_dcn
2374
+
- v->dcfclk
2375
+
* v->return_bus_width
2376
+
/ 4.0)
2377
+
+ v->urgent_latency)));
2378
+
}
2379
+
v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency
2380
+
/ (v->return_bandwidth_to_dcn * v->urgent_latency
2381
+
+ (v->rob_buffer_size_in_kbyte
2382
+
- v->pixel_chunk_size_in_kbyte) * 1024.0);
2383
+
if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0
2384
+
&& v->critical_compression < 4.0) {
2385
+
v->return_bw =
2386
+
dcn_bw_min2(
2387
+
v->return_bw,
2388
+
dcn_bw_pow(
2389
+
4.0 * v->return_bandwidth_to_dcn
2390
+
* (v->rob_buffer_size_in_kbyte
2391
+
- v->pixel_chunk_size_in_kbyte)
2392
+
* 1024.0
2393
+
* v->return_bus_width
2394
+
* v->dcfclk
2395
+
* v->urgent_latency
2396
+
/ (v->return_bandwidth_to_dcn
2397
+
* v->urgent_latency
2398
+
+ (v->rob_buffer_size_in_kbyte
2399
+
- v->pixel_chunk_size_in_kbyte)
2400
+
* 1024.0),
2401
+
2));
2402
+
}
2403
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2404
+
if (v->source_scan[k] == dcn_bw_hor) {
2405
+
v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
2406
+
} else {
2407
+
v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
2408
+
}
2409
+
}
2410
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2411
+
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
2412
+
v->byte_per_pixel_dety[k] = 8.0;
2413
+
v->byte_per_pixel_detc[k] = 0.0;
2414
+
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
2415
+
v->byte_per_pixel_dety[k] = 4.0;
2416
+
v->byte_per_pixel_detc[k] = 0.0;
2417
+
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
2418
+
v->byte_per_pixel_dety[k] = 2.0;
2419
+
v->byte_per_pixel_detc[k] = 0.0;
2420
+
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
2421
+
v->byte_per_pixel_dety[k] = 1.0;
2422
+
v->byte_per_pixel_detc[k] = 2.0;
2423
+
} else {
2424
+
v->byte_per_pixel_dety[k] = 4.0f / 3;
2425
+
v->byte_per_pixel_detc[k] = 8.0f / 3;
2426
+
}
2427
+
}
2428
+
v->total_data_read_bandwidth = 0.0;
2429
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2430
+
v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k]
2431
+
* dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0)
2432
+
/ (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
2433
+
v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k]
2434
+
* dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
2435
+
/ (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
2436
+
v->total_data_read_bandwidth = v->total_data_read_bandwidth
2437
+
+ v->read_bandwidth_plane_luma[k]
2438
+
+ v->read_bandwidth_plane_chroma[k];
2439
+
}
2440
+
v->total_active_dpp = 0.0;
2441
+
v->total_dcc_active_dpp = 0.0;
2442
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2443
+
v->total_active_dpp = v->total_active_dpp + v->dpp_per_plane[k];
2444
+
if (v->dcc_enable[k] == dcn_bw_yes) {
2445
+
v->total_dcc_active_dpp = v->total_dcc_active_dpp + v->dpp_per_plane[k];
2446
+
}
2447
+
}
2448
+
v->urgent_round_trip_and_out_of_order_latency = (v->round_trip_ping_latency_cycles + 32.0)
2449
+
/ v->dcfclk
2450
+
+ v->urgent_out_of_order_return_per_channel * v->number_of_channels
2451
+
/ v->return_bw;
2452
+
v->last_pixel_of_line_extra_watermark = 0.0;
2453
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2454
+
if (v->v_ratio[k] <= 1.0) {
2455
+
v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k]
2456
+
* v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
2457
+
} else {
2458
+
v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k]
2459
+
/ v->pscl_throughput[k] / v->dppclk;
2460
+
}
2461
+
v->data_fabric_line_delivery_time_luma =
2462
+
v->swath_width_y[k] * v->swath_height_y[k]
2463
+
* dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0)
2464
+
/ (v->return_bw * v->read_bandwidth_plane_luma[k]
2465
+
/ v->dpp_per_plane[k]
2466
+
/ v->total_data_read_bandwidth);
2467
+
v->last_pixel_of_line_extra_watermark = dcn_bw_max2(
2468
+
v->last_pixel_of_line_extra_watermark,
2469
+
v->data_fabric_line_delivery_time_luma
2470
+
- v->display_pipe_line_delivery_time_luma[k]);
2471
+
if (v->byte_per_pixel_detc[k] == 0.0) {
2472
+
v->display_pipe_line_delivery_time_chroma[k] = 0.0;
2473
+
} else {
2474
+
if (v->v_ratio[k] / 2.0 <= 1.0) {
2475
+
v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k]
2476
+
/ 2.0 * v->dpp_per_plane[k] / (v->h_ratio[k] / 2.0)
2477
+
/ v->pixel_clock[k];
2478
+
} else {
2479
+
v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k]
2480
+
/ 2.0 / v->pscl_throughput_chroma[k] / v->dppclk;
2481
+
}
2482
+
v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0
2483
+
* v->swath_height_c[k]
2484
+
* dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
2485
+
/ (v->return_bw * v->read_bandwidth_plane_chroma[k]
2486
+
/ v->dpp_per_plane[k]
2487
+
/ v->total_data_read_bandwidth);
2488
+
v->last_pixel_of_line_extra_watermark =
2489
+
dcn_bw_max2(
2490
+
v->last_pixel_of_line_extra_watermark,
2491
+
v->data_fabric_line_delivery_time_chroma
2492
+
- v->display_pipe_line_delivery_time_chroma[k]);
2493
+
}
2494
+
}
2495
+
v->urgent_extra_latency = v->urgent_round_trip_and_out_of_order_latency
2496
+
+ (v->total_active_dpp * v->pixel_chunk_size_in_kbyte
2497
+
+ v->total_dcc_active_dpp * v->meta_chunk_size) * 1024.0
2498
+
/ v->return_bw;
2499
+
if (v->pte_enable == dcn_bw_yes) {
2500
+
v->urgent_extra_latency = v->urgent_extra_latency
2501
+
+ v->total_active_dpp * v->pte_chunk_size * 1024.0 / v->return_bw;
2502
+
}
2503
+
v->urgent_watermark = v->urgent_latency + v->last_pixel_of_line_extra_watermark
2504
+
+ v->urgent_extra_latency;
2505
+
v->ptemeta_urgent_watermark = v->urgent_watermark + 2.0 * v->urgent_latency;
2506
+
/*nb p-state/dram clock change watermark*/
2507
+
2508
+
v->dram_clock_change_watermark = v->dram_clock_change_latency + v->urgent_watermark;
2509
+
v->total_active_writeback = 0.0;
2510
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2511
+
if (v->output[k] == dcn_bw_writeback) {
2512
+
v->total_active_writeback = v->total_active_writeback + 1.0;
2513
+
}
2514
+
}
2515
+
if (v->total_active_writeback <= 1.0) {
2516
+
v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency
2517
+
+ v->write_back_latency;
2518
+
} else {
2519
+
v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency
2520
+
+ v->write_back_latency
2521
+
+ v->writeback_chunk_size * 1024.0 / 32.0 / v->socclk;
2522
+
}
2523
+
/*stutter efficiency*/
2524
+
2525
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2526
+
v->lines_in_dety[k] = v->det_buffer_size_y[k] / v->byte_per_pixel_dety[k]
2527
+
/ v->swath_width_y[k];
2528
+
v->lines_in_dety_rounded_down_to_swath[k] = dcn_bw_floor2(
2529
+
v->lines_in_dety[k],
2530
+
v->swath_height_y[k]);
2531
+
v->full_det_buffering_time_y[k] = v->lines_in_dety_rounded_down_to_swath[k]
2532
+
* (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k];
2533
+
if (v->byte_per_pixel_detc[k] > 0.0) {
2534
+
v->lines_in_detc[k] = v->det_buffer_size_c[k] / v->byte_per_pixel_detc[k]
2535
+
/ (v->swath_width_y[k] / 2.0);
2536
+
v->lines_in_detc_rounded_down_to_swath[k] = dcn_bw_floor2(
2537
+
v->lines_in_detc[k],
2538
+
v->swath_height_c[k]);
2539
+
v->full_det_buffering_time_c[k] = v->lines_in_detc_rounded_down_to_swath[k]
2540
+
* (v->htotal[k] / v->pixel_clock[k])
2541
+
/ (v->v_ratio[k] / 2.0);
2542
+
} else {
2543
+
v->lines_in_detc[k] = 0.0;
2544
+
v->lines_in_detc_rounded_down_to_swath[k] = 0.0;
2545
+
v->full_det_buffering_time_c[k] = 999999.0;
2546
+
}
2547
+
}
2548
+
v->min_full_det_buffering_time = 999999.0;
2549
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2550
+
if (v->full_det_buffering_time_y[k] < v->min_full_det_buffering_time) {
2551
+
v->min_full_det_buffering_time = v->full_det_buffering_time_y[k];
2552
+
v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k]
2553
+
/ v->pixel_clock[k];
2554
+
}
2555
+
if (v->full_det_buffering_time_c[k] < v->min_full_det_buffering_time) {
2556
+
v->min_full_det_buffering_time = v->full_det_buffering_time_c[k];
2557
+
v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k]
2558
+
/ v->pixel_clock[k];
2559
+
}
2560
+
}
2561
+
v->average_read_bandwidth_gbyte_per_second = 0.0;
2562
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2563
+
if (v->dcc_enable[k] == dcn_bw_yes) {
2564
+
v->average_read_bandwidth_gbyte_per_second =
2565
+
v->average_read_bandwidth_gbyte_per_second
2566
+
+ v->read_bandwidth_plane_luma[k]
2567
+
/ v->dcc_rate[k] / 1000.0
2568
+
+ v->read_bandwidth_plane_chroma[k]
2569
+
/ v->dcc_rate[k] / 1000.0;
2570
+
} else {
2571
+
v->average_read_bandwidth_gbyte_per_second =
2572
+
v->average_read_bandwidth_gbyte_per_second
2573
+
+ v->read_bandwidth_plane_luma[k] / 1000.0
2574
+
+ v->read_bandwidth_plane_chroma[k]
2575
+
/ 1000.0;
2576
+
}
2577
+
if (v->dcc_enable[k] == dcn_bw_yes) {
2578
+
v->average_read_bandwidth_gbyte_per_second =
2579
+
v->average_read_bandwidth_gbyte_per_second
2580
+
+ v->read_bandwidth_plane_luma[k] / 1000.0
2581
+
/ 256.0
2582
+
+ v->read_bandwidth_plane_chroma[k] / 1000.0
2583
+
/ 256.0;
2584
+
}
2585
+
if (v->pte_enable == dcn_bw_yes) {
2586
+
v->average_read_bandwidth_gbyte_per_second =
2587
+
v->average_read_bandwidth_gbyte_per_second
2588
+
+ v->read_bandwidth_plane_luma[k] / 1000.0
2589
+
/ 512.0
2590
+
+ v->read_bandwidth_plane_chroma[k] / 1000.0
2591
+
/ 512.0;
2592
+
}
2593
+
}
2594
+
v->part_of_burst_that_fits_in_rob = dcn_bw_min2(
2595
+
v->min_full_det_buffering_time * v->total_data_read_bandwidth,
2596
+
v->rob_buffer_size_in_kbyte * 1024.0 * v->total_data_read_bandwidth
2597
+
/ (v->average_read_bandwidth_gbyte_per_second * 1000.0));
2598
+
v->stutter_burst_time = v->part_of_burst_that_fits_in_rob
2599
+
* (v->average_read_bandwidth_gbyte_per_second * 1000.0)
2600
+
/ v->total_data_read_bandwidth / v->return_bw
2601
+
+ (v->min_full_det_buffering_time * v->total_data_read_bandwidth
2602
+
- v->part_of_burst_that_fits_in_rob) / (v->dcfclk * 64.0);
2603
+
if (v->total_active_writeback == 0.0) {
2604
+
v->stutter_efficiency_not_including_vblank = (1.0
2605
+
- (v->sr_exit_time + v->stutter_burst_time)
2606
+
/ v->min_full_det_buffering_time) * 100.0;
2607
+
} else {
2608
+
v->stutter_efficiency_not_including_vblank = 0.0;
2609
+
}
2610
+
v->smallest_vblank = 999999.0;
2611
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2612
+
if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) {
2613
+
v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k]
2614
+
/ v->pixel_clock[k];
2615
+
} else {
2616
+
v->v_blank_time = 0.0;
2617
+
}
2618
+
v->smallest_vblank = dcn_bw_min2(v->smallest_vblank, v->v_blank_time);
2619
+
}
2620
+
v->stutter_efficiency = (v->stutter_efficiency_not_including_vblank / 100.0
2621
+
* (v->frame_time_for_min_full_det_buffering_time - v->smallest_vblank)
2622
+
+ v->smallest_vblank) / v->frame_time_for_min_full_det_buffering_time
2623
+
* 100.0;
2624
+
/*dcfclk deep sleep*/
2625
+
2626
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2627
+
if (v->byte_per_pixel_detc[k] > 0.0) {
2628
+
v->dcfclk_deep_sleep_per_plane[k] =
2629
+
dcn_bw_max2(
2630
+
1.1 * v->swath_width_y[k]
2631
+
* dcn_bw_ceil2(
2632
+
v->byte_per_pixel_dety[k],
2633
+
1.0) / 32.0
2634
+
/ v->display_pipe_line_delivery_time_luma[k],
2635
+
1.1 * v->swath_width_y[k] / 2.0
2636
+
* dcn_bw_ceil2(
2637
+
v->byte_per_pixel_detc[k],
2638
+
2.0) / 32.0
2639
+
/ v->display_pipe_line_delivery_time_chroma[k]);
2640
+
} else {
2641
+
v->dcfclk_deep_sleep_per_plane[k] = 1.1 * v->swath_width_y[k]
2642
+
* dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 64.0
2643
+
/ v->display_pipe_line_delivery_time_luma[k];
2644
+
}
2645
+
v->dcfclk_deep_sleep_per_plane[k] = dcn_bw_max2(
2646
+
v->dcfclk_deep_sleep_per_plane[k],
2647
+
v->pixel_clock[k] / 16.0);
2648
+
}
2649
+
v->dcf_clk_deep_sleep = 8.0;
2650
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2651
+
v->dcf_clk_deep_sleep = dcn_bw_max2(
2652
+
v->dcf_clk_deep_sleep,
2653
+
v->dcfclk_deep_sleep_per_plane[k]);
2654
+
}
2655
+
/*stutter watermark*/
2656
+
2657
+
v->stutter_exit_watermark = v->sr_exit_time + v->last_pixel_of_line_extra_watermark
2658
+
+ v->urgent_extra_latency + 10.0 / v->dcf_clk_deep_sleep;
2659
+
v->stutter_enter_plus_exit_watermark = v->sr_enter_plus_exit_time
2660
+
+ v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency;
2661
+
/*urgent latency supported*/
2662
+
2663
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2664
+
v->effective_det_plus_lb_lines_luma =
2665
+
dcn_bw_floor2(
2666
+
v->lines_in_dety[k]
2667
+
+ dcn_bw_min2(
2668
+
v->lines_in_dety[k]
2669
+
* v->dppclk
2670
+
* v->byte_per_pixel_dety[k]
2671
+
* v->pscl_throughput[k]
2672
+
/ (v->return_bw
2673
+
/ v->dpp_per_plane[k]),
2674
+
v->effective_lb_latency_hiding_source_lines_luma),
2675
+
v->swath_height_y[k]);
2676
+
v->urgent_latency_support_us_luma = v->effective_det_plus_lb_lines_luma
2677
+
* (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k]
2678
+
- v->effective_det_plus_lb_lines_luma * v->swath_width_y[k]
2679
+
* v->byte_per_pixel_dety[k]
2680
+
/ (v->return_bw / v->dpp_per_plane[k]);
2681
+
if (v->byte_per_pixel_detc[k] > 0.0) {
2682
+
v->effective_det_plus_lb_lines_chroma =
2683
+
dcn_bw_floor2(
2684
+
v->lines_in_detc[k]
2685
+
+ dcn_bw_min2(
2686
+
v->lines_in_detc[k]
2687
+
* v->dppclk
2688
+
* v->byte_per_pixel_detc[k]
2689
+
* v->pscl_throughput_chroma[k]
2690
+
/ (v->return_bw
2691
+
/ v->dpp_per_plane[k]),
2692
+
v->effective_lb_latency_hiding_source_lines_chroma),
2693
+
v->swath_height_c[k]);
2694
+
v->urgent_latency_support_us_chroma = v->effective_det_plus_lb_lines_chroma
2695
+
* (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0)
2696
+
- v->effective_det_plus_lb_lines_chroma
2697
+
* (v->swath_width_y[k] / 2.0)
2698
+
* v->byte_per_pixel_detc[k]
2699
+
/ (v->return_bw / v->dpp_per_plane[k]);
2700
+
v->urgent_latency_support_us[k] = dcn_bw_min2(
2701
+
v->urgent_latency_support_us_luma,
2702
+
v->urgent_latency_support_us_chroma);
2703
+
} else {
2704
+
v->urgent_latency_support_us[k] = v->urgent_latency_support_us_luma;
2705
+
}
2706
+
}
2707
+
v->min_urgent_latency_support_us = 999999.0;
2708
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2709
+
v->min_urgent_latency_support_us = dcn_bw_min2(
2710
+
v->min_urgent_latency_support_us,
2711
+
v->urgent_latency_support_us[k]);
2712
+
}
2713
+
/*non-urgent latency tolerance*/
2714
+
2715
+
v->non_urgent_latency_tolerance = v->min_urgent_latency_support_us - v->urgent_watermark;
2716
+
/*prefetch*/
2717
+
2718
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
2719
+
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64
2720
+
|| v->source_pixel_format[k] == dcn_bw_rgb_sub_32
2721
+
|| v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
2722
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
2723
+
v->block_height256_bytes_y = 1.0;
2724
+
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
2725
+
v->block_height256_bytes_y = 4.0;
2726
+
} else {
2727
+
v->block_height256_bytes_y = 8.0;
2728
+
}
2729
+
v->block_height256_bytes_c = 0.0;
2730
+
} else {
2731
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
2732
+
v->block_height256_bytes_y = 1.0;
2733
+
v->block_height256_bytes_c = 1.0;
2734
+
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
2735
+
v->block_height256_bytes_y = 16.0;
2736
+
v->block_height256_bytes_c = 8.0;
2737
+
} else {
2738
+
v->block_height256_bytes_y = 8.0;
2739
+
v->block_height256_bytes_c = 8.0;
2740
+
}
2741
+
}
2742
+
if (v->dcc_enable[k] == dcn_bw_yes) {
2743
+
v->meta_request_width_y = 64.0 * 256.0
2744
+
/ dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0)
2745
+
/ (8.0 * v->block_height256_bytes_y);
2746
+
v->meta_surf_width_y = dcn_bw_ceil2(
2747
+
v->swath_width_y[k] - 1.0,
2748
+
v->meta_request_width_y) + v->meta_request_width_y;
2749
+
v->meta_surf_height_y = dcn_bw_ceil2(
2750
+
v->viewport_height[k] - 1.0,
2751
+
8.0 * v->block_height256_bytes_y)
2752
+
+ 8.0 * v->block_height256_bytes_y;
2753
+
if (v->pte_enable == dcn_bw_yes) {
2754
+
v->meta_pte_bytes_frame_y =
2755
+
(dcn_bw_ceil2(
2756
+
(v->meta_surf_width_y
2757
+
* v->meta_surf_height_y
2758
+
* dcn_bw_ceil2(
2759
+
v->byte_per_pixel_dety[k],
2760
+
1.0)
2761
+
/ 256.0 - 4096.0)
2762
+
/ 8.0 / 4096.0,
2763
+
1.0) + 1) * 64.0;
2764
+
} else {
2765
+
v->meta_pte_bytes_frame_y = 0.0;
2766
+
}
2767
+
if (v->source_scan[k] == dcn_bw_hor) {
2768
+
v->meta_row_byte_y = v->meta_surf_width_y * 8.0
2769
+
* v->block_height256_bytes_y
2770
+
* dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
2771
+
} else {
2772
+
v->meta_row_byte_y = v->meta_surf_height_y * v->meta_request_width_y
2773
+
* dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
2774
+
}
2775
+
} else {
2776
+
v->meta_pte_bytes_frame_y = 0.0;
2777
+
v->meta_row_byte_y = 0.0;
2778
+
}
2779
+
if (v->pte_enable == dcn_bw_yes) {
2780
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
2781
+
v->macro_tile_size_byte_y = 256.0;
2782
+
v->macro_tile_height_y = 1.0;
2783
+
} else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s
2784
+
|| v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x
2785
+
|| v->source_surface_mode[k] == dcn_bw_sw_4_kb_d
2786
+
|| v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
2787
+
v->macro_tile_size_byte_y = 4096.0;
2788
+
v->macro_tile_height_y = 4.0 * v->block_height256_bytes_y;
2789
+
} else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s
2790
+
|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t
2791
+
|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x
2792
+
|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_d
2793
+
|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t
2794
+
|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
2795
+
v->macro_tile_size_byte_y = 64.0 * 1024;
2796
+
v->macro_tile_height_y = 16.0 * v->block_height256_bytes_y;
2797
+
} else {
2798
+
v->macro_tile_size_byte_y = 256.0 * 1024;
2799
+
v->macro_tile_height_y = 32.0 * v->block_height256_bytes_y;
2800
+
}
2801
+
if (v->macro_tile_size_byte_y <= 65536.0) {
2802
+
v->pixel_pte_req_height_y = v->macro_tile_height_y;
2803
+
} else {
2804
+
v->pixel_pte_req_height_y = 16.0 * v->block_height256_bytes_y;
2805
+
}
2806
+
v->pixel_pte_req_width_y = 4096.0 / dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0)
2807
+
/ v->pixel_pte_req_height_y * 8;
2808
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
2809
+
v->pixel_pte_bytes_per_row_y =
2810
+
64.0
2811
+
* (dcn_bw_ceil2(
2812
+
(v->swath_width_y[k]
2813
+
* dcn_bw_min2(
2814
+
128.0,
2815
+
dcn_bw_pow(
2816
+
2.0,
2817
+
dcn_bw_floor2(
2818
+
dcn_bw_log(
2819
+
v->pte_buffer_size_in_requests
2820
+
* v->pixel_pte_req_width_y
2821
+
/ v->swath_width_y[k],
2822
+
2.0),
2823
+
1.0)))
2824
+
- 1.0)
2825
+
/ v->pixel_pte_req_width_y,
2826
+
1.0) + 1);
2827
+
} else if (v->source_scan[k] == dcn_bw_hor) {
2828
+
v->pixel_pte_bytes_per_row_y =
2829
+
64.0
2830
+
* (dcn_bw_ceil2(
2831
+
(v->swath_width_y[k]
2832
+
- 1.0)
2833
+
/ v->pixel_pte_req_width_y,
2834
+
1.0) + 1);
2835
+
} else {
2836
+
v->pixel_pte_bytes_per_row_y =
2837
+
64.0
2838
+
* (dcn_bw_ceil2(
2839
+
(v->viewport_height[k]
2840
+
- 1.0)
2841
+
/ v->pixel_pte_req_height_y,
2842
+
1.0) + 1);
2843
+
}
2844
+
} else {
2845
+
v->pixel_pte_bytes_per_row_y = 0.0;
2846
+
}
2847
+
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64
2848
+
&& v->source_pixel_format[k] != dcn_bw_rgb_sub_32
2849
+
&& v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
2850
+
if (v->dcc_enable[k] == dcn_bw_yes) {
2851
+
v->meta_request_width_c = 64.0 * 256.0
2852
+
/ dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
2853
+
/ (8.0 * v->block_height256_bytes_c);
2854
+
v->meta_surf_width_c = dcn_bw_ceil2(
2855
+
v->swath_width_y[k] / 2.0 - 1.0,
2856
+
v->meta_request_width_c) + v->meta_request_width_c;
2857
+
v->meta_surf_height_c = dcn_bw_ceil2(
2858
+
v->viewport_height[k] / 2.0 - 1.0,
2859
+
8.0 * v->block_height256_bytes_c)
2860
+
+ 8.0 * v->block_height256_bytes_c;
2861
+
if (v->pte_enable == dcn_bw_yes) {
2862
+
v->meta_pte_bytes_frame_c =
2863
+
(dcn_bw_ceil2(
2864
+
(v->meta_surf_width_c
2865
+
* v->meta_surf_height_c
2866
+
* dcn_bw_ceil2(
2867
+
v->byte_per_pixel_detc[k],
2868
+
2.0)
2869
+
/ 256.0
2870
+
- 4096.0)
2871
+
/ 8.0
2872
+
/ 4096.0,
2873
+
1.0) + 1) * 64.0;
2874
+
} else {
2875
+
v->meta_pte_bytes_frame_c = 0.0;
2876
+
}
2877
+
if (v->source_scan[k] == dcn_bw_hor) {
2878
+
v->meta_row_byte_c = v->meta_surf_width_c * 8.0
2879
+
* v->block_height256_bytes_c
2880
+
* dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
2881
+
/ 256.0;
2882
+
} else {
2883
+
v->meta_row_byte_c = v->meta_surf_height_c
2884
+
* v->meta_request_width_c
2885
+
* dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
2886
+
/ 256.0;
2887
+
}
2888
+
} else {
2889
+
v->meta_pte_bytes_frame_c = 0.0;
2890
+
v->meta_row_byte_c = 0.0;
2891
+
}
2892
+
if (v->pte_enable == dcn_bw_yes) {
2893
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
2894
+
v->macro_tile_size_bytes_c = 256.0;
2895
+
v->macro_tile_height_c = 1.0;
2896
+
} else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s
2897
+
|| v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x
2898
+
|| v->source_surface_mode[k] == dcn_bw_sw_4_kb_d
2899
+
|| v->source_surface_mode[k]
2900
+
== dcn_bw_sw_4_kb_d_x) {
2901
+
v->macro_tile_size_bytes_c = 4096.0;
2902
+
v->macro_tile_height_c = 4.0 * v->block_height256_bytes_c;
2903
+
} else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s
2904
+
|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t
2905
+
|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x
2906
+
|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_d
2907
+
|| v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t
2908
+
|| v->source_surface_mode[k]
2909
+
== dcn_bw_sw_64_kb_d_x) {
2910
+
v->macro_tile_size_bytes_c = 64.0 * 1024;
2911
+
v->macro_tile_height_c = 16.0 * v->block_height256_bytes_c;
2912
+
} else {
2913
+
v->macro_tile_size_bytes_c = 256.0 * 1024;
2914
+
v->macro_tile_height_c = 32.0 * v->block_height256_bytes_c;
2915
+
}
2916
+
if (v->macro_tile_size_bytes_c <= 65536.0) {
2917
+
v->pixel_pte_req_height_c = v->macro_tile_height_c;
2918
+
} else {
2919
+
v->pixel_pte_req_height_c = 16.0
2920
+
* v->block_height256_bytes_c;
2921
+
}
2922
+
v->pixel_pte_req_width_c = 4096.0
2923
+
/ dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
2924
+
/ v->pixel_pte_req_height_c * 8;
2925
+
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
2926
+
v->pixel_pte_bytes_per_row_c =
2927
+
64.0
2928
+
* (dcn_bw_ceil2(
2929
+
(v->swath_width_y[k]
2930
+
/ 2.0
2931
+
* dcn_bw_min2(
2932
+
128.0,
2933
+
dcn_bw_pow(
2934
+
2.0,
2935
+
dcn_bw_floor2(
2936
+
dcn_bw_log(
2937
+
v->pte_buffer_size_in_requests
2938
+
* v->pixel_pte_req_width_c
2939
+
/ (v->swath_width_y[k]
2940
+
/ 2.0),
2941
+
2.0),
2942
+
1.0)))
2943
+
- 1.0)
2944
+
/ v->pixel_pte_req_width_c,
2945
+
1.0) + 1);
2946
+
} else if (v->source_scan[k] == dcn_bw_hor) {
2947
+
v->pixel_pte_bytes_per_row_c =
2948
+
64.0
2949
+
* (dcn_bw_ceil2(
2950
+
(v->swath_width_y[k]
2951
+
/ 2.0
2952
+
- 1.0)
2953
+
/ v->pixel_pte_req_width_c,
2954
+
1.0) + 1);
2955
+
} else {
2956
+
v->pixel_pte_bytes_per_row_c =
2957
+
64.0
2958
+
* (dcn_bw_ceil2(
2959
+
(v->viewport_height[k]
2960
+
/ 2.0
2961
+
- 1.0)
2962
+
/ v->pixel_pte_req_height_c,
2963
+
1.0) + 1);
2964
+
}
2965
+
} else {
2966
+
v->pixel_pte_bytes_per_row_c = 0.0;
2967
+
}
2968
+
} else {
2969
+
v->pixel_pte_bytes_per_row_c = 0.0;
2970
+
v->meta_pte_bytes_frame_c = 0.0;
2971
+
v->meta_row_byte_c = 0.0;
2972
+
}
2973
+
v->pixel_pte_bytes_per_row[k] = v->pixel_pte_bytes_per_row_y
2974
+
+ v->pixel_pte_bytes_per_row_c;
2975
+
v->meta_pte_bytes_frame[k] = v->meta_pte_bytes_frame_y + v->meta_pte_bytes_frame_c;
2976
+
v->meta_row_byte[k] = v->meta_row_byte_y + v->meta_row_byte_c;
2977
+
v->v_init_pre_fill_y[k] = dcn_bw_floor2(
2978
+
(v->v_ratio[k] + v->vtaps[k] + 1.0
2979
+
+ v->interlace_output[k] * 0.5 * v->v_ratio[k])
2980
+
/ 2.0,
2981
+
1.0);
2982
+
v->max_num_swath_y[k] = dcn_bw_ceil2(
2983
+
(v->v_init_pre_fill_y[k] - 1.0) / v->swath_height_y[k],
2984
+
1.0) + 1;
2985
+
if (v->v_init_pre_fill_y[k] > 1.0) {
2986
+
v->max_partial_swath_y = dcn_bw_mod(
2987
+
(v->v_init_pre_fill_y[k] - 2.0),
2988
+
v->swath_height_y[k]);
2989
+
} else {
2990
+
v->max_partial_swath_y = dcn_bw_mod(
2991
+
(v->v_init_pre_fill_y[k] + v->swath_height_y[k] - 2.0),
2992
+
v->swath_height_y[k]);
2993
+
}
2994
+
v->max_partial_swath_y = dcn_bw_max2(1.0, v->max_partial_swath_y);
2995
+
v->prefetch_source_lines_y[k] = v->max_num_swath_y[k] * v->swath_height_y[k]
2996
+
+ v->max_partial_swath_y;
2997
+
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64
2998
+
&& v->source_pixel_format[k] != dcn_bw_rgb_sub_32
2999
+
&& v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
3000
+
v->v_init_pre_fill_c[k] = dcn_bw_floor2(
3001
+
(v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0
3002
+
+ v->interlace_output[k] * 0.5
3003
+
* v->v_ratio[k] / 2.0)
3004
+
/ 2.0,
3005
+
1.0);
3006
+
v->max_num_swath_c[k] = dcn_bw_ceil2(
3007
+
(v->v_init_pre_fill_c[k] - 1.0) / v->swath_height_c[k],
3008
+
1.0) + 1;
3009
+
if (v->v_init_pre_fill_c[k] > 1.0) {
3010
+
v->max_partial_swath_c = dcn_bw_mod(
3011
+
(v->v_init_pre_fill_c[k] - 2.0),
3012
+
v->swath_height_c[k]);
3013
+
} else {
3014
+
v->max_partial_swath_c = dcn_bw_mod(
3015
+
(v->v_init_pre_fill_c[k] + v->swath_height_c[k]
3016
+
- 2.0),
3017
+
v->swath_height_c[k]);
3018
+
}
3019
+
v->max_partial_swath_c = dcn_bw_max2(1.0, v->max_partial_swath_c);
3020
+
} else {
3021
+
v->max_num_swath_c[k] = 0.0;
3022
+
v->max_partial_swath_c = 0.0;
3023
+
}
3024
+
v->prefetch_source_lines_c[k] = v->max_num_swath_c[k] * v->swath_height_c[k]
3025
+
+ v->max_partial_swath_c;
3026
+
}
3027
+
v->t_calc = 24.0 / v->dcf_clk_deep_sleep;
3028
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3029
+
if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one
3030
+
== dcn_bw_yes) {
3031
+
v->max_vstartup_lines[k] = v->vtotal[k] - v->vactive[k] - 1.0;
3032
+
} else {
3033
+
v->max_vstartup_lines[k] = v->v_sync_plus_back_porch[k] - 1.0;
3034
+
}
3035
+
}
3036
+
v->next_prefetch_mode = 0.0;
3037
+
do {
3038
+
v->v_startup_lines = 13.0;
3039
+
do {
3040
+
v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw =
3041
+
dcn_bw_yes;
3042
+
v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 =
3043
+
dcn_bw_no;
3044
+
v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 =
3045
+
dcn_bw_no;
3046
+
v->v_ratio_prefetch_more_than4 = dcn_bw_no;
3047
+
v->destination_line_times_for_prefetch_less_than2 = dcn_bw_no;
3048
+
v->prefetch_mode = v->next_prefetch_mode;
3049
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3050
+
v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk
3051
+
+ 42.0 * v->pixel_clock[k] / v->dispclk;
3052
+
if (v->dpp_per_plane[k] > 1.0) {
3053
+
v->dstx_after_scaler = v->dstx_after_scaler
3054
+
+ v->scaler_rec_out_width[k] / 2.0;
3055
+
}
3056
+
if (v->output_format[k] == dcn_bw_420) {
3057
+
v->dsty_after_scaler = 1.0;
3058
+
} else {
3059
+
v->dsty_after_scaler = 0.0;
3060
+
}
3061
+
v->v_update_offset_pix = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
3062
+
v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters
3063
+
* (2.0 / v->dppclk + 3.0 / v->dispclk);
3064
+
v->v_update_width_pix = (14.0 / v->dcf_clk_deep_sleep
3065
+
+ 12.0 / v->dppclk + v->total_repeater_delay_time)
3066
+
* v->pixel_clock[k];
3067
+
v->v_ready_offset_pix = dcn_bw_max2(
3068
+
150.0 / v->dppclk,
3069
+
v->total_repeater_delay_time
3070
+
+ 20.0 / v->dcf_clk_deep_sleep
3071
+
+ 10.0 / v->dppclk)
3072
+
* v->pixel_clock[k];
3073
+
v->t_setup = (v->v_update_offset_pix + v->v_update_width_pix
3074
+
+ v->v_ready_offset_pix) / v->pixel_clock[k];
3075
+
v->v_startup[k] = dcn_bw_min2(
3076
+
v->v_startup_lines,
3077
+
v->max_vstartup_lines[k]);
3078
+
if (v->prefetch_mode == 0.0) {
3079
+
v->t_wait = dcn_bw_max3(
3080
+
v->dram_clock_change_latency
3081
+
+ v->urgent_latency,
3082
+
v->sr_enter_plus_exit_time,
3083
+
v->urgent_latency);
3084
+
} else if (v->prefetch_mode == 1.0) {
3085
+
v->t_wait = dcn_bw_max2(
3086
+
v->sr_enter_plus_exit_time,
3087
+
v->urgent_latency);
3088
+
} else {
3089
+
v->t_wait = v->urgent_latency;
3090
+
}
3091
+
v->destination_lines_for_prefetch[k] =
3092
+
dcn_bw_floor2(
3093
+
4.0
3094
+
* (v->v_startup[k]
3095
+
- v->t_wait
3096
+
/ (v->htotal[k]
3097
+
/ v->pixel_clock[k])
3098
+
- (v->t_calc
3099
+
+ v->t_setup)
3100
+
/ (v->htotal[k]
3101
+
/ v->pixel_clock[k])
3102
+
- (v->dsty_after_scaler
3103
+
+ v->dstx_after_scaler
3104
+
/ v->htotal[k])
3105
+
+ 0.125),
3106
+
1.0) / 4;
3107
+
if (v->destination_lines_for_prefetch[k] > 0.0) {
3108
+
v->prefetch_bandwidth[k] =
3109
+
(v->meta_pte_bytes_frame[k]
3110
+
+ 2.0 * v->meta_row_byte[k]
3111
+
+ 2.0
3112
+
* v->pixel_pte_bytes_per_row[k]
3113
+
+ v->prefetch_source_lines_y[k]
3114
+
* v->swath_width_y[k]
3115
+
* dcn_bw_ceil2(
3116
+
v->byte_per_pixel_dety[k],
3117
+
1.0)
3118
+
+ v->prefetch_source_lines_c[k]
3119
+
* v->swath_width_y[k]
3120
+
/ 2.0
3121
+
* dcn_bw_ceil2(
3122
+
v->byte_per_pixel_detc[k],
3123
+
2.0))
3124
+
/ (v->destination_lines_for_prefetch[k]
3125
+
* v->htotal[k]
3126
+
/ v->pixel_clock[k]);
3127
+
} else {
3128
+
v->prefetch_bandwidth[k] = 999999.0;
3129
+
}
3130
+
}
3131
+
v->bandwidth_available_for_immediate_flip = v->return_bw;
3132
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3133
+
v->bandwidth_available_for_immediate_flip =
3134
+
v->bandwidth_available_for_immediate_flip
3135
+
- dcn_bw_max2(
3136
+
v->read_bandwidth_plane_luma[k]
3137
+
+ v->read_bandwidth_plane_chroma[k],
3138
+
v->prefetch_bandwidth[k]);
3139
+
}
3140
+
v->tot_immediate_flip_bytes = 0.0;
3141
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3142
+
if (v->immediate_flip_supported == dcn_bw_yes
3143
+
&& (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
3144
+
&& v->source_pixel_format[k]
3145
+
!= dcn_bw_yuv420_sub_10)) {
3146
+
v->tot_immediate_flip_bytes = v->tot_immediate_flip_bytes
3147
+
+ v->meta_pte_bytes_frame[k]
3148
+
+ v->meta_row_byte[k]
3149
+
+ v->pixel_pte_bytes_per_row[k];
3150
+
}
3151
+
}
3152
+
v->max_rd_bandwidth = 0.0;
3153
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3154
+
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
3155
+
if (v->immediate_flip_supported == dcn_bw_yes
3156
+
&& (v->source_pixel_format[k]
3157
+
!= dcn_bw_yuv420_sub_8
3158
+
&& v->source_pixel_format[k]
3159
+
!= dcn_bw_yuv420_sub_10)) {
3160
+
v->time_for_fetching_meta_pte =
3161
+
dcn_bw_max5(
3162
+
v->meta_pte_bytes_frame[k]
3163
+
/ v->prefetch_bandwidth[k],
3164
+
v->meta_pte_bytes_frame[k]
3165
+
* v->tot_immediate_flip_bytes
3166
+
/ (v->bandwidth_available_for_immediate_flip
3167
+
* (v->meta_pte_bytes_frame[k]
3168
+
+ v->meta_row_byte[k]
3169
+
+ v->pixel_pte_bytes_per_row[k])),
3170
+
v->urgent_extra_latency,
3171
+
v->urgent_latency,
3172
+
v->htotal[k]
3173
+
/ v->pixel_clock[k]
3174
+
/ 4.0);
3175
+
} else {
3176
+
v->time_for_fetching_meta_pte =
3177
+
dcn_bw_max3(
3178
+
v->meta_pte_bytes_frame[k]
3179
+
/ v->prefetch_bandwidth[k],
3180
+
v->urgent_extra_latency,
3181
+
v->htotal[k]
3182
+
/ v->pixel_clock[k]
3183
+
/ 4.0);
3184
+
}
3185
+
} else {
3186
+
v->time_for_fetching_meta_pte = v->htotal[k]
3187
+
/ v->pixel_clock[k] / 4.0;
3188
+
}
3189
+
v->destination_lines_to_request_vm_inv_blank[k] =
3190
+
dcn_bw_floor2(
3191
+
4.0
3192
+
* (v->time_for_fetching_meta_pte
3193
+
/ (v->htotal[k]
3194
+
/ v->pixel_clock[k])
3195
+
+ 0.125),
3196
+
1.0) / 4;
3197
+
if ((v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes)) {
3198
+
if (v->immediate_flip_supported == dcn_bw_yes
3199
+
&& (v->source_pixel_format[k]
3200
+
!= dcn_bw_yuv420_sub_8
3201
+
&& v->source_pixel_format[k]
3202
+
!= dcn_bw_yuv420_sub_10)) {
3203
+
v->time_for_fetching_row_in_vblank =
3204
+
dcn_bw_max5(
3205
+
(v->meta_row_byte[k]
3206
+
+ v->pixel_pte_bytes_per_row[k])
3207
+
/ v->prefetch_bandwidth[k],
3208
+
(v->meta_row_byte[k]
3209
+
+ v->pixel_pte_bytes_per_row[k])
3210
+
* v->tot_immediate_flip_bytes
3211
+
/ (v->bandwidth_available_for_immediate_flip
3212
+
* (v->meta_pte_bytes_frame[k]
3213
+
+ v->meta_row_byte[k]
3214
+
+ v->pixel_pte_bytes_per_row[k])),
3215
+
v->urgent_extra_latency,
3216
+
2.0
3217
+
* v->urgent_latency,
3218
+
v->htotal[k]
3219
+
/ v->pixel_clock[k]
3220
+
- v->time_for_fetching_meta_pte);
3221
+
} else {
3222
+
v->time_for_fetching_row_in_vblank =
3223
+
dcn_bw_max3(
3224
+
(v->meta_row_byte[k]
3225
+
+ v->pixel_pte_bytes_per_row[k])
3226
+
/ v->prefetch_bandwidth[k],
3227
+
v->urgent_extra_latency,
3228
+
v->htotal[k]
3229
+
/ v->pixel_clock[k]
3230
+
- v->time_for_fetching_meta_pte);
3231
+
}
3232
+
} else {
3233
+
v->time_for_fetching_row_in_vblank =
3234
+
dcn_bw_max2(
3235
+
v->urgent_extra_latency
3236
+
- v->time_for_fetching_meta_pte,
3237
+
v->htotal[k]
3238
+
/ v->pixel_clock[k]
3239
+
- v->time_for_fetching_meta_pte);
3240
+
}
3241
+
v->destination_lines_to_request_row_in_vblank[k] =
3242
+
dcn_bw_floor2(
3243
+
4.0
3244
+
* (v->time_for_fetching_row_in_vblank
3245
+
/ (v->htotal[k]
3246
+
/ v->pixel_clock[k])
3247
+
+ 0.125),
3248
+
1.0) / 4;
3249
+
v->lines_to_request_prefetch_pixel_data =
3250
+
v->destination_lines_for_prefetch[k]
3251
+
- v->destination_lines_to_request_vm_inv_blank[k]
3252
+
- v->destination_lines_to_request_row_in_vblank[k];
3253
+
if (v->lines_to_request_prefetch_pixel_data > 0.0) {
3254
+
v->v_ratio_prefetch_y[k] = v->prefetch_source_lines_y[k]
3255
+
/ v->lines_to_request_prefetch_pixel_data;
3256
+
if ((v->swath_height_y[k] > 4.0)) {
3257
+
if (v->lines_to_request_prefetch_pixel_data
3258
+
> (v->v_init_pre_fill_y[k] - 3.0)
3259
+
/ 2.0) {
3260
+
v->v_ratio_prefetch_y[k] =
3261
+
dcn_bw_max2(
3262
+
v->v_ratio_prefetch_y[k],
3263
+
v->max_num_swath_y[k]
3264
+
* v->swath_height_y[k]
3265
+
/ (v->lines_to_request_prefetch_pixel_data
3266
+
- (v->v_init_pre_fill_y[k]
3267
+
- 3.0)
3268
+
/ 2.0));
3269
+
} else {
3270
+
v->v_ratio_prefetch_y[k] = 999999.0;
3271
+
}
3272
+
}
3273
+
} else {
3274
+
v->v_ratio_prefetch_y[k] = 999999.0;
3275
+
}
3276
+
v->v_ratio_prefetch_y[k] = dcn_bw_max2(v->v_ratio_prefetch_y[k], 1.0);
3277
+
if (v->lines_to_request_prefetch_pixel_data > 0.0) {
3278
+
v->v_ratio_prefetch_c[k] = v->prefetch_source_lines_c[k]
3279
+
/ v->lines_to_request_prefetch_pixel_data;
3280
+
if ((v->swath_height_c[k] > 4.0)) {
3281
+
if (v->lines_to_request_prefetch_pixel_data
3282
+
> (v->v_init_pre_fill_c[k] - 3.0)
3283
+
/ 2.0) {
3284
+
v->v_ratio_prefetch_c[k] =
3285
+
dcn_bw_max2(
3286
+
v->v_ratio_prefetch_c[k],
3287
+
v->max_num_swath_c[k]
3288
+
* v->swath_height_c[k]
3289
+
/ (v->lines_to_request_prefetch_pixel_data
3290
+
- (v->v_init_pre_fill_c[k]
3291
+
- 3.0)
3292
+
/ 2.0));
3293
+
} else {
3294
+
v->v_ratio_prefetch_c[k] = 999999.0;
3295
+
}
3296
+
}
3297
+
} else {
3298
+
v->v_ratio_prefetch_c[k] = 999999.0;
3299
+
}
3300
+
v->v_ratio_prefetch_c[k] = dcn_bw_max2(v->v_ratio_prefetch_c[k], 1.0);
3301
+
if (v->lines_to_request_prefetch_pixel_data > 0.0) {
3302
+
v->required_prefetch_pix_data_bw =
3303
+
v->dpp_per_plane[k]
3304
+
* (v->prefetch_source_lines_y[k]
3305
+
/ v->lines_to_request_prefetch_pixel_data
3306
+
* dcn_bw_ceil2(
3307
+
v->byte_per_pixel_dety[k],
3308
+
1.0)
3309
+
+ v->prefetch_source_lines_c[k]
3310
+
/ v->lines_to_request_prefetch_pixel_data
3311
+
* dcn_bw_ceil2(
3312
+
v->byte_per_pixel_detc[k],
3313
+
2.0)
3314
+
/ 2.0)
3315
+
* v->swath_width_y[k]
3316
+
/ (v->htotal[k]
3317
+
/ v->pixel_clock[k]);
3318
+
} else {
3319
+
v->required_prefetch_pix_data_bw = 999999.0;
3320
+
}
3321
+
v->max_rd_bandwidth =
3322
+
v->max_rd_bandwidth
3323
+
+ dcn_bw_max2(
3324
+
v->read_bandwidth_plane_luma[k]
3325
+
+ v->read_bandwidth_plane_chroma[k],
3326
+
v->required_prefetch_pix_data_bw);
3327
+
if (v->immediate_flip_supported == dcn_bw_yes
3328
+
&& (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
3329
+
&& v->source_pixel_format[k]
3330
+
!= dcn_bw_yuv420_sub_10)) {
3331
+
v->max_rd_bandwidth =
3332
+
v->max_rd_bandwidth
3333
+
+ dcn_bw_max2(
3334
+
v->meta_pte_bytes_frame[k]
3335
+
/ (v->destination_lines_to_request_vm_inv_blank[k]
3336
+
* v->htotal[k]
3337
+
/ v->pixel_clock[k]),
3338
+
(v->meta_row_byte[k]
3339
+
+ v->pixel_pte_bytes_per_row[k])
3340
+
/ (v->destination_lines_to_request_row_in_vblank[k]
3341
+
* v->htotal[k]
3342
+
/ v->pixel_clock[k]));
3343
+
}
3344
+
if (v->v_ratio_prefetch_y[k] > 4.0
3345
+
|| v->v_ratio_prefetch_c[k] > 4.0) {
3346
+
v->v_ratio_prefetch_more_than4 = dcn_bw_yes;
3347
+
}
3348
+
if (v->destination_lines_for_prefetch[k] < 2.0) {
3349
+
v->destination_line_times_for_prefetch_less_than2 =
3350
+
dcn_bw_yes;
3351
+
}
3352
+
if (v->max_vstartup_lines[k] > v->v_startup_lines) {
3353
+
if (v->required_prefetch_pix_data_bw
3354
+
> (v->read_bandwidth_plane_luma[k]
3355
+
+ v->read_bandwidth_plane_chroma[k])) {
3356
+
v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw =
3357
+
dcn_bw_no;
3358
+
}
3359
+
if (v->v_ratio_prefetch_y[k] > 4.0
3360
+
|| v->v_ratio_prefetch_c[k] > 4.0) {
3361
+
v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 =
3362
+
dcn_bw_yes;
3363
+
}
3364
+
if (v->destination_lines_for_prefetch[k] < 2.0) {
3365
+
v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 =
3366
+
dcn_bw_yes;
3367
+
}
3368
+
}
3369
+
}
3370
+
if (v->max_rd_bandwidth <= v->return_bw
3371
+
&& v->v_ratio_prefetch_more_than4 == dcn_bw_no
3372
+
&& v->destination_line_times_for_prefetch_less_than2
3373
+
== dcn_bw_no) {
3374
+
v->prefetch_mode_supported = dcn_bw_yes;
3375
+
} else {
3376
+
v->prefetch_mode_supported = dcn_bw_no;
3377
+
}
3378
+
v->v_startup_lines = v->v_startup_lines + 1.0;
3379
+
} while (!(v->prefetch_mode_supported == dcn_bw_yes
3380
+
|| (v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw
3381
+
== dcn_bw_yes
3382
+
&& v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4
3383
+
== dcn_bw_no
3384
+
&& v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2
3385
+
== dcn_bw_no)));
3386
+
v->next_prefetch_mode = v->next_prefetch_mode + 1.0;
3387
+
} while (!(v->prefetch_mode_supported == dcn_bw_yes || v->prefetch_mode == 2.0));
3388
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3389
+
if (v->v_ratio_prefetch_y[k] <= 1.0) {
3390
+
v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k]
3391
+
* v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
3392
+
} else {
3393
+
v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k]
3394
+
/ v->pscl_throughput[k] / v->dppclk;
3395
+
}
3396
+
if (v->byte_per_pixel_detc[k] == 0.0) {
3397
+
v->display_pipe_line_delivery_time_chroma_prefetch[k] = 0.0;
3398
+
} else {
3399
+
if (v->v_ratio_prefetch_c[k] <= 1.0) {
3400
+
v->display_pipe_line_delivery_time_chroma_prefetch[k] =
3401
+
v->swath_width_y[k] * v->dpp_per_plane[k]
3402
+
/ v->h_ratio[k] / v->pixel_clock[k];
3403
+
} else {
3404
+
v->display_pipe_line_delivery_time_chroma_prefetch[k] =
3405
+
v->swath_width_y[k] / v->pscl_throughput[k]
3406
+
/ v->dppclk;
3407
+
}
3408
+
}
3409
+
}
3410
+
/*min ttuv_blank*/
3411
+
3412
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3413
+
if (v->prefetch_mode == 0.0) {
3414
+
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_yes;
3415
+
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
3416
+
v->min_ttuv_blank[k] = v->t_calc
3417
+
+ dcn_bw_max3(
3418
+
v->dram_clock_change_watermark,
3419
+
v->stutter_enter_plus_exit_watermark,
3420
+
v->urgent_watermark);
3421
+
} else if (v->prefetch_mode == 1.0) {
3422
+
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
3423
+
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
3424
+
v->min_ttuv_blank[k] = v->t_calc
3425
+
+ dcn_bw_max2(
3426
+
v->stutter_enter_plus_exit_watermark,
3427
+
v->urgent_watermark);
3428
+
} else {
3429
+
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
3430
+
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_no;
3431
+
v->min_ttuv_blank[k] = v->t_calc + v->urgent_watermark;
3432
+
}
3433
+
}
3434
+
/*nb p-state/dram clock change support*/
3435
+
3436
+
v->active_dp_ps = 0.0;
3437
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3438
+
v->active_dp_ps = v->active_dp_ps + v->dpp_per_plane[k];
3439
+
}
3440
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3441
+
v->lb_latency_hiding_source_lines_y =
3442
+
dcn_bw_min2(
3443
+
v->max_line_buffer_lines,
3444
+
dcn_bw_floor2(
3445
+
v->line_buffer_size
3446
+
/ v->lb_bit_per_pixel[k]
3447
+
/ (v->swath_width_y[k]
3448
+
/ dcn_bw_max2(
3449
+
v->h_ratio[k],
3450
+
1.0)),
3451
+
1.0)) - (v->vtaps[k] - 1.0);
3452
+
v->lb_latency_hiding_source_lines_c =
3453
+
dcn_bw_min2(
3454
+
v->max_line_buffer_lines,
3455
+
dcn_bw_floor2(
3456
+
v->line_buffer_size
3457
+
/ v->lb_bit_per_pixel[k]
3458
+
/ (v->swath_width_y[k]
3459
+
/ 2.0
3460
+
/ dcn_bw_max2(
3461
+
v->h_ratio[k]
3462
+
/ 2.0,
3463
+
1.0)),
3464
+
1.0)) - (v->vta_pschroma[k] - 1.0);
3465
+
v->effective_lb_latency_hiding_y = v->lb_latency_hiding_source_lines_y
3466
+
/ v->v_ratio[k] * (v->htotal[k] / v->pixel_clock[k]);
3467
+
v->effective_lb_latency_hiding_c = v->lb_latency_hiding_source_lines_c
3468
+
/ (v->v_ratio[k] / 2.0) * (v->htotal[k] / v->pixel_clock[k]);
3469
+
if (v->swath_width_y[k] > 2.0 * v->dpp_output_buffer_pixels) {
3470
+
v->dpp_output_buffer_lines_y = v->dpp_output_buffer_pixels
3471
+
/ v->swath_width_y[k];
3472
+
} else if (v->swath_width_y[k] > v->dpp_output_buffer_pixels) {
3473
+
v->dpp_output_buffer_lines_y = 0.5;
3474
+
} else {
3475
+
v->dpp_output_buffer_lines_y = 1.0;
3476
+
}
3477
+
if (v->swath_width_y[k] / 2.0 > 2.0 * v->dpp_output_buffer_pixels) {
3478
+
v->dpp_output_buffer_lines_c = v->dpp_output_buffer_pixels
3479
+
/ (v->swath_width_y[k] / 2.0);
3480
+
} else if (v->swath_width_y[k] / 2.0 > v->dpp_output_buffer_pixels) {
3481
+
v->dpp_output_buffer_lines_c = 0.5;
3482
+
} else {
3483
+
v->dpp_output_buffer_lines_c = 1.0;
3484
+
}
3485
+
v->dppopp_buffering_y = (v->htotal[k] / v->pixel_clock[k])
3486
+
* (v->dpp_output_buffer_lines_y + v->opp_output_buffer_lines);
3487
+
v->max_det_buffering_time_y = v->full_det_buffering_time_y[k]
3488
+
+ (v->lines_in_dety[k] - v->lines_in_dety_rounded_down_to_swath[k])
3489
+
/ v->swath_height_y[k]
3490
+
* (v->htotal[k] / v->pixel_clock[k]);
3491
+
v->active_dram_clock_change_latency_margin_y = v->dppopp_buffering_y
3492
+
+ v->effective_lb_latency_hiding_y + v->max_det_buffering_time_y
3493
+
- v->dram_clock_change_watermark;
3494
+
if (v->active_dp_ps > 1.0) {
3495
+
v->active_dram_clock_change_latency_margin_y =
3496
+
v->active_dram_clock_change_latency_margin_y
3497
+
- (1.0 - 1.0 / (v->active_dp_ps - 1.0))
3498
+
* v->swath_height_y[k]
3499
+
* (v->htotal[k]
3500
+
/ v->pixel_clock[k]);
3501
+
}
3502
+
if (v->byte_per_pixel_detc[k] > 0.0) {
3503
+
v->dppopp_buffering_c =
3504
+
(v->htotal[k] / v->pixel_clock[k])
3505
+
* (v->dpp_output_buffer_lines_c
3506
+
+ v->opp_output_buffer_lines);
3507
+
v->max_det_buffering_time_c = v->full_det_buffering_time_c[k]
3508
+
+ (v->lines_in_detc[k]
3509
+
- v->lines_in_detc_rounded_down_to_swath[k])
3510
+
/ v->swath_height_c[k]
3511
+
* (v->htotal[k] / v->pixel_clock[k]);
3512
+
v->active_dram_clock_change_latency_margin_c = v->dppopp_buffering_c
3513
+
+ v->effective_lb_latency_hiding_c
3514
+
+ v->max_det_buffering_time_c
3515
+
- v->dram_clock_change_watermark;
3516
+
if (v->active_dp_ps > 1.0) {
3517
+
v->active_dram_clock_change_latency_margin_c =
3518
+
v->active_dram_clock_change_latency_margin_c
3519
+
- (1.0
3520
+
- 1.0
3521
+
/ (v->active_dp_ps
3522
+
- 1.0))
3523
+
* v->swath_height_c[k]
3524
+
* (v->htotal[k]
3525
+
/ v->pixel_clock[k]);
3526
+
}
3527
+
v->active_dram_clock_change_latency_margin[k] = dcn_bw_min2(
3528
+
v->active_dram_clock_change_latency_margin_y,
3529
+
v->active_dram_clock_change_latency_margin_c);
3530
+
} else {
3531
+
v->active_dram_clock_change_latency_margin[k] =
3532
+
v->active_dram_clock_change_latency_margin_y;
3533
+
}
3534
+
if (v->output_format[k] == dcn_bw_444) {
3535
+
v->writeback_dram_clock_change_latency_margin =
3536
+
(v->writeback_luma_buffer_size
3537
+
+ v->writeback_chroma_buffer_size) * 1024.0
3538
+
/ (v->scaler_rec_out_width[k]
3539
+
/ (v->htotal[k]
3540
+
/ v->pixel_clock[k])
3541
+
* 4.0)
3542
+
- v->writeback_dram_clock_change_watermark;
3543
+
} else {
3544
+
v->writeback_dram_clock_change_latency_margin = dcn_bw_min2(
3545
+
v->writeback_luma_buffer_size,
3546
+
2.0 * v->writeback_chroma_buffer_size) * 1024.0
3547
+
/ (v->scaler_rec_out_width[k]
3548
+
/ (v->htotal[k] / v->pixel_clock[k]))
3549
+
- v->writeback_dram_clock_change_watermark;
3550
+
}
3551
+
if (v->output[k] == dcn_bw_writeback) {
3552
+
v->active_dram_clock_change_latency_margin[k] = dcn_bw_min2(
3553
+
v->active_dram_clock_change_latency_margin[k],
3554
+
v->writeback_dram_clock_change_latency_margin);
3555
+
}
3556
+
}
3557
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3558
+
if (v->allow_dram_clock_change_during_vblank[k] == dcn_bw_yes) {
3559
+
v->v_blank_dram_clock_change_latency_margin[k] = (v->vtotal[k]
3560
+
- v->scaler_recout_height[k])
3561
+
* (v->htotal[k] / v->pixel_clock[k])
3562
+
- dcn_bw_max2(
3563
+
v->dram_clock_change_watermark,
3564
+
v->writeback_dram_clock_change_watermark);
3565
+
} else {
3566
+
v->v_blank_dram_clock_change_latency_margin[k] = 0.0;
3567
+
}
3568
+
}
3569
+
v->min_active_dram_clock_change_margin = 999999.0;
3570
+
v->v_blank_of_min_active_dram_clock_change_margin = 999999.0;
3571
+
v->second_min_active_dram_clock_change_margin = 999999.0;
3572
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3573
+
if (v->active_dram_clock_change_latency_margin[k]
3574
+
< v->min_active_dram_clock_change_margin) {
3575
+
v->second_min_active_dram_clock_change_margin =
3576
+
v->min_active_dram_clock_change_margin;
3577
+
v->min_active_dram_clock_change_margin =
3578
+
v->active_dram_clock_change_latency_margin[k];
3579
+
v->v_blank_of_min_active_dram_clock_change_margin =
3580
+
v->v_blank_dram_clock_change_latency_margin[k];
3581
+
} else if (v->active_dram_clock_change_latency_margin[k]
3582
+
< v->second_min_active_dram_clock_change_margin) {
3583
+
v->second_min_active_dram_clock_change_margin =
3584
+
v->active_dram_clock_change_latency_margin[k];
3585
+
}
3586
+
}
3587
+
v->min_vblank_dram_clock_change_margin = 999999.0;
3588
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3589
+
if (v->min_vblank_dram_clock_change_margin
3590
+
> v->v_blank_dram_clock_change_latency_margin[k]) {
3591
+
v->min_vblank_dram_clock_change_margin =
3592
+
v->v_blank_dram_clock_change_latency_margin[k];
3593
+
}
3594
+
}
3595
+
if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) {
3596
+
v->dram_clock_change_margin = dcn_bw_max2(
3597
+
v->min_active_dram_clock_change_margin,
3598
+
v->min_vblank_dram_clock_change_margin);
3599
+
} else if (v->v_blank_of_min_active_dram_clock_change_margin
3600
+
> v->min_active_dram_clock_change_margin) {
3601
+
v->dram_clock_change_margin = dcn_bw_min2(
3602
+
v->second_min_active_dram_clock_change_margin,
3603
+
v->v_blank_of_min_active_dram_clock_change_margin);
3604
+
} else {
3605
+
v->dram_clock_change_margin = v->min_active_dram_clock_change_margin;
3606
+
}
3607
+
if (v->min_active_dram_clock_change_margin > 0.0) {
3608
+
v->dram_clock_change_support = dcn_bw_supported_in_v_active;
3609
+
} else if (v->dram_clock_change_margin > 0.0) {
3610
+
v->dram_clock_change_support = dcn_bw_supported_in_v_blank;
3611
+
} else {
3612
+
v->dram_clock_change_support = dcn_bw_not_supported;
3613
+
}
3614
+
/*maximum bandwidth used*/
3615
+
3616
+
v->wr_bandwidth = 0.0;
3617
+
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
3618
+
if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
3619
+
v->wr_bandwidth = v->wr_bandwidth
3620
+
+ v->scaler_rec_out_width[k]
3621
+
/ (v->htotal[k] / v->pixel_clock[k]) * 4.0;
3622
+
} else if (v->output[k] == dcn_bw_writeback) {
3623
+
v->wr_bandwidth = v->wr_bandwidth
3624
+
+ v->scaler_rec_out_width[k]
3625
+
/ (v->htotal[k] / v->pixel_clock[k]) * 1.5;
3626
+
}
3627
+
}
3628
+
v->max_used_bw = v->max_rd_bandwidth + v->wr_bandwidth;
3629
+
}
+37
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h
+37
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h
···
1
+
/*
2
+
* Copyright 2017 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: AMD
23
+
*
24
+
*/
25
+
26
+
#ifndef _DCN_CALC_AUTO_H_
27
+
#define _DCN_CALC_AUTO_H_
28
+
29
+
#include "dcn_calcs.h"
30
+
31
+
void scaler_settings_calculation(struct dcn_bw_internal_vars *v);
32
+
void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v);
33
+
void display_pipe_configuration(struct dcn_bw_internal_vars *v);
34
+
void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(
35
+
struct dcn_bw_internal_vars *v);
36
+
37
+
#endif /* _DCN_CALC_AUTO_H_ */
+104
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
+104
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
···
1
+
/*
2
+
* Copyright 2017 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: AMD
23
+
*
24
+
*/
25
+
26
+
#include "dcn_calc_math.h"
27
+
28
+
float dcn_bw_mod(const float arg1, const float arg2)
29
+
{
30
+
return arg1 - arg1 * ((int) (arg1 / arg2));
31
+
}
32
+
33
+
float dcn_bw_min2(const float arg1, const float arg2)
34
+
{
35
+
return arg1 < arg2 ? arg1 : arg2;
36
+
}
37
+
38
+
unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
39
+
{
40
+
return arg1 > arg2 ? arg1 : arg2;
41
+
}
42
+
float dcn_bw_max2(const float arg1, const float arg2)
43
+
{
44
+
return arg1 > arg2 ? arg1 : arg2;
45
+
}
46
+
47
+
float dcn_bw_floor2(const float arg, const float significance)
48
+
{
49
+
if (significance == 0)
50
+
return 0;
51
+
return ((int) (arg / significance)) * significance;
52
+
}
53
+
54
+
float dcn_bw_ceil2(const float arg, const float significance)
55
+
{
56
+
float flr = dcn_bw_floor2(arg, significance);
57
+
if (significance == 0)
58
+
return 0;
59
+
return flr + 0.00001 >= arg ? arg : flr + significance;
60
+
}
61
+
62
+
float dcn_bw_max3(float v1, float v2, float v3)
63
+
{
64
+
return v3 > dcn_bw_max2(v1, v2) ? v3 : dcn_bw_max2(v1, v2);
65
+
}
66
+
67
+
float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5)
68
+
{
69
+
return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v5);
70
+
}
71
+
72
+
float dcn_bw_pow(float a, float exp)
73
+
{
74
+
float temp;
75
+
/*ASSERT(exp == (int)exp);*/
76
+
if ((int)exp == 0)
77
+
return 1;
78
+
temp = dcn_bw_pow(a, (int)(exp / 2));
79
+
if (((int)exp % 2) == 0) {
80
+
return temp * temp;
81
+
} else {
82
+
if ((int)exp > 0)
83
+
return a * temp * temp;
84
+
else
85
+
return (temp * temp) / a;
86
+
}
87
+
}
88
+
89
+
float dcn_bw_log(float a, float b)
90
+
{
91
+
int * const exp_ptr = (int *)(&a);
92
+
int x = *exp_ptr;
93
+
const int log_2 = ((x >> 23) & 255) - 128;
94
+
x &= ~(255 << 23);
95
+
x += 127 << 23;
96
+
*exp_ptr = x;
97
+
98
+
a = ((-1.0f / 3) * a + 2) * a - 2.0f / 3;
99
+
100
+
if (b > 2.00001 || b < 1.99999)
101
+
return (a + log_2) / dcn_bw_log(b, 2);
102
+
else
103
+
return (a + log_2);
104
+
}
+40
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
+40
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
···
1
+
/*
2
+
* Copyright 2017 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: AMD
23
+
*
24
+
*/
25
+
26
+
#ifndef _DCN_CALC_MATH_H_
27
+
#define _DCN_CALC_MATH_H_
28
+
29
+
float dcn_bw_mod(const float arg1, const float arg2);
30
+
float dcn_bw_min2(const float arg1, const float arg2);
31
+
unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2);
32
+
float dcn_bw_max2(const float arg1, const float arg2);
33
+
float dcn_bw_floor2(const float arg, const float significance);
34
+
float dcn_bw_ceil2(const float arg, const float significance);
35
+
float dcn_bw_max3(float v1, float v2, float v3);
36
+
float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5);
37
+
float dcn_bw_pow(float a, float exp);
38
+
float dcn_bw_log(float a, float b);
39
+
40
+
#endif /* _DCN_CALC_MATH_H_ */
+1366
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+1366
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
···
1
+
/*
2
+
* Copyright 2017 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: AMD
23
+
*
24
+
*/
25
+
26
+
#include "dm_services.h"
27
+
#include "dcn_calcs.h"
28
+
#include "dcn_calc_auto.h"
29
+
#include "dc.h"
30
+
#include "core_dc.h"
31
+
#include "dal_asic_id.h"
32
+
33
+
#include "resource.h"
34
+
#include "dcn10/dcn10_resource.h"
35
+
#include "dcn_calc_math.h"
36
+
37
+
/* Defaults from spreadsheet rev#247 */
38
+
const struct dcn_soc_bounding_box dcn10_soc_defaults = {
39
+
.sr_exit_time = 17, /*us*/ /*update based on HW Request for 118773*/
40
+
.sr_enter_plus_exit_time = 19, /*us*/
41
+
.urgent_latency = 4, /*us*/
42
+
.write_back_latency = 12, /*us*/
43
+
.percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
44
+
.max_request_size = 256, /*bytes*/
45
+
.dcfclkv_max0p9 = 600, /*MHz*/
46
+
.dcfclkv_nom0p8 = 600, /*MHz*/
47
+
.dcfclkv_mid0p72 = 300, /*MHz*/
48
+
.dcfclkv_min0p65 = 300, /*MHz*/
49
+
.max_dispclk_vmax0p9 = 1086, /*MHz*/
50
+
.max_dispclk_vnom0p8 = 661, /*MHz*/
51
+
.max_dispclk_vmid0p72 = 608, /*MHz*/
52
+
.max_dispclk_vmin0p65 = 608, /*MHz*/
53
+
.max_dppclk_vmax0p9 = 661, /*MHz*/
54
+
.max_dppclk_vnom0p8 = 661, /*MHz*/
55
+
.max_dppclk_vmid0p72 = 435, /*MHz*/
56
+
.max_dppclk_vmin0p65 = 435, /*MHz*/
57
+
.socclk = 208, /*MHz*/
58
+
.fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
59
+
.fabric_and_dram_bandwidth_vnom0p8 = 34.1f, /*GB/s*/
60
+
.fabric_and_dram_bandwidth_vmid0p72 = 29.8f, /*GB/s*/
61
+
.fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
62
+
.phyclkv_max0p9 = 810, /*MHz*/
63
+
.phyclkv_nom0p8 = 810, /*MHz*/
64
+
.phyclkv_mid0p72 = 540, /*MHz*/
65
+
.phyclkv_min0p65 = 540, /*MHz*/
66
+
.downspreading = 0.5f, /*%*/
67
+
.round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
68
+
.urgent_out_of_order_return_per_channel = 256, /*bytes*/
69
+
.number_of_channels = 2,
70
+
.vmm_page_size = 4096, /*bytes*/
71
+
.dram_clock_change_latency = 17, /*us*/
72
+
.return_bus_width = 64, /*bytes*/
73
+
};
74
+
75
+
const struct dcn_ip_params dcn10_ip_defaults = {
76
+
.rob_buffer_size_in_kbyte = 64,
77
+
.det_buffer_size_in_kbyte = 164,
78
+
.dpp_output_buffer_pixels = 2560,
79
+
.opp_output_buffer_lines = 1,
80
+
.pixel_chunk_size_in_kbyte = 8,
81
+
.pte_enable = dcn_bw_yes,
82
+
.pte_chunk_size = 2, /*kbytes*/
83
+
.meta_chunk_size = 2, /*kbytes*/
84
+
.writeback_chunk_size = 2, /*kbytes*/
85
+
.odm_capability = dcn_bw_no,
86
+
.dsc_capability = dcn_bw_no,
87
+
.line_buffer_size = 589824, /*bit*/
88
+
.max_line_buffer_lines = 12,
89
+
.is_line_buffer_bpp_fixed = dcn_bw_no,
90
+
.line_buffer_fixed_bpp = dcn_bw_na,
91
+
.writeback_luma_buffer_size = 12, /*kbytes*/
92
+
.writeback_chroma_buffer_size = 8, /*kbytes*/
93
+
.max_num_dpp = 4,
94
+
.max_num_writeback = 2,
95
+
.max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
96
+
.max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
97
+
.max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
98
+
.max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
99
+
.max_hscl_ratio = 4,
100
+
.max_vscl_ratio = 4,
101
+
.max_hscl_taps = 8,
102
+
.max_vscl_taps = 8,
103
+
.pte_buffer_size_in_requests = 42,
104
+
.dispclk_ramping_margin = 1, /*%*/
105
+
.under_scan_factor = 1.11f,
106
+
.max_inter_dcn_tile_repeaters = 8,
107
+
.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no,
108
+
.bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no,
109
+
.dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
110
+
};
111
+
112
+
static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
113
+
{
114
+
switch (sw_mode) {
115
+
case DC_SW_LINEAR:
116
+
return dcn_bw_sw_linear;
117
+
case DC_SW_4KB_S:
118
+
return dcn_bw_sw_4_kb_s;
119
+
case DC_SW_4KB_D:
120
+
return dcn_bw_sw_4_kb_d;
121
+
case DC_SW_64KB_S:
122
+
return dcn_bw_sw_64_kb_s;
123
+
case DC_SW_64KB_D:
124
+
return dcn_bw_sw_64_kb_d;
125
+
case DC_SW_VAR_S:
126
+
return dcn_bw_sw_var_s;
127
+
case DC_SW_VAR_D:
128
+
return dcn_bw_sw_var_d;
129
+
case DC_SW_64KB_S_T:
130
+
return dcn_bw_sw_64_kb_s_t;
131
+
case DC_SW_64KB_D_T:
132
+
return dcn_bw_sw_64_kb_d_t;
133
+
case DC_SW_4KB_S_X:
134
+
return dcn_bw_sw_4_kb_s_x;
135
+
case DC_SW_4KB_D_X:
136
+
return dcn_bw_sw_4_kb_d_x;
137
+
case DC_SW_64KB_S_X:
138
+
return dcn_bw_sw_64_kb_s_x;
139
+
case DC_SW_64KB_D_X:
140
+
return dcn_bw_sw_64_kb_d_x;
141
+
case DC_SW_VAR_S_X:
142
+
return dcn_bw_sw_var_s_x;
143
+
case DC_SW_VAR_D_X:
144
+
return dcn_bw_sw_var_d_x;
145
+
case DC_SW_256B_S:
146
+
case DC_SW_256_D:
147
+
case DC_SW_256_R:
148
+
case DC_SW_4KB_R:
149
+
case DC_SW_64KB_R:
150
+
case DC_SW_VAR_R:
151
+
case DC_SW_4KB_R_X:
152
+
case DC_SW_64KB_R_X:
153
+
case DC_SW_VAR_R_X:
154
+
default:
155
+
BREAK_TO_DEBUGGER(); /*not in formula*/
156
+
return dcn_bw_sw_4_kb_s;
157
+
}
158
+
}
159
+
160
+
static int tl_lb_bpp_to_int(enum lb_pixel_depth depth)
161
+
{
162
+
switch (depth) {
163
+
case LB_PIXEL_DEPTH_18BPP:
164
+
return 18;
165
+
case LB_PIXEL_DEPTH_24BPP:
166
+
return 24;
167
+
case LB_PIXEL_DEPTH_30BPP:
168
+
return 30;
169
+
case LB_PIXEL_DEPTH_36BPP:
170
+
return 36;
171
+
default:
172
+
return 30;
173
+
}
174
+
}
175
+
176
+
static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format)
177
+
{
178
+
switch (format) {
179
+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
180
+
case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
181
+
return dcn_bw_rgb_sub_16;
182
+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
183
+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
184
+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
185
+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
186
+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
187
+
return dcn_bw_rgb_sub_32;
188
+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
189
+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
190
+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
191
+
return dcn_bw_rgb_sub_64;
192
+
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
193
+
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
194
+
return dcn_bw_yuv420_sub_8;
195
+
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
196
+
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
197
+
return dcn_bw_yuv420_sub_10;
198
+
default:
199
+
return dcn_bw_rgb_sub_32;
200
+
}
201
+
}
202
+
203
+
static void pipe_ctx_to_e2e_pipe_params (
204
+
const struct pipe_ctx *pipe,
205
+
struct _vcs_dpi_display_pipe_params_st *input)
206
+
{
207
+
input->src.is_hsplit = false;
208
+
if (pipe->top_pipe != NULL && pipe->top_pipe->surface == pipe->surface)
209
+
input->src.is_hsplit = true;
210
+
else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->surface == pipe->surface)
211
+
input->src.is_hsplit = true;
212
+
213
+
input->src.dcc = pipe->surface->public.dcc.enable;
214
+
input->src.dcc_rate = 1;
215
+
input->src.meta_pitch = pipe->surface->public.dcc.grph.meta_pitch;
216
+
input->src.source_scan = dm_horz;
217
+
input->src.sw_mode = pipe->surface->public.tiling_info.gfx9.swizzle;
218
+
219
+
input->src.viewport_width = pipe->scl_data.viewport.width;
220
+
input->src.viewport_height = pipe->scl_data.viewport.height;
221
+
input->src.data_pitch = pipe->scl_data.viewport.width;
222
+
input->src.data_pitch_c = pipe->scl_data.viewport.width;
223
+
input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */
224
+
input->src.cur0_bpp = 32;
225
+
226
+
switch (pipe->surface->public.tiling_info.gfx9.swizzle) {
227
+
/* for 4/8/16 high tiles */
228
+
case DC_SW_LINEAR:
229
+
input->src.is_display_sw = 1;
230
+
input->src.macro_tile_size = dm_4k_tile;
231
+
break;
232
+
case DC_SW_4KB_S:
233
+
case DC_SW_4KB_S_X:
234
+
input->src.is_display_sw = 0;
235
+
input->src.macro_tile_size = dm_4k_tile;
236
+
break;
237
+
case DC_SW_64KB_S:
238
+
case DC_SW_64KB_S_X:
239
+
input->src.is_display_sw = 0;
240
+
input->src.macro_tile_size = dm_64k_tile;
241
+
break;
242
+
case DC_SW_VAR_S:
243
+
case DC_SW_VAR_S_X:
244
+
input->src.is_display_sw = 0;
245
+
input->src.macro_tile_size = dm_256k_tile;
246
+
break;
247
+
248
+
/* For 64bpp 2 high tiles */
249
+
case DC_SW_4KB_D:
250
+
case DC_SW_4KB_D_X:
251
+
input->src.is_display_sw = 1;
252
+
input->src.macro_tile_size = dm_4k_tile;
253
+
break;
254
+
case DC_SW_64KB_D:
255
+
case DC_SW_64KB_D_X:
256
+
input->src.is_display_sw = 1;
257
+
input->src.macro_tile_size = dm_64k_tile;
258
+
break;
259
+
case DC_SW_VAR_D:
260
+
case DC_SW_VAR_D_X:
261
+
input->src.is_display_sw = 1;
262
+
input->src.macro_tile_size = dm_256k_tile;
263
+
break;
264
+
265
+
/* Unsupported swizzle modes for dcn */
266
+
case DC_SW_256B_S:
267
+
default:
268
+
ASSERT(0); /* Not supported */
269
+
break;
270
+
}
271
+
272
+
switch (pipe->surface->public.rotation) {
273
+
case ROTATION_ANGLE_0:
274
+
case ROTATION_ANGLE_180:
275
+
input->src.source_scan = dm_horz;
276
+
break;
277
+
case ROTATION_ANGLE_90:
278
+
case ROTATION_ANGLE_270:
279
+
input->src.source_scan = dm_vert;
280
+
break;
281
+
default:
282
+
ASSERT(0); /* Not supported */
283
+
break;
284
+
}
285
+
286
+
/* TODO: Fix pixel format mappings */
287
+
switch (pipe->surface->public.format) {
288
+
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
289
+
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
290
+
input->src.source_format = dm_420_8;
291
+
input->src.viewport_width_c = input->src.viewport_width / 2;
292
+
input->src.viewport_height_c = input->src.viewport_height / 2;
293
+
break;
294
+
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
295
+
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
296
+
input->src.source_format = dm_420_10;
297
+
input->src.viewport_width_c = input->src.viewport_width / 2;
298
+
input->src.viewport_height_c = input->src.viewport_height / 2;
299
+
break;
300
+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
301
+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
302
+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
303
+
input->src.source_format = dm_444_64;
304
+
input->src.viewport_width_c = input->src.viewport_width;
305
+
input->src.viewport_height_c = input->src.viewport_height;
306
+
break;
307
+
default:
308
+
input->src.source_format = dm_444_32;
309
+
input->src.viewport_width_c = input->src.viewport_width;
310
+
input->src.viewport_height_c = input->src.viewport_height;
311
+
break;
312
+
}
313
+
314
+
input->scale_taps.htaps = pipe->scl_data.taps.h_taps;
315
+
input->scale_ratio_depth.hscl_ratio = pipe->scl_data.ratios.horz.value/4294967296.0;
316
+
input->scale_ratio_depth.vscl_ratio = pipe->scl_data.ratios.vert.value/4294967296.0;
317
+
input->scale_ratio_depth.vinit = pipe->scl_data.inits.v.value/4294967296.0;
318
+
if (input->scale_ratio_depth.vinit < 1.0)
319
+
input->scale_ratio_depth.vinit = 1;
320
+
input->scale_taps.vtaps = pipe->scl_data.taps.v_taps;
321
+
input->scale_taps.vtaps_c = pipe->scl_data.taps.v_taps_c;
322
+
input->scale_taps.htaps_c = pipe->scl_data.taps.h_taps_c;
323
+
input->scale_ratio_depth.hscl_ratio_c = pipe->scl_data.ratios.horz_c.value/4294967296.0;
324
+
input->scale_ratio_depth.vscl_ratio_c = pipe->scl_data.ratios.vert_c.value/4294967296.0;
325
+
input->scale_ratio_depth.vinit_c = pipe->scl_data.inits.v_c.value/4294967296.0;
326
+
if (input->scale_ratio_depth.vinit_c < 1.0)
327
+
input->scale_ratio_depth.vinit_c = 1;
328
+
switch (pipe->scl_data.lb_params.depth) {
329
+
case LB_PIXEL_DEPTH_30BPP:
330
+
input->scale_ratio_depth.lb_depth = 30; break;
331
+
case LB_PIXEL_DEPTH_36BPP:
332
+
input->scale_ratio_depth.lb_depth = 36; break;
333
+
default:
334
+
input->scale_ratio_depth.lb_depth = 24; break;
335
+
}
336
+
337
+
338
+
input->dest.vactive = pipe->stream->public.timing.v_addressable;
339
+
340
+
input->dest.recout_width = pipe->scl_data.recout.width;
341
+
input->dest.recout_height = pipe->scl_data.recout.height;
342
+
343
+
input->dest.full_recout_width = pipe->scl_data.recout.width;
344
+
input->dest.full_recout_height = pipe->scl_data.recout.height;
345
+
346
+
input->dest.htotal = pipe->stream->public.timing.h_total;
347
+
input->dest.hblank_start = input->dest.htotal - pipe->stream->public.timing.h_front_porch;
348
+
input->dest.hblank_end = input->dest.hblank_start
349
+
- pipe->stream->public.timing.h_addressable
350
+
- pipe->stream->public.timing.h_border_left
351
+
- pipe->stream->public.timing.h_border_right;
352
+
353
+
input->dest.vtotal = pipe->stream->public.timing.v_total;
354
+
input->dest.vblank_start = input->dest.vtotal - pipe->stream->public.timing.v_front_porch;
355
+
input->dest.vblank_end = input->dest.vblank_start
356
+
- pipe->stream->public.timing.v_addressable
357
+
- pipe->stream->public.timing.v_border_bottom
358
+
- pipe->stream->public.timing.v_border_top;
359
+
360
+
input->dest.vsync_plus_back_porch = pipe->stream->public.timing.v_total
361
+
- pipe->stream->public.timing.v_addressable
362
+
- pipe->stream->public.timing.v_front_porch;
363
+
input->dest.pixel_rate_mhz = pipe->stream->public.timing.pix_clk_khz/1000.0;
364
+
input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
365
+
input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
366
+
input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
367
+
input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
368
+
369
+
}
370
+
371
+
static void dcn_bw_calc_rq_dlg_ttu(
372
+
const struct core_dc *dc,
373
+
const struct dcn_bw_internal_vars *v,
374
+
struct pipe_ctx *pipe)
375
+
{
376
+
struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
377
+
struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
378
+
struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
379
+
struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
380
+
struct _vcs_dpi_display_rq_params_st rq_param = {0};
381
+
struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
382
+
struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
383
+
float total_active_bw = 0;
384
+
float total_prefetch_bw = 0;
385
+
int total_flip_bytes = 0;
386
+
int i;
387
+
388
+
for (i = 0; i < number_of_planes; i++) {
389
+
total_active_bw += v->read_bandwidth[i];
390
+
total_prefetch_bw += v->prefetch_bandwidth[i];
391
+
total_flip_bytes += v->total_immediate_flip_bytes[i];
392
+
}
393
+
dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
394
+
if (dlg_sys_param.total_flip_bw < 0.0)
395
+
dlg_sys_param.total_flip_bw = 0;
396
+
397
+
dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
398
+
dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
399
+
dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
400
+
dlg_sys_param.t_extra_us = v->urgent_extra_latency;
401
+
dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
402
+
dlg_sys_param.total_flip_bytes = total_flip_bytes;
403
+
404
+
pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);
405
+
input.clks_cfg.dcfclk_mhz = v->dcfclk;
406
+
input.clks_cfg.dispclk_mhz = v->dispclk;
407
+
input.clks_cfg.dppclk_mhz = v->dppclk;
408
+
input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz/1000;
409
+
input.clks_cfg.socclk_mhz = v->socclk;
410
+
input.clks_cfg.voltage = v->voltage_level;
411
+
// dc->dml.logger = pool->base.logger;
412
+
413
+
/*todo: soc->sr_enter_plus_exit_time??*/
414
+
dlg_sys_param.t_srx_delay_us = dc->dcn_ip.dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
415
+
416
+
dml_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
417
+
extract_rq_regs(dml, rq_regs, rq_param);
418
+
dml_rq_dlg_get_dlg_params(
419
+
dml,
420
+
dlg_regs,
421
+
ttu_regs,
422
+
rq_param.dlg,
423
+
dlg_sys_param,
424
+
input,
425
+
true,
426
+
true,
427
+
v->pte_enable == dcn_bw_yes,
428
+
pipe->surface->public.flip_immediate);
429
+
}
430
+
431
+
static void dcn_dml_wm_override(
432
+
const struct dcn_bw_internal_vars *v,
433
+
struct display_mode_lib *dml,
434
+
struct validate_context *context,
435
+
const struct resource_pool *pool)
436
+
{
437
+
int i, in_idx, active_count;
438
+
439
+
struct _vcs_dpi_display_e2e_pipe_params_st *input = dm_alloc(pool->pipe_count *
440
+
sizeof(struct _vcs_dpi_display_e2e_pipe_params_st));
441
+
struct wm {
442
+
double urgent;
443
+
struct _vcs_dpi_cstate_pstate_watermarks_st cpstate;
444
+
double pte_meta_urgent;
445
+
} a;
446
+
447
+
448
+
for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
449
+
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
450
+
451
+
if (!pipe->stream || !pipe->surface)
452
+
continue;
453
+
454
+
input[in_idx].clks_cfg.dcfclk_mhz = v->dcfclk;
455
+
input[in_idx].clks_cfg.dispclk_mhz = v->dispclk;
456
+
input[in_idx].clks_cfg.dppclk_mhz = v->dppclk;
457
+
input[in_idx].clks_cfg.refclk_mhz = pool->ref_clock_inKhz / 1000;
458
+
input[in_idx].clks_cfg.socclk_mhz = v->socclk;
459
+
input[in_idx].clks_cfg.voltage = v->voltage_level;
460
+
pipe_ctx_to_e2e_pipe_params(pipe, &input[in_idx].pipe);
461
+
dml_rq_dlg_get_rq_reg(
462
+
dml,
463
+
&pipe->rq_regs,
464
+
input[in_idx].pipe.src);
465
+
in_idx++;
466
+
}
467
+
active_count = in_idx;
468
+
469
+
a.urgent = dml_wm_urgent_e2e(dml, input, active_count);
470
+
a.cpstate = dml_wm_cstate_pstate_e2e(dml, input, active_count);
471
+
a.pte_meta_urgent = dml_wm_pte_meta_urgent(dml, a.urgent);
472
+
473
+
context->watermarks.a.cstate_pstate.cstate_exit_ns =
474
+
a.cpstate.cstate_exit_us * 1000;
475
+
context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
476
+
a.cpstate.cstate_enter_plus_exit_us * 1000;
477
+
context->watermarks.a.cstate_pstate.pstate_change_ns =
478
+
a.cpstate.pstate_change_us * 1000;
479
+
context->watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000;
480
+
context->watermarks.a.urgent_ns = a.urgent * 1000;
481
+
context->watermarks.b = context->watermarks.a;
482
+
context->watermarks.c = context->watermarks.a;
483
+
context->watermarks.d = context->watermarks.a;
484
+
485
+
486
+
for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
487
+
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
488
+
489
+
if (!pipe->stream || !pipe->surface)
490
+
continue;
491
+
492
+
dml_rq_dlg_get_dlg_reg(dml,
493
+
&pipe->dlg_regs,
494
+
&pipe->ttu_regs,
495
+
input, active_count,
496
+
in_idx,
497
+
true,
498
+
true,
499
+
v->pte_enable == dcn_bw_yes,
500
+
pipe->surface->public.flip_immediate);
501
+
in_idx++;
502
+
}
503
+
dm_free(input);
504
+
}
505
+
506
+
static void split_stream_across_pipes(
507
+
struct resource_context *res_ctx,
508
+
const struct resource_pool *pool,
509
+
struct pipe_ctx *primary_pipe,
510
+
struct pipe_ctx *secondary_pipe)
511
+
{
512
+
if (!primary_pipe->surface)
513
+
return;
514
+
515
+
secondary_pipe->stream = primary_pipe->stream;
516
+
secondary_pipe->tg = primary_pipe->tg;
517
+
518
+
secondary_pipe->mi = pool->mis[secondary_pipe->pipe_idx];
519
+
secondary_pipe->ipp = pool->ipps[secondary_pipe->pipe_idx];
520
+
secondary_pipe->xfm = pool->transforms[secondary_pipe->pipe_idx];
521
+
secondary_pipe->opp = pool->opps[secondary_pipe->pipe_idx];
522
+
if (primary_pipe->bottom_pipe) {
523
+
secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
524
+
secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
525
+
}
526
+
primary_pipe->bottom_pipe = secondary_pipe;
527
+
secondary_pipe->top_pipe = primary_pipe;
528
+
secondary_pipe->surface = primary_pipe->surface;
529
+
secondary_pipe->pipe_dlg_param = primary_pipe->pipe_dlg_param;
530
+
531
+
resource_build_scaling_params(primary_pipe);
532
+
resource_build_scaling_params(secondary_pipe);
533
+
}
534
+
535
+
static void calc_wm_sets_and_perf_params(
536
+
struct validate_context *context,
537
+
struct dcn_bw_internal_vars *v)
538
+
{
539
+
/* Calculate set A last to keep internal var state consistent for required config */
540
+
if (v->voltage_level < 2) {
541
+
v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
542
+
v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
543
+
v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
544
+
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
545
+
546
+
context->watermarks.b.cstate_pstate.cstate_exit_ns =
547
+
v->stutter_exit_watermark * 1000;
548
+
context->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
549
+
v->stutter_enter_plus_exit_watermark * 1000;
550
+
context->watermarks.b.cstate_pstate.pstate_change_ns =
551
+
v->dram_clock_change_watermark * 1000;
552
+
context->watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
553
+
context->watermarks.b.urgent_ns = v->urgent_watermark * 1000;
554
+
555
+
v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
556
+
v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
557
+
v->dcfclk = v->dcfclkv_nom0p8;
558
+
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
559
+
560
+
context->watermarks.c.cstate_pstate.cstate_exit_ns =
561
+
v->stutter_exit_watermark * 1000;
562
+
context->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
563
+
v->stutter_enter_plus_exit_watermark * 1000;
564
+
context->watermarks.c.cstate_pstate.pstate_change_ns =
565
+
v->dram_clock_change_watermark * 1000;
566
+
context->watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
567
+
context->watermarks.c.urgent_ns = v->urgent_watermark * 1000;
568
+
}
569
+
570
+
if (v->voltage_level < 3) {
571
+
v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
572
+
v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
573
+
v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
574
+
v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
575
+
v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
576
+
v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
577
+
v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
578
+
v->dcfclk = v->dcfclkv_max0p9;
579
+
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
580
+
581
+
context->watermarks.d.cstate_pstate.cstate_exit_ns =
582
+
v->stutter_exit_watermark * 1000;
583
+
context->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
584
+
v->stutter_enter_plus_exit_watermark * 1000;
585
+
context->watermarks.d.cstate_pstate.pstate_change_ns =
586
+
v->dram_clock_change_watermark * 1000;
587
+
context->watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
588
+
context->watermarks.d.urgent_ns = v->urgent_watermark * 1000;
589
+
}
590
+
591
+
v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
592
+
v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
593
+
v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
594
+
v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
595
+
v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
596
+
v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
597
+
v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
598
+
v->dcfclk = v->dcfclk_per_state[v->voltage_level];
599
+
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
600
+
601
+
context->watermarks.a.cstate_pstate.cstate_exit_ns =
602
+
v->stutter_exit_watermark * 1000;
603
+
context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
604
+
v->stutter_enter_plus_exit_watermark * 1000;
605
+
context->watermarks.a.cstate_pstate.pstate_change_ns =
606
+
v->dram_clock_change_watermark * 1000;
607
+
context->watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
608
+
context->watermarks.a.urgent_ns = v->urgent_watermark * 1000;
609
+
if (v->voltage_level >= 2) {
610
+
context->watermarks.b = context->watermarks.a;
611
+
context->watermarks.c = context->watermarks.a;
612
+
}
613
+
if (v->voltage_level >= 3)
614
+
context->watermarks.d = context->watermarks.a;
615
+
}
616
+
617
+
static void dcn_bw_apply_registry_override(struct core_dc *dc)
618
+
{
619
+
kernel_fpu_begin();
620
+
if (dc->public.debug.sr_exit_time_ns)
621
+
dc->dcn_soc.sr_exit_time = dc->public.debug.sr_exit_time_ns / 1000.0;
622
+
if (dc->public.debug.sr_enter_plus_exit_time_ns)
623
+
dc->dcn_soc.sr_enter_plus_exit_time =
624
+
dc->public.debug.sr_enter_plus_exit_time_ns / 1000.0;
625
+
if (dc->public.debug.urgent_latency_ns)
626
+
dc->dcn_soc.urgent_latency = dc->public.debug.urgent_latency_ns / 1000.0;
627
+
if (dc->public.debug.percent_of_ideal_drambw)
628
+
dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency =
629
+
dc->public.debug.percent_of_ideal_drambw;
630
+
if (dc->public.debug.dram_clock_change_latency_ns)
631
+
dc->dcn_soc.dram_clock_change_latency =
632
+
dc->public.debug.dram_clock_change_latency_ns / 1000.0;
633
+
kernel_fpu_end();
634
+
}
635
+
636
+
bool dcn_validate_bandwidth(
637
+
const struct core_dc *dc,
638
+
struct validate_context *context)
639
+
{
640
+
const struct resource_pool *pool = dc->res_pool;
641
+
struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
642
+
int i, input_idx;
643
+
int vesa_sync_start, asic_blank_end, asic_blank_start;
644
+
645
+
dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public));
646
+
647
+
memset(v, 0, sizeof(*v));
648
+
kernel_fpu_begin();
649
+
v->sr_exit_time = dc->dcn_soc.sr_exit_time;
650
+
v->sr_enter_plus_exit_time = dc->dcn_soc.sr_enter_plus_exit_time;
651
+
v->urgent_latency = dc->dcn_soc.urgent_latency;
652
+
v->write_back_latency = dc->dcn_soc.write_back_latency;
653
+
v->percent_of_ideal_drambw_received_after_urg_latency =
654
+
dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency;
655
+
656
+
v->dcfclkv_min0p65 = dc->dcn_soc.dcfclkv_min0p65;
657
+
v->dcfclkv_mid0p72 = dc->dcn_soc.dcfclkv_mid0p72;
658
+
v->dcfclkv_nom0p8 = dc->dcn_soc.dcfclkv_nom0p8;
659
+
v->dcfclkv_max0p9 = dc->dcn_soc.dcfclkv_max0p9;
660
+
661
+
v->max_dispclk_vmin0p65 = dc->dcn_soc.max_dispclk_vmin0p65;
662
+
v->max_dispclk_vmid0p72 = dc->dcn_soc.max_dispclk_vmid0p72;
663
+
v->max_dispclk_vnom0p8 = dc->dcn_soc.max_dispclk_vnom0p8;
664
+
v->max_dispclk_vmax0p9 = dc->dcn_soc.max_dispclk_vmax0p9;
665
+
666
+
v->max_dppclk_vmin0p65 = dc->dcn_soc.max_dppclk_vmin0p65;
667
+
v->max_dppclk_vmid0p72 = dc->dcn_soc.max_dppclk_vmid0p72;
668
+
v->max_dppclk_vnom0p8 = dc->dcn_soc.max_dppclk_vnom0p8;
669
+
v->max_dppclk_vmax0p9 = dc->dcn_soc.max_dppclk_vmax0p9;
670
+
671
+
v->socclk = dc->dcn_soc.socclk;
672
+
673
+
v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65;
674
+
v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72;
675
+
v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8;
676
+
v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9;
677
+
678
+
v->phyclkv_min0p65 = dc->dcn_soc.phyclkv_min0p65;
679
+
v->phyclkv_mid0p72 = dc->dcn_soc.phyclkv_mid0p72;
680
+
v->phyclkv_nom0p8 = dc->dcn_soc.phyclkv_nom0p8;
681
+
v->phyclkv_max0p9 = dc->dcn_soc.phyclkv_max0p9;
682
+
683
+
v->downspreading = dc->dcn_soc.downspreading;
684
+
v->round_trip_ping_latency_cycles = dc->dcn_soc.round_trip_ping_latency_cycles;
685
+
v->urgent_out_of_order_return_per_channel = dc->dcn_soc.urgent_out_of_order_return_per_channel;
686
+
v->number_of_channels = dc->dcn_soc.number_of_channels;
687
+
v->vmm_page_size = dc->dcn_soc.vmm_page_size;
688
+
v->dram_clock_change_latency = dc->dcn_soc.dram_clock_change_latency;
689
+
v->return_bus_width = dc->dcn_soc.return_bus_width;
690
+
691
+
v->rob_buffer_size_in_kbyte = dc->dcn_ip.rob_buffer_size_in_kbyte;
692
+
v->det_buffer_size_in_kbyte = dc->dcn_ip.det_buffer_size_in_kbyte;
693
+
v->dpp_output_buffer_pixels = dc->dcn_ip.dpp_output_buffer_pixels;
694
+
v->opp_output_buffer_lines = dc->dcn_ip.opp_output_buffer_lines;
695
+
v->pixel_chunk_size_in_kbyte = dc->dcn_ip.pixel_chunk_size_in_kbyte;
696
+
v->pte_enable = dc->dcn_ip.pte_enable;
697
+
v->pte_chunk_size = dc->dcn_ip.pte_chunk_size;
698
+
v->meta_chunk_size = dc->dcn_ip.meta_chunk_size;
699
+
v->writeback_chunk_size = dc->dcn_ip.writeback_chunk_size;
700
+
v->odm_capability = dc->dcn_ip.odm_capability;
701
+
v->dsc_capability = dc->dcn_ip.dsc_capability;
702
+
v->line_buffer_size = dc->dcn_ip.line_buffer_size;
703
+
v->is_line_buffer_bpp_fixed = dc->dcn_ip.is_line_buffer_bpp_fixed;
704
+
v->line_buffer_fixed_bpp = dc->dcn_ip.line_buffer_fixed_bpp;
705
+
v->max_line_buffer_lines = dc->dcn_ip.max_line_buffer_lines;
706
+
v->writeback_luma_buffer_size = dc->dcn_ip.writeback_luma_buffer_size;
707
+
v->writeback_chroma_buffer_size = dc->dcn_ip.writeback_chroma_buffer_size;
708
+
v->max_num_dpp = dc->dcn_ip.max_num_dpp;
709
+
v->max_num_writeback = dc->dcn_ip.max_num_writeback;
710
+
v->max_dchub_topscl_throughput = dc->dcn_ip.max_dchub_topscl_throughput;
711
+
v->max_pscl_tolb_throughput = dc->dcn_ip.max_pscl_tolb_throughput;
712
+
v->max_lb_tovscl_throughput = dc->dcn_ip.max_lb_tovscl_throughput;
713
+
v->max_vscl_tohscl_throughput = dc->dcn_ip.max_vscl_tohscl_throughput;
714
+
v->max_hscl_ratio = dc->dcn_ip.max_hscl_ratio;
715
+
v->max_vscl_ratio = dc->dcn_ip.max_vscl_ratio;
716
+
v->max_hscl_taps = dc->dcn_ip.max_hscl_taps;
717
+
v->max_vscl_taps = dc->dcn_ip.max_vscl_taps;
718
+
v->under_scan_factor = dc->dcn_ip.under_scan_factor;
719
+
v->pte_buffer_size_in_requests = dc->dcn_ip.pte_buffer_size_in_requests;
720
+
v->dispclk_ramping_margin = dc->dcn_ip.dispclk_ramping_margin;
721
+
v->max_inter_dcn_tile_repeaters = dc->dcn_ip.max_inter_dcn_tile_repeaters;
722
+
v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
723
+
dc->dcn_ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
724
+
v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
725
+
dc->dcn_ip.bug_forcing_luma_and_chroma_request_to_same_size_fixed;
726
+
727
+
v->voltage[5] = dcn_bw_no_support;
728
+
v->voltage[4] = dcn_bw_v_max0p9;
729
+
v->voltage[3] = dcn_bw_v_max0p9;
730
+
v->voltage[2] = dcn_bw_v_nom0p8;
731
+
v->voltage[1] = dcn_bw_v_mid0p72;
732
+
v->voltage[0] = dcn_bw_v_min0p65;
733
+
v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
734
+
v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
735
+
v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
736
+
v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
737
+
v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
738
+
v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
739
+
v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
740
+
v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
741
+
v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
742
+
v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
743
+
v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
744
+
v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
745
+
v->max_dispclk[5] = v->max_dispclk_vmax0p9;
746
+
v->max_dispclk[4] = v->max_dispclk_vmax0p9;
747
+
v->max_dispclk[3] = v->max_dispclk_vmax0p9;
748
+
v->max_dispclk[2] = v->max_dispclk_vnom0p8;
749
+
v->max_dispclk[1] = v->max_dispclk_vmid0p72;
750
+
v->max_dispclk[0] = v->max_dispclk_vmin0p65;
751
+
v->max_dppclk[5] = v->max_dppclk_vmax0p9;
752
+
v->max_dppclk[4] = v->max_dppclk_vmax0p9;
753
+
v->max_dppclk[3] = v->max_dppclk_vmax0p9;
754
+
v->max_dppclk[2] = v->max_dppclk_vnom0p8;
755
+
v->max_dppclk[1] = v->max_dppclk_vmid0p72;
756
+
v->max_dppclk[0] = v->max_dppclk_vmin0p65;
757
+
v->phyclk_per_state[5] = v->phyclkv_max0p9;
758
+
v->phyclk_per_state[4] = v->phyclkv_max0p9;
759
+
v->phyclk_per_state[3] = v->phyclkv_max0p9;
760
+
v->phyclk_per_state[2] = v->phyclkv_nom0p8;
761
+
v->phyclk_per_state[1] = v->phyclkv_mid0p72;
762
+
v->phyclk_per_state[0] = v->phyclkv_min0p65;
763
+
764
+
if (dc->public.debug.use_max_voltage) {
765
+
v->max_dppclk[1] = v->max_dppclk_vnom0p8;
766
+
v->max_dppclk[0] = v->max_dppclk_vnom0p8;
767
+
}
768
+
769
+
if (v->voltage_override == dcn_bw_v_max0p9) {
770
+
v->voltage_override_level = number_of_states - 1;
771
+
} else if (v->voltage_override == dcn_bw_v_nom0p8) {
772
+
v->voltage_override_level = number_of_states - 2;
773
+
} else if (v->voltage_override == dcn_bw_v_mid0p72) {
774
+
v->voltage_override_level = number_of_states - 3;
775
+
} else {
776
+
v->voltage_override_level = 0;
777
+
}
778
+
v->synchronized_vblank = dcn_bw_no;
779
+
v->ta_pscalculation = dcn_bw_override;
780
+
v->allow_different_hratio_vratio = dcn_bw_yes;
781
+
782
+
783
+
for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
784
+
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
785
+
786
+
if (!pipe->stream)
787
+
continue;
788
+
/* skip all but first of split pipes */
789
+
if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface)
790
+
continue;
791
+
792
+
v->underscan_output[input_idx] = false; /* taken care of in recout already*/
793
+
v->interlace_output[input_idx] = false;
794
+
795
+
v->htotal[input_idx] = pipe->stream->public.timing.h_total;
796
+
v->vtotal[input_idx] = pipe->stream->public.timing.v_total;
797
+
v->v_sync_plus_back_porch[input_idx] = pipe->stream->public.timing.v_total
798
+
- pipe->stream->public.timing.v_addressable
799
+
- pipe->stream->public.timing.v_front_porch;
800
+
v->vactive[input_idx] = pipe->stream->public.timing.v_addressable;
801
+
v->pixel_clock[input_idx] = pipe->stream->public.timing.pix_clk_khz / 1000.0f;
802
+
803
+
804
+
if (!pipe->surface){
805
+
v->dcc_enable[input_idx] = dcn_bw_yes;
806
+
v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
807
+
v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
808
+
v->lb_bit_per_pixel[input_idx] = 30;
809
+
v->viewport_width[input_idx] = pipe->stream->public.timing.h_addressable;
810
+
v->viewport_height[input_idx] = pipe->stream->public.timing.v_addressable;
811
+
v->scaler_rec_out_width[input_idx] = pipe->stream->public.timing.h_addressable;
812
+
v->scaler_recout_height[input_idx] = pipe->stream->public.timing.v_addressable;
813
+
v->override_hta_ps[input_idx] = 1;
814
+
v->override_vta_ps[input_idx] = 1;
815
+
v->override_hta_pschroma[input_idx] = 1;
816
+
v->override_vta_pschroma[input_idx] = 1;
817
+
v->source_scan[input_idx] = dcn_bw_hor;
818
+
819
+
} else {
820
+
v->viewport_height[input_idx] = pipe->scl_data.viewport.height;
821
+
v->viewport_width[input_idx] = pipe->scl_data.viewport.width;
822
+
v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width;
823
+
v->scaler_recout_height[input_idx] = pipe->scl_data.recout.height;
824
+
if (pipe->bottom_pipe && pipe->bottom_pipe->surface == pipe->surface) {
825
+
if (pipe->surface->public.rotation % 2 == 0) {
826
+
int viewport_end = pipe->scl_data.viewport.width
827
+
+ pipe->scl_data.viewport.x;
828
+
int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.width
829
+
+ pipe->bottom_pipe->scl_data.viewport.x;
830
+
831
+
if (viewport_end > viewport_b_end)
832
+
v->viewport_width[input_idx] = viewport_end
833
+
- pipe->bottom_pipe->scl_data.viewport.x;
834
+
else
835
+
v->viewport_width[input_idx] = viewport_b_end
836
+
- pipe->scl_data.viewport.x;
837
+
} else {
838
+
int viewport_end = pipe->scl_data.viewport.height
839
+
+ pipe->scl_data.viewport.y;
840
+
int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.height
841
+
+ pipe->bottom_pipe->scl_data.viewport.y;
842
+
843
+
if (viewport_end > viewport_b_end)
844
+
v->viewport_height[input_idx] = viewport_end
845
+
- pipe->bottom_pipe->scl_data.viewport.y;
846
+
else
847
+
v->viewport_height[input_idx] = viewport_b_end
848
+
- pipe->scl_data.viewport.y;
849
+
}
850
+
v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width
851
+
+ pipe->bottom_pipe->scl_data.recout.width;
852
+
}
853
+
854
+
v->dcc_enable[input_idx] = pipe->surface->public.dcc.enable ? dcn_bw_yes : dcn_bw_no;
855
+
v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
856
+
pipe->surface->public.format);
857
+
v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
858
+
pipe->surface->public.tiling_info.gfx9.swizzle);
859
+
v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->scl_data.lb_params.depth);
860
+
v->override_hta_ps[input_idx] = pipe->scl_data.taps.h_taps;
861
+
v->override_vta_ps[input_idx] = pipe->scl_data.taps.v_taps;
862
+
v->override_hta_pschroma[input_idx] = pipe->scl_data.taps.h_taps_c;
863
+
v->override_vta_pschroma[input_idx] = pipe->scl_data.taps.v_taps_c;
864
+
v->source_scan[input_idx] = (pipe->surface->public.rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
865
+
}
866
+
if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
867
+
v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
868
+
v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
869
+
v->output_format[input_idx] = dcn_bw_444;
870
+
v->output[input_idx] = dcn_bw_dp;
871
+
872
+
input_idx++;
873
+
}
874
+
v->number_of_active_planes = input_idx;
875
+
876
+
scaler_settings_calculation(v);
877
+
mode_support_and_system_configuration(v);
878
+
879
+
if (v->voltage_level != 5) {
880
+
float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
881
+
if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
882
+
bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
883
+
else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
884
+
bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
885
+
else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
886
+
bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
887
+
else
888
+
bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
889
+
890
+
display_pipe_configuration(v);
891
+
calc_wm_sets_and_perf_params(context, v);
892
+
context->fclk_khz = (int)(bw_consumed * 1000000 /
893
+
(ddr4_dram_factor_single_Channel * v->number_of_channels));
894
+
context->dram_ccm_us = (int)(v->dram_clock_change_margin);
895
+
context->min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);
896
+
context->dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
897
+
context->dcfclk_khz = (int)(v->dcfclk * 1000);
898
+
context->dispclk_khz = (int)(v->dispclk * 1000);
899
+
if (dc->public.debug.max_disp_clk == true)
900
+
context->dispclk_khz = (int)(dc->dcn_soc.max_dispclk_vmax0p9 * 1000);
901
+
context->dppclk_khz = (int)(v->dppclk * 1000);
902
+
context->dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;
903
+
904
+
for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
905
+
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
906
+
907
+
/* skip inactive pipe */
908
+
if (!pipe->stream)
909
+
continue;
910
+
/* skip all but first of split pipes */
911
+
if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface)
912
+
continue;
913
+
914
+
pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
915
+
pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx];
916
+
pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
917
+
pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
918
+
919
+
pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total;
920
+
pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total;
921
+
vesa_sync_start = pipe->stream->public.timing.v_addressable +
922
+
pipe->stream->public.timing.v_border_bottom +
923
+
pipe->stream->public.timing.v_front_porch;
924
+
925
+
asic_blank_end = (pipe->stream->public.timing.v_total -
926
+
vesa_sync_start -
927
+
pipe->stream->public.timing.v_border_top)
928
+
* (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0);
929
+
930
+
asic_blank_start = asic_blank_end +
931
+
(pipe->stream->public.timing.v_border_top +
932
+
pipe->stream->public.timing.v_addressable +
933
+
pipe->stream->public.timing.v_border_bottom)
934
+
* (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0);
935
+
936
+
pipe->pipe_dlg_param.vblank_start = asic_blank_start;
937
+
pipe->pipe_dlg_param.vblank_end = asic_blank_end;
938
+
939
+
if (pipe->surface) {
940
+
struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
941
+
942
+
if (v->dpp_per_plane[input_idx] == 2 ||
943
+
(pipe->stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
944
+
pipe->stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE)) {
945
+
if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
946
+
/* update previously split pipe */
947
+
hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
948
+
hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx];
949
+
hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
950
+
hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
951
+
952
+
hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total;
953
+
hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total;
954
+
hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
955
+
hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
956
+
} else {
957
+
/* pipe not split previously needs split */
958
+
hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool);
959
+
ASSERT(hsplit_pipe);
960
+
split_stream_across_pipes(
961
+
&context->res_ctx, pool,
962
+
pipe, hsplit_pipe);
963
+
}
964
+
965
+
dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe);
966
+
} else if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
967
+
/* merge previously split pipe */
968
+
if (pipe->bottom_pipe->bottom_pipe)
969
+
pipe->bottom_pipe->bottom_pipe->top_pipe = pipe;
970
+
memset(pipe->bottom_pipe, 0, sizeof(*pipe->bottom_pipe));
971
+
pipe->bottom_pipe = pipe->bottom_pipe->bottom_pipe;
972
+
resource_build_scaling_params(pipe);
973
+
}
974
+
/* for now important to do this after pipe split for building e2e params */
975
+
dcn_bw_calc_rq_dlg_ttu(dc, v, pipe);
976
+
}
977
+
978
+
input_idx++;
979
+
}
980
+
if (dc->public.debug.use_dml_wm)
981
+
dcn_dml_wm_override(v, (struct display_mode_lib *)
982
+
&dc->dml, context, pool);
983
+
}
984
+
985
+
kernel_fpu_end();
986
+
return v->voltage_level != 5;
987
+
}
988
+
989
+
unsigned int dcn_find_normalized_clock_vdd_Level(
990
+
const struct core_dc *dc,
991
+
enum dm_pp_clock_type clocks_type,
992
+
int clocks_in_khz)
993
+
{
994
+
int vdd_level = dcn_bw_v_min0p65;
995
+
996
+
if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
997
+
return vdd_level;
998
+
999
+
switch (clocks_type) {
1000
+
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
1001
+
if (clocks_in_khz > dc->dcn_soc.max_dispclk_vmax0p9*1000) {
1002
+
vdd_level = dcn_bw_v_max0p91;
1003
+
BREAK_TO_DEBUGGER();
1004
+
} else if (clocks_in_khz > dc->dcn_soc.max_dispclk_vnom0p8*1000) {
1005
+
vdd_level = dcn_bw_v_max0p9;
1006
+
} else if (clocks_in_khz > dc->dcn_soc.max_dispclk_vmid0p72*1000) {
1007
+
vdd_level = dcn_bw_v_nom0p8;
1008
+
} else if (clocks_in_khz > dc->dcn_soc.max_dispclk_vmin0p65*1000) {
1009
+
vdd_level = dcn_bw_v_mid0p72;
1010
+
} else
1011
+
vdd_level = dcn_bw_v_min0p65;
1012
+
break;
1013
+
case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
1014
+
if (clocks_in_khz > dc->dcn_soc.phyclkv_max0p9*1000) {
1015
+
vdd_level = dcn_bw_v_max0p91;
1016
+
BREAK_TO_DEBUGGER();
1017
+
} else if (clocks_in_khz > dc->dcn_soc.phyclkv_nom0p8*1000) {
1018
+
vdd_level = dcn_bw_v_max0p9;
1019
+
} else if (clocks_in_khz > dc->dcn_soc.phyclkv_mid0p72*1000) {
1020
+
vdd_level = dcn_bw_v_nom0p8;
1021
+
} else if (clocks_in_khz > dc->dcn_soc.phyclkv_min0p65*1000) {
1022
+
vdd_level = dcn_bw_v_mid0p72;
1023
+
} else
1024
+
vdd_level = dcn_bw_v_min0p65;
1025
+
break;
1026
+
1027
+
case DM_PP_CLOCK_TYPE_DPPCLK:
1028
+
if (clocks_in_khz > dc->dcn_soc.max_dppclk_vmax0p9*1000) {
1029
+
vdd_level = dcn_bw_v_max0p91;
1030
+
BREAK_TO_DEBUGGER();
1031
+
} else if (clocks_in_khz > dc->dcn_soc.max_dppclk_vnom0p8*1000) {
1032
+
vdd_level = dcn_bw_v_max0p9;
1033
+
} else if (clocks_in_khz > dc->dcn_soc.max_dppclk_vmid0p72*1000) {
1034
+
vdd_level = dcn_bw_v_nom0p8;
1035
+
} else if (clocks_in_khz > dc->dcn_soc.max_dppclk_vmin0p65*1000) {
1036
+
vdd_level = dcn_bw_v_mid0p72;
1037
+
} else
1038
+
vdd_level = dcn_bw_v_min0p65;
1039
+
break;
1040
+
1041
+
case DM_PP_CLOCK_TYPE_MEMORY_CLK:
1042
+
{
1043
+
unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc.number_of_channels);
1044
+
if (clocks_in_khz > dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
1045
+
vdd_level = dcn_bw_v_max0p91;
1046
+
BREAK_TO_DEBUGGER();
1047
+
} else if (clocks_in_khz > dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
1048
+
vdd_level = dcn_bw_v_max0p9;
1049
+
} else if (clocks_in_khz > dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
1050
+
vdd_level = dcn_bw_v_nom0p8;
1051
+
} else if (clocks_in_khz > dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
1052
+
vdd_level = dcn_bw_v_mid0p72;
1053
+
} else
1054
+
vdd_level = dcn_bw_v_min0p65;
1055
+
}
1056
+
break;
1057
+
1058
+
case DM_PP_CLOCK_TYPE_DCFCLK:
1059
+
if (clocks_in_khz > dc->dcn_soc.dcfclkv_max0p9*1000) {
1060
+
vdd_level = dcn_bw_v_max0p91;
1061
+
BREAK_TO_DEBUGGER();
1062
+
} else if (clocks_in_khz > dc->dcn_soc.dcfclkv_nom0p8*1000) {
1063
+
vdd_level = dcn_bw_v_max0p9;
1064
+
} else if (clocks_in_khz > dc->dcn_soc.dcfclkv_mid0p72*1000) {
1065
+
vdd_level = dcn_bw_v_nom0p8;
1066
+
} else if (clocks_in_khz > dc->dcn_soc.dcfclkv_min0p65*1000) {
1067
+
vdd_level = dcn_bw_v_mid0p72;
1068
+
} else
1069
+
vdd_level = dcn_bw_v_min0p65;
1070
+
break;
1071
+
1072
+
default:
1073
+
break;
1074
+
}
1075
+
return vdd_level;
1076
+
}
1077
+
1078
+
unsigned int dcn_find_dcfclk_suits_all(
1079
+
const struct core_dc *dc,
1080
+
struct clocks_value *clocks)
1081
+
{
1082
+
unsigned vdd_level, vdd_level_temp;
1083
+
unsigned dcf_clk;
1084
+
1085
+
/*find a common supported voltage level*/
1086
+
vdd_level = dcn_find_normalized_clock_vdd_Level(
1087
+
dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_in_khz);
1088
+
vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1089
+
dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_in_khz);
1090
+
1091
+
vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1092
+
vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1093
+
dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_in_khz);
1094
+
vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1095
+
1096
+
vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1097
+
dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->dcfclock_in_khz);
1098
+
vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1099
+
vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1100
+
dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclock_in_khz);
1101
+
1102
+
/*find that level conresponding dcfclk*/
1103
+
vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1104
+
if (vdd_level == dcn_bw_v_max0p91) {
1105
+
BREAK_TO_DEBUGGER();
1106
+
dcf_clk = dc->dcn_soc.dcfclkv_max0p9*1000;
1107
+
} else if (vdd_level == dcn_bw_v_max0p9)
1108
+
dcf_clk = dc->dcn_soc.dcfclkv_max0p9*1000;
1109
+
else if (vdd_level == dcn_bw_v_nom0p8)
1110
+
dcf_clk = dc->dcn_soc.dcfclkv_nom0p8*1000;
1111
+
else if (vdd_level == dcn_bw_v_mid0p72)
1112
+
dcf_clk = dc->dcn_soc.dcfclkv_mid0p72*1000;
1113
+
else
1114
+
dcf_clk = dc->dcn_soc.dcfclkv_min0p65*1000;
1115
+
1116
+
dm_logger_write(dc->ctx->logger, LOG_HW_MARKS,
1117
+
"\tdcf_clk for voltage = %d\n", dcf_clk);
1118
+
return dcf_clk;
1119
+
}
1120
+
1121
+
void dcn_bw_update_from_pplib(struct core_dc *dc)
1122
+
{
1123
+
struct dc_context *ctx = dc->ctx;
1124
+
struct dm_pp_clock_levels_with_latency clks = {0};
1125
+
struct dm_pp_clock_levels_with_voltage clks2 = {0};
1126
+
1127
+
kernel_fpu_begin();
1128
+
dc->dcn_soc.number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1129
+
ASSERT(dc->dcn_soc.number_of_channels && dc->dcn_soc.number_of_channels < 3);
1130
+
if (dc->dcn_soc.number_of_channels == 0)/*old sbios bug*/
1131
+
dc->dcn_soc.number_of_channels = 2;
1132
+
1133
+
if (dm_pp_get_clock_levels_by_type_with_voltage(
1134
+
ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, &clks2) &&
1135
+
clks2.num_levels >= 3) {
1136
+
dc->dcn_soc.max_dispclk_vmin0p65 = clks2.data[0].clocks_in_khz / 1000.0;
1137
+
dc->dcn_soc.max_dispclk_vmid0p72 = clks2.data[clks2.num_levels - 3].clocks_in_khz / 1000.0;
1138
+
dc->dcn_soc.max_dispclk_vnom0p8 = clks2.data[clks2.num_levels - 2].clocks_in_khz / 1000.0;
1139
+
dc->dcn_soc.max_dispclk_vmax0p9 = clks2.data[clks2.num_levels - 1].clocks_in_khz / 1000.0;
1140
+
} else
1141
+
BREAK_TO_DEBUGGER();
1142
+
/*
1143
+
if (dm_pp_get_clock_levels_by_type_with_latency(
1144
+
ctx, DM_PP_CLOCK_TYPE_MEMORY_CLK, &clks) &&
1145
+
clks.num_levels != 0) {
1146
+
//this is to get DRAM data_rate
1147
+
//FabricAndDRAMBandwidth = min(64*FCLK , Data rate * single_Channel_Width * number of channels);
1148
+
}*/
1149
+
if (dm_pp_get_clock_levels_by_type_with_latency(
1150
+
ctx, DM_PP_CLOCK_TYPE_FCLK, &clks) &&
1151
+
clks.num_levels != 0) {
1152
+
ASSERT(clks.num_levels >= 3);
1153
+
dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc.number_of_channels *
1154
+
(clks.data[0].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
1155
+
if (clks.num_levels > 2) {
1156
+
dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc.number_of_channels *
1157
+
(clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
1158
+
} else {
1159
+
dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc.number_of_channels *
1160
+
(clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
1161
+
}
1162
+
dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc.number_of_channels *
1163
+
(clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
1164
+
dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc.number_of_channels *
1165
+
(clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
1166
+
} else
1167
+
BREAK_TO_DEBUGGER();
1168
+
if (dm_pp_get_clock_levels_by_type_with_latency(
1169
+
ctx, DM_PP_CLOCK_TYPE_DCFCLK, &clks) &&
1170
+
clks.num_levels >= 3) {
1171
+
dc->dcn_soc.dcfclkv_min0p65 = clks.data[0].clocks_in_khz / 1000.0;
1172
+
dc->dcn_soc.dcfclkv_mid0p72 = clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0;
1173
+
dc->dcn_soc.dcfclkv_nom0p8 = clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0;
1174
+
dc->dcn_soc.dcfclkv_max0p9 = clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0;
1175
+
} else
1176
+
BREAK_TO_DEBUGGER();
1177
+
if (dm_pp_get_clock_levels_by_type_with_voltage(
1178
+
ctx, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, &clks2) &&
1179
+
clks2.num_levels >= 3) {
1180
+
dc->dcn_soc.phyclkv_min0p65 = clks2.data[0].clocks_in_khz / 1000.0;
1181
+
dc->dcn_soc.phyclkv_mid0p72 = clks2.data[clks2.num_levels - 3].clocks_in_khz / 1000.0;
1182
+
dc->dcn_soc.phyclkv_nom0p8 = clks2.data[clks2.num_levels - 2].clocks_in_khz / 1000.0;
1183
+
dc->dcn_soc.phyclkv_max0p9 = clks2.data[clks2.num_levels - 1].clocks_in_khz / 1000.0;
1184
+
} else
1185
+
BREAK_TO_DEBUGGER();
1186
+
if (dm_pp_get_clock_levels_by_type_with_latency(
1187
+
ctx, DM_PP_CLOCK_TYPE_DPPCLK, &clks) &&
1188
+
clks.num_levels >= 3) {
1189
+
dc->dcn_soc.max_dppclk_vmin0p65 = clks.data[0].clocks_in_khz / 1000.0;
1190
+
dc->dcn_soc.max_dppclk_vmid0p72 = clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0;
1191
+
dc->dcn_soc.max_dppclk_vnom0p8 = clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0;
1192
+
dc->dcn_soc.max_dppclk_vmax0p9 = clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0;
1193
+
}
1194
+
1195
+
if (dm_pp_get_clock_levels_by_type_with_latency(
1196
+
ctx, DM_PP_CLOCK_TYPE_SOCCLK, &clks) &&
1197
+
clks.num_levels >= 3) {
1198
+
dc->dcn_soc.socclk = clks.data[0].clocks_in_khz / 1000.0;
1199
+
} else
1200
+
BREAK_TO_DEBUGGER();
1201
+
kernel_fpu_end();
1202
+
}
1203
+
1204
+
void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc)
1205
+
{
1206
+
struct dm_pp_wm_sets_with_clock_ranges_soc15 clk_ranges = {0};
1207
+
int max_fclk_khz, nom_fclk_khz, min_fclk_khz, max_dcfclk_khz,
1208
+
nom_dcfclk_khz, min_dcfclk_khz, socclk_khz;
1209
+
const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
1210
+
unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc.number_of_channels);
1211
+
1212
+
kernel_fpu_begin();
1213
+
max_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 * 1000000 / factor;
1214
+
nom_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 * 1000000 / factor;
1215
+
min_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 * 1000000 / factor;
1216
+
max_dcfclk_khz = dc->dcn_soc.dcfclkv_max0p9 * 1000;
1217
+
nom_dcfclk_khz = dc->dcn_soc.dcfclkv_nom0p8 * 1000;
1218
+
min_dcfclk_khz = dc->dcn_soc.dcfclkv_min0p65 * 1000;
1219
+
socclk_khz = dc->dcn_soc.socclk * 1000;
1220
+
kernel_fpu_end();
1221
+
1222
+
/* Now notify PPLib/SMU about which Watermarks sets they should select
1223
+
* depending on DPM state they are in. And update BW MGR GFX Engine and
1224
+
* Memory clock member variables for Watermarks calculations for each
1225
+
* Watermark Set
1226
+
*/
1227
+
/* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
1228
+
* care what the value is, hence min to overdrive level
1229
+
*/
1230
+
clk_ranges.num_wm_dmif_sets = 4;
1231
+
clk_ranges.num_wm_mcif_sets = 4;
1232
+
clk_ranges.wm_dmif_clocks_ranges[0].wm_set_id = WM_SET_A;
1233
+
clk_ranges.wm_dmif_clocks_ranges[0].wm_min_dcfclk_clk_in_khz = min_dcfclk_khz;
1234
+
clk_ranges.wm_dmif_clocks_ranges[0].wm_max_dcfclk_clk_in_khz = nom_dcfclk_khz - 1;
1235
+
clk_ranges.wm_dmif_clocks_ranges[0].wm_min_memg_clk_in_khz = min_fclk_khz;
1236
+
clk_ranges.wm_dmif_clocks_ranges[0].wm_max_mem_clk_in_khz = nom_fclk_khz - 1;
1237
+
clk_ranges.wm_mcif_clocks_ranges[0].wm_set_id = WM_SET_A;
1238
+
clk_ranges.wm_mcif_clocks_ranges[0].wm_min_socclk_clk_in_khz = socclk_khz;
1239
+
clk_ranges.wm_mcif_clocks_ranges[0].wm_max_socclk_clk_in_khz = overdrive;
1240
+
clk_ranges.wm_mcif_clocks_ranges[0].wm_min_memg_clk_in_khz = min_fclk_khz;
1241
+
clk_ranges.wm_mcif_clocks_ranges[0].wm_max_mem_clk_in_khz = nom_fclk_khz - 1;
1242
+
1243
+
clk_ranges.wm_dmif_clocks_ranges[1].wm_set_id = WM_SET_B;
1244
+
clk_ranges.wm_dmif_clocks_ranges[1].wm_min_dcfclk_clk_in_khz = min_dcfclk_khz;
1245
+
clk_ranges.wm_dmif_clocks_ranges[1].wm_max_dcfclk_clk_in_khz = nom_dcfclk_khz - 1;
1246
+
clk_ranges.wm_dmif_clocks_ranges[1].wm_min_memg_clk_in_khz = nom_fclk_khz;
1247
+
clk_ranges.wm_dmif_clocks_ranges[1].wm_max_mem_clk_in_khz = max_fclk_khz;
1248
+
clk_ranges.wm_mcif_clocks_ranges[1].wm_set_id = WM_SET_B;
1249
+
clk_ranges.wm_mcif_clocks_ranges[1].wm_min_socclk_clk_in_khz = socclk_khz;
1250
+
clk_ranges.wm_mcif_clocks_ranges[1].wm_max_socclk_clk_in_khz = overdrive;
1251
+
clk_ranges.wm_mcif_clocks_ranges[1].wm_min_memg_clk_in_khz = nom_fclk_khz;
1252
+
clk_ranges.wm_mcif_clocks_ranges[1].wm_max_mem_clk_in_khz = max_fclk_khz;
1253
+
1254
+
1255
+
clk_ranges.wm_dmif_clocks_ranges[2].wm_set_id = WM_SET_C;
1256
+
clk_ranges.wm_dmif_clocks_ranges[2].wm_min_dcfclk_clk_in_khz = nom_dcfclk_khz;
1257
+
clk_ranges.wm_dmif_clocks_ranges[2].wm_max_dcfclk_clk_in_khz = max_dcfclk_khz;
1258
+
clk_ranges.wm_dmif_clocks_ranges[2].wm_min_memg_clk_in_khz = nom_fclk_khz;
1259
+
clk_ranges.wm_dmif_clocks_ranges[2].wm_max_mem_clk_in_khz = max_fclk_khz;
1260
+
clk_ranges.wm_mcif_clocks_ranges[2].wm_set_id = WM_SET_C;
1261
+
clk_ranges.wm_mcif_clocks_ranges[2].wm_min_socclk_clk_in_khz = socclk_khz;
1262
+
clk_ranges.wm_mcif_clocks_ranges[2].wm_max_socclk_clk_in_khz = overdrive;
1263
+
clk_ranges.wm_mcif_clocks_ranges[2].wm_min_memg_clk_in_khz = nom_fclk_khz;
1264
+
clk_ranges.wm_mcif_clocks_ranges[2].wm_max_mem_clk_in_khz = max_fclk_khz;
1265
+
1266
+
clk_ranges.wm_dmif_clocks_ranges[3].wm_set_id = WM_SET_D;
1267
+
clk_ranges.wm_dmif_clocks_ranges[3].wm_min_dcfclk_clk_in_khz = max_dcfclk_khz + 1;
1268
+
clk_ranges.wm_dmif_clocks_ranges[3].wm_max_dcfclk_clk_in_khz = overdrive;
1269
+
clk_ranges.wm_dmif_clocks_ranges[3].wm_min_memg_clk_in_khz = max_fclk_khz + 1;
1270
+
clk_ranges.wm_dmif_clocks_ranges[3].wm_max_mem_clk_in_khz = overdrive;
1271
+
clk_ranges.wm_mcif_clocks_ranges[3].wm_set_id = WM_SET_D;
1272
+
clk_ranges.wm_mcif_clocks_ranges[3].wm_min_socclk_clk_in_khz = socclk_khz;
1273
+
clk_ranges.wm_mcif_clocks_ranges[3].wm_max_socclk_clk_in_khz = overdrive;
1274
+
clk_ranges.wm_mcif_clocks_ranges[3].wm_min_memg_clk_in_khz = max_fclk_khz + 1;
1275
+
clk_ranges.wm_mcif_clocks_ranges[3].wm_max_mem_clk_in_khz = overdrive;
1276
+
1277
+
/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1278
+
dm_pp_notify_wm_clock_changes_soc15(dc->ctx, &clk_ranges);
1279
+
}
1280
+
1281
+
void dcn_bw_sync_calcs_and_dml(struct core_dc *dc)
1282
+
{
1283
+
kernel_fpu_begin();
1284
+
dc->dml.soc.vmin.socclk_mhz = dc->dcn_soc.socclk;
1285
+
dc->dml.soc.vmid.socclk_mhz = dc->dcn_soc.socclk;
1286
+
dc->dml.soc.vnom.socclk_mhz = dc->dcn_soc.socclk;
1287
+
dc->dml.soc.vmax.socclk_mhz = dc->dcn_soc.socclk;
1288
+
1289
+
dc->dml.soc.vmin.dcfclk_mhz = dc->dcn_soc.dcfclkv_min0p65;
1290
+
dc->dml.soc.vmid.dcfclk_mhz = dc->dcn_soc.dcfclkv_mid0p72;
1291
+
dc->dml.soc.vnom.dcfclk_mhz = dc->dcn_soc.dcfclkv_nom0p8;
1292
+
dc->dml.soc.vmax.dcfclk_mhz = dc->dcn_soc.dcfclkv_max0p9;
1293
+
1294
+
dc->dml.soc.vmin.dispclk_mhz = dc->dcn_soc.max_dispclk_vmin0p65;
1295
+
dc->dml.soc.vmid.dispclk_mhz = dc->dcn_soc.max_dispclk_vmid0p72;
1296
+
dc->dml.soc.vnom.dispclk_mhz = dc->dcn_soc.max_dispclk_vnom0p8;
1297
+
dc->dml.soc.vmax.dispclk_mhz = dc->dcn_soc.max_dispclk_vmax0p9;
1298
+
1299
+
dc->dml.soc.vmin.dppclk_mhz = dc->dcn_soc.max_dppclk_vmin0p65;
1300
+
dc->dml.soc.vmid.dppclk_mhz = dc->dcn_soc.max_dppclk_vmid0p72;
1301
+
dc->dml.soc.vnom.dppclk_mhz = dc->dcn_soc.max_dppclk_vnom0p8;
1302
+
dc->dml.soc.vmax.dppclk_mhz = dc->dcn_soc.max_dppclk_vmax0p9;
1303
+
1304
+
dc->dml.soc.vmin.phyclk_mhz = dc->dcn_soc.phyclkv_min0p65;
1305
+
dc->dml.soc.vmid.phyclk_mhz = dc->dcn_soc.phyclkv_mid0p72;
1306
+
dc->dml.soc.vnom.phyclk_mhz = dc->dcn_soc.phyclkv_nom0p8;
1307
+
dc->dml.soc.vmax.phyclk_mhz = dc->dcn_soc.phyclkv_max0p9;
1308
+
1309
+
dc->dml.soc.vmin.dram_bw_per_chan_gbps = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65;
1310
+
dc->dml.soc.vmid.dram_bw_per_chan_gbps = dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72;
1311
+
dc->dml.soc.vnom.dram_bw_per_chan_gbps = dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8;
1312
+
dc->dml.soc.vmax.dram_bw_per_chan_gbps = dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9;
1313
+
1314
+
dc->dml.soc.sr_exit_time_us = dc->dcn_soc.sr_exit_time;
1315
+
dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc.sr_enter_plus_exit_time;
1316
+
dc->dml.soc.urgent_latency_us = dc->dcn_soc.urgent_latency;
1317
+
dc->dml.soc.writeback_latency_us = dc->dcn_soc.write_back_latency;
1318
+
dc->dml.soc.ideal_dram_bw_after_urgent_percent =
1319
+
dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency;
1320
+
dc->dml.soc.max_request_size_bytes = dc->dcn_soc.max_request_size;
1321
+
dc->dml.soc.downspread_percent = dc->dcn_soc.downspreading;
1322
+
dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
1323
+
dc->dcn_soc.round_trip_ping_latency_cycles;
1324
+
dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
1325
+
dc->dcn_soc.urgent_out_of_order_return_per_channel;
1326
+
dc->dml.soc.num_chans = dc->dcn_soc.number_of_channels;
1327
+
dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc.vmm_page_size;
1328
+
dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc.dram_clock_change_latency;
1329
+
dc->dml.soc.return_bus_width_bytes = dc->dcn_soc.return_bus_width;
1330
+
1331
+
dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip.rob_buffer_size_in_kbyte;
1332
+
dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip.det_buffer_size_in_kbyte;
1333
+
dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip.dpp_output_buffer_pixels;
1334
+
dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip.opp_output_buffer_lines;
1335
+
dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip.pixel_chunk_size_in_kbyte;
1336
+
dc->dml.ip.pte_enable = dc->dcn_ip.pte_enable == dcn_bw_yes;
1337
+
dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip.pte_chunk_size;
1338
+
dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip.meta_chunk_size;
1339
+
dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip.writeback_chunk_size;
1340
+
dc->dml.ip.line_buffer_size_bits = dc->dcn_ip.line_buffer_size;
1341
+
dc->dml.ip.max_line_buffer_lines = dc->dcn_ip.max_line_buffer_lines;
1342
+
dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip.is_line_buffer_bpp_fixed == dcn_bw_yes;
1343
+
dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip.line_buffer_fixed_bpp;
1344
+
dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip.writeback_luma_buffer_size;
1345
+
dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip.writeback_chroma_buffer_size;
1346
+
dc->dml.ip.max_num_dpp = dc->dcn_ip.max_num_dpp;
1347
+
dc->dml.ip.max_num_wb = dc->dcn_ip.max_num_writeback;
1348
+
dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip.max_dchub_topscl_throughput;
1349
+
dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip.max_pscl_tolb_throughput;
1350
+
dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip.max_lb_tovscl_throughput;
1351
+
dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip.max_vscl_tohscl_throughput;
1352
+
dc->dml.ip.max_hscl_ratio = dc->dcn_ip.max_hscl_ratio;
1353
+
dc->dml.ip.max_vscl_ratio = dc->dcn_ip.max_vscl_ratio;
1354
+
dc->dml.ip.max_hscl_taps = dc->dcn_ip.max_hscl_taps;
1355
+
dc->dml.ip.max_vscl_taps = dc->dcn_ip.max_vscl_taps;
1356
+
/*pte_buffer_size_in_requests missing in dml*/
1357
+
dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip.dispclk_ramping_margin;
1358
+
dc->dml.ip.underscan_factor = dc->dcn_ip.under_scan_factor;
1359
+
dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip.max_inter_dcn_tile_repeaters;
1360
+
dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
1361
+
dc->dcn_ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
1362
+
dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
1363
+
dc->dcn_ip.bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
1364
+
dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip.dcfclk_cstate_latency;
1365
+
kernel_fpu_end();
1366
+
}
+629
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+629
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
···
1
+
/*
2
+
* Copyright 2017 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: AMD
23
+
*
24
+
*/
25
+
26
+
/**
27
+
* Bandwidth and Watermark calculations interface.
28
+
* (Refer to "DCEx_mode_support.xlsm" from Perforce.)
29
+
*/
30
+
#ifndef __DCN_CALCS_H__
31
+
#define __DCN_CALCS_H__
32
+
33
+
#include "bw_fixed.h"
34
+
#include "display_clock.h"
35
+
#include "../dml/display_mode_lib.h"
36
+
37
+
struct core_dc;
38
+
struct validate_context;
39
+
40
+
/*******************************************************************************
41
+
* DCN data structures.
42
+
******************************************************************************/
43
+
44
+
#define number_of_planes 6
45
+
#define number_of_planes_minus_one 5
46
+
#define number_of_states 4
47
+
#define number_of_states_plus_one 5
48
+
49
+
#define ddr4_dram_width 64
50
+
#define ddr4_dram_factor_single_Channel 16
51
+
enum dcn_bw_defs {
52
+
dcn_bw_v_min0p65,
53
+
dcn_bw_v_mid0p72,
54
+
dcn_bw_v_nom0p8,
55
+
dcn_bw_v_max0p9,
56
+
dcn_bw_v_max0p91,
57
+
dcn_bw_no_support = 5,
58
+
dcn_bw_yes,
59
+
dcn_bw_hor,
60
+
dcn_bw_vert,
61
+
dcn_bw_override,
62
+
dcn_bw_rgb_sub_64,
63
+
dcn_bw_rgb_sub_32,
64
+
dcn_bw_rgb_sub_16,
65
+
dcn_bw_no,
66
+
dcn_bw_sw_linear,
67
+
dcn_bw_sw_4_kb_d,
68
+
dcn_bw_sw_4_kb_d_x,
69
+
dcn_bw_sw_64_kb_d,
70
+
dcn_bw_sw_64_kb_d_t,
71
+
dcn_bw_sw_64_kb_d_x,
72
+
dcn_bw_sw_var_d,
73
+
dcn_bw_sw_var_d_x,
74
+
dcn_bw_yuv420_sub_8,
75
+
dcn_bw_sw_4_kb_s,
76
+
dcn_bw_sw_4_kb_s_x,
77
+
dcn_bw_sw_64_kb_s,
78
+
dcn_bw_sw_64_kb_s_t,
79
+
dcn_bw_sw_64_kb_s_x,
80
+
dcn_bw_writeback,
81
+
dcn_bw_444,
82
+
dcn_bw_dp,
83
+
dcn_bw_420,
84
+
dcn_bw_hdmi,
85
+
dcn_bw_sw_var_s,
86
+
dcn_bw_sw_var_s_x,
87
+
dcn_bw_yuv420_sub_10,
88
+
dcn_bw_supported_in_v_active,
89
+
dcn_bw_supported_in_v_blank,
90
+
dcn_bw_not_supported,
91
+
dcn_bw_na,
92
+
};
93
+
94
+
/*bounding box parameters*/
95
+
/*mode parameters*/
96
+
/*system configuration*/
97
+
/* display configuration*/
98
+
struct dcn_bw_internal_vars {
99
+
float voltage[number_of_states_plus_one + 1];
100
+
float max_dispclk[number_of_states_plus_one + 1];
101
+
float max_dppclk[number_of_states_plus_one + 1];
102
+
float dcfclk_per_state[number_of_states_plus_one + 1];
103
+
float phyclk_per_state[number_of_states_plus_one + 1];
104
+
float fabric_and_dram_bandwidth_per_state[number_of_states_plus_one + 1];
105
+
float sr_exit_time;
106
+
float sr_enter_plus_exit_time;
107
+
float dram_clock_change_latency;
108
+
float urgent_latency;
109
+
float write_back_latency;
110
+
float percent_of_ideal_drambw_received_after_urg_latency;
111
+
float dcfclkv_max0p9;
112
+
float dcfclkv_nom0p8;
113
+
float dcfclkv_mid0p72;
114
+
float dcfclkv_min0p65;
115
+
float max_dispclk_vmax0p9;
116
+
float max_dppclk_vmax0p9;
117
+
float max_dispclk_vnom0p8;
118
+
float max_dppclk_vnom0p8;
119
+
float max_dispclk_vmid0p72;
120
+
float max_dppclk_vmid0p72;
121
+
float max_dispclk_vmin0p65;
122
+
float max_dppclk_vmin0p65;
123
+
float socclk;
124
+
float fabric_and_dram_bandwidth_vmax0p9;
125
+
float fabric_and_dram_bandwidth_vnom0p8;
126
+
float fabric_and_dram_bandwidth_vmid0p72;
127
+
float fabric_and_dram_bandwidth_vmin0p65;
128
+
float round_trip_ping_latency_cycles;
129
+
float urgent_out_of_order_return_per_channel;
130
+
float number_of_channels;
131
+
float vmm_page_size;
132
+
float return_bus_width;
133
+
float rob_buffer_size_in_kbyte;
134
+
float det_buffer_size_in_kbyte;
135
+
float dpp_output_buffer_pixels;
136
+
float opp_output_buffer_lines;
137
+
float pixel_chunk_size_in_kbyte;
138
+
float pte_chunk_size;
139
+
float meta_chunk_size;
140
+
float writeback_chunk_size;
141
+
enum dcn_bw_defs odm_capability;
142
+
enum dcn_bw_defs dsc_capability;
143
+
float line_buffer_size;
144
+
enum dcn_bw_defs is_line_buffer_bpp_fixed;
145
+
float line_buffer_fixed_bpp;
146
+
float max_line_buffer_lines;
147
+
float writeback_luma_buffer_size;
148
+
float writeback_chroma_buffer_size;
149
+
float max_num_dpp;
150
+
float max_num_writeback;
151
+
float max_dchub_topscl_throughput;
152
+
float max_pscl_tolb_throughput;
153
+
float max_lb_tovscl_throughput;
154
+
float max_vscl_tohscl_throughput;
155
+
float max_hscl_ratio;
156
+
float max_vscl_ratio;
157
+
float max_hscl_taps;
158
+
float max_vscl_taps;
159
+
float under_scan_factor;
160
+
float phyclkv_max0p9;
161
+
float phyclkv_nom0p8;
162
+
float phyclkv_mid0p72;
163
+
float phyclkv_min0p65;
164
+
float pte_buffer_size_in_requests;
165
+
float dispclk_ramping_margin;
166
+
float downspreading;
167
+
float max_inter_dcn_tile_repeaters;
168
+
enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
169
+
enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed;
170
+
int mode;
171
+
float viewport_width[number_of_planes_minus_one + 1];
172
+
float htotal[number_of_planes_minus_one + 1];
173
+
float vtotal[number_of_planes_minus_one + 1];
174
+
float v_sync_plus_back_porch[number_of_planes_minus_one + 1];
175
+
float vactive[number_of_planes_minus_one + 1];
176
+
float pixel_clock[number_of_planes_minus_one + 1]; /*MHz*/
177
+
float viewport_height[number_of_planes_minus_one + 1];
178
+
enum dcn_bw_defs dcc_enable[number_of_planes_minus_one + 1];
179
+
float dcc_rate[number_of_planes_minus_one + 1];
180
+
enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1];
181
+
float lb_bit_per_pixel[number_of_planes_minus_one + 1];
182
+
enum dcn_bw_defs source_pixel_format[number_of_planes_minus_one + 1];
183
+
enum dcn_bw_defs source_surface_mode[number_of_planes_minus_one + 1];
184
+
enum dcn_bw_defs output_format[number_of_planes_minus_one + 1];
185
+
enum dcn_bw_defs output[number_of_planes_minus_one + 1];
186
+
float scaler_rec_out_width[number_of_planes_minus_one + 1];
187
+
float scaler_recout_height[number_of_planes_minus_one + 1];
188
+
float underscan_output[number_of_planes_minus_one + 1];
189
+
float interlace_output[number_of_planes_minus_one + 1];
190
+
float override_hta_ps[number_of_planes_minus_one + 1];
191
+
float override_vta_ps[number_of_planes_minus_one + 1];
192
+
float override_hta_pschroma[number_of_planes_minus_one + 1];
193
+
float override_vta_pschroma[number_of_planes_minus_one + 1];
194
+
float urgent_latency_support_us[number_of_planes_minus_one + 1];
195
+
float h_ratio[number_of_planes_minus_one + 1];
196
+
float v_ratio[number_of_planes_minus_one + 1];
197
+
float htaps[number_of_planes_minus_one + 1];
198
+
float vtaps[number_of_planes_minus_one + 1];
199
+
float hta_pschroma[number_of_planes_minus_one + 1];
200
+
float vta_pschroma[number_of_planes_minus_one + 1];
201
+
enum dcn_bw_defs pte_enable;
202
+
enum dcn_bw_defs synchronized_vblank;
203
+
enum dcn_bw_defs ta_pscalculation;
204
+
int voltage_override_level;
205
+
int number_of_active_planes;
206
+
int voltage_level;
207
+
enum dcn_bw_defs immediate_flip_supported;
208
+
float dcfclk;
209
+
float max_phyclk;
210
+
float fabric_and_dram_bandwidth;
211
+
float dpp_per_plane_per_ratio[1 + 1][number_of_planes_minus_one + 1];
212
+
enum dcn_bw_defs dispclk_dppclk_support_per_ratio[1 + 1];
213
+
float required_dispclk_per_ratio[1 + 1];
214
+
enum dcn_bw_defs error_message[1 + 1];
215
+
int dispclk_dppclk_ratio;
216
+
float dpp_per_plane[number_of_planes_minus_one + 1];
217
+
float det_buffer_size_y[number_of_planes_minus_one + 1];
218
+
float det_buffer_size_c[number_of_planes_minus_one + 1];
219
+
float swath_height_y[number_of_planes_minus_one + 1];
220
+
float swath_height_c[number_of_planes_minus_one + 1];
221
+
enum dcn_bw_defs final_error_message;
222
+
float frequency;
223
+
float header_line;
224
+
float header;
225
+
enum dcn_bw_defs voltage_override;
226
+
enum dcn_bw_defs allow_different_hratio_vratio;
227
+
float acceptable_quality_hta_ps;
228
+
float acceptable_quality_vta_ps;
229
+
float no_of_dpp[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
230
+
float swath_width_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
231
+
float swath_height_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
232
+
float swath_height_cper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
233
+
float urgent_latency_support_us_per_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
234
+
float v_ratio_pre_ywith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
235
+
float v_ratio_pre_cwith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
236
+
float required_prefetch_pixel_data_bw_with_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
237
+
float v_ratio_pre_ywithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
238
+
float v_ratio_pre_cwithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
239
+
float required_prefetch_pixel_data_bw_without_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
240
+
enum dcn_bw_defs prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
241
+
enum dcn_bw_defs prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
242
+
enum dcn_bw_defs v_ratio_in_prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
243
+
enum dcn_bw_defs v_ratio_in_prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
244
+
float required_dispclk[number_of_states_plus_one + 1][1 + 1];
245
+
enum dcn_bw_defs dispclk_dppclk_support[number_of_states_plus_one + 1][1 + 1];
246
+
enum dcn_bw_defs total_available_pipes_support[number_of_states_plus_one + 1][1 + 1];
247
+
float total_number_of_active_dpp[number_of_states_plus_one + 1][1 + 1];
248
+
float total_number_of_dcc_active_dpp[number_of_states_plus_one + 1][1 + 1];
249
+
enum dcn_bw_defs urgent_latency_support[number_of_states_plus_one + 1][1 + 1];
250
+
enum dcn_bw_defs mode_support_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
251
+
enum dcn_bw_defs mode_support_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
252
+
float return_bw_per_state[number_of_states_plus_one + 1];
253
+
enum dcn_bw_defs dio_support[number_of_states_plus_one + 1];
254
+
float urgent_round_trip_and_out_of_order_latency_per_state[number_of_states_plus_one + 1];
255
+
enum dcn_bw_defs rob_support[number_of_states_plus_one + 1];
256
+
enum dcn_bw_defs bandwidth_support[number_of_states_plus_one + 1];
257
+
float prefetch_bw[number_of_planes_minus_one + 1];
258
+
float meta_pte_bytes_per_frame[number_of_planes_minus_one + 1];
259
+
float meta_row_bytes[number_of_planes_minus_one + 1];
260
+
float dpte_bytes_per_row[number_of_planes_minus_one + 1];
261
+
float prefetch_lines_y[number_of_planes_minus_one + 1];
262
+
float prefetch_lines_c[number_of_planes_minus_one + 1];
263
+
float max_num_sw_y[number_of_planes_minus_one + 1];
264
+
float max_num_sw_c[number_of_planes_minus_one + 1];
265
+
float line_times_for_prefetch[number_of_planes_minus_one + 1];
266
+
float lines_for_meta_pte_with_immediate_flip[number_of_planes_minus_one + 1];
267
+
float lines_for_meta_pte_without_immediate_flip[number_of_planes_minus_one + 1];
268
+
float lines_for_meta_and_dpte_row_with_immediate_flip[number_of_planes_minus_one + 1];
269
+
float lines_for_meta_and_dpte_row_without_immediate_flip[number_of_planes_minus_one + 1];
270
+
float min_dppclk_using_single_dpp[number_of_planes_minus_one + 1];
271
+
float swath_width_ysingle_dpp[number_of_planes_minus_one + 1];
272
+
float byte_per_pixel_in_dety[number_of_planes_minus_one + 1];
273
+
float byte_per_pixel_in_detc[number_of_planes_minus_one + 1];
274
+
float number_of_dpp_required_for_det_and_lb_size[number_of_planes_minus_one + 1];
275
+
float required_phyclk[number_of_planes_minus_one + 1];
276
+
float read256_block_height_y[number_of_planes_minus_one + 1];
277
+
float read256_block_width_y[number_of_planes_minus_one + 1];
278
+
float read256_block_height_c[number_of_planes_minus_one + 1];
279
+
float read256_block_width_c[number_of_planes_minus_one + 1];
280
+
float max_swath_height_y[number_of_planes_minus_one + 1];
281
+
float max_swath_height_c[number_of_planes_minus_one + 1];
282
+
float min_swath_height_y[number_of_planes_minus_one + 1];
283
+
float min_swath_height_c[number_of_planes_minus_one + 1];
284
+
float read_bandwidth[number_of_planes_minus_one + 1];
285
+
float write_bandwidth[number_of_planes_minus_one + 1];
286
+
float pscl_factor[number_of_planes_minus_one + 1];
287
+
float pscl_factor_chroma[number_of_planes_minus_one + 1];
288
+
enum dcn_bw_defs scale_ratio_support;
289
+
enum dcn_bw_defs source_format_pixel_and_scan_support;
290
+
float total_read_bandwidth_consumed_gbyte_per_second;
291
+
float total_write_bandwidth_consumed_gbyte_per_second;
292
+
float total_bandwidth_consumed_gbyte_per_second;
293
+
enum dcn_bw_defs dcc_enabled_in_any_plane;
294
+
float return_bw_todcn_per_state;
295
+
float critical_point;
296
+
enum dcn_bw_defs writeback_latency_support;
297
+
float required_output_bw;
298
+
float total_number_of_active_writeback;
299
+
enum dcn_bw_defs total_available_writeback_support;
300
+
float maximum_swath_width;
301
+
float number_of_dpp_required_for_det_size;
302
+
float number_of_dpp_required_for_lb_size;
303
+
float min_dispclk_using_single_dpp;
304
+
float min_dispclk_using_dual_dpp;
305
+
enum dcn_bw_defs viewport_size_support;
306
+
float swath_width_granularity_y;
307
+
float rounded_up_max_swath_size_bytes_y;
308
+
float swath_width_granularity_c;
309
+
float rounded_up_max_swath_size_bytes_c;
310
+
float lines_in_det_luma;
311
+
float lines_in_det_chroma;
312
+
float effective_lb_latency_hiding_source_lines_luma;
313
+
float effective_lb_latency_hiding_source_lines_chroma;
314
+
float effective_detlb_lines_luma;
315
+
float effective_detlb_lines_chroma;
316
+
float projected_dcfclk_deep_sleep;
317
+
float meta_req_height_y;
318
+
float meta_req_width_y;
319
+
float meta_surface_width_y;
320
+
float meta_surface_height_y;
321
+
float meta_pte_bytes_per_frame_y;
322
+
float meta_row_bytes_y;
323
+
float macro_tile_block_size_bytes_y;
324
+
float macro_tile_block_height_y;
325
+
float data_pte_req_height_y;
326
+
float data_pte_req_width_y;
327
+
float dpte_bytes_per_row_y;
328
+
float meta_req_height_c;
329
+
float meta_req_width_c;
330
+
float meta_surface_width_c;
331
+
float meta_surface_height_c;
332
+
float meta_pte_bytes_per_frame_c;
333
+
float meta_row_bytes_c;
334
+
float macro_tile_block_size_bytes_c;
335
+
float macro_tile_block_height_c;
336
+
float macro_tile_block_width_c;
337
+
float data_pte_req_height_c;
338
+
float data_pte_req_width_c;
339
+
float dpte_bytes_per_row_c;
340
+
float v_init_y;
341
+
float max_partial_sw_y;
342
+
float v_init_c;
343
+
float max_partial_sw_c;
344
+
float dst_x_after_scaler;
345
+
float dst_y_after_scaler;
346
+
float time_calc;
347
+
float v_update_offset[number_of_planes_minus_one + 1];
348
+
float total_repeater_delay;
349
+
float v_update_width[number_of_planes_minus_one + 1];
350
+
float v_ready_offset[number_of_planes_minus_one + 1];
351
+
float time_setup;
352
+
float extra_latency;
353
+
float maximum_vstartup;
354
+
float bw_available_for_immediate_flip;
355
+
float total_immediate_flip_bytes[number_of_planes_minus_one + 1];
356
+
float time_for_meta_pte_with_immediate_flip;
357
+
float time_for_meta_pte_without_immediate_flip;
358
+
float time_for_meta_and_dpte_row_with_immediate_flip;
359
+
float time_for_meta_and_dpte_row_without_immediate_flip;
360
+
float line_times_to_request_prefetch_pixel_data_with_immediate_flip;
361
+
float line_times_to_request_prefetch_pixel_data_without_immediate_flip;
362
+
float maximum_read_bandwidth_with_prefetch_with_immediate_flip;
363
+
float maximum_read_bandwidth_with_prefetch_without_immediate_flip;
364
+
float voltage_level_with_immediate_flip;
365
+
float voltage_level_without_immediate_flip;
366
+
float total_number_of_active_dpp_per_ratio[1 + 1];
367
+
float byte_per_pix_dety;
368
+
float byte_per_pix_detc;
369
+
float read256_bytes_block_height_y;
370
+
float read256_bytes_block_width_y;
371
+
float read256_bytes_block_height_c;
372
+
float read256_bytes_block_width_c;
373
+
float maximum_swath_height_y;
374
+
float maximum_swath_height_c;
375
+
float minimum_swath_height_y;
376
+
float minimum_swath_height_c;
377
+
float swath_width;
378
+
float prefetch_bandwidth[number_of_planes_minus_one + 1];
379
+
float v_init_pre_fill_y[number_of_planes_minus_one + 1];
380
+
float v_init_pre_fill_c[number_of_planes_minus_one + 1];
381
+
float max_num_swath_y[number_of_planes_minus_one + 1];
382
+
float max_num_swath_c[number_of_planes_minus_one + 1];
383
+
float prefill_y[number_of_planes_minus_one + 1];
384
+
float prefill_c[number_of_planes_minus_one + 1];
385
+
float v_startup[number_of_planes_minus_one + 1];
386
+
enum dcn_bw_defs allow_dram_clock_change_during_vblank[number_of_planes_minus_one + 1];
387
+
float allow_dram_self_refresh_during_vblank[number_of_planes_minus_one + 1];
388
+
float v_ratio_prefetch_y[number_of_planes_minus_one + 1];
389
+
float v_ratio_prefetch_c[number_of_planes_minus_one + 1];
390
+
float destination_lines_for_prefetch[number_of_planes_minus_one + 1];
391
+
float destination_lines_to_request_vm_inv_blank[number_of_planes_minus_one + 1];
392
+
float destination_lines_to_request_row_in_vblank[number_of_planes_minus_one + 1];
393
+
float min_ttuv_blank[number_of_planes_minus_one + 1];
394
+
float byte_per_pixel_dety[number_of_planes_minus_one + 1];
395
+
float byte_per_pixel_detc[number_of_planes_minus_one + 1];
396
+
float swath_width_y[number_of_planes_minus_one + 1];
397
+
float lines_in_dety[number_of_planes_minus_one + 1];
398
+
float lines_in_dety_rounded_down_to_swath[number_of_planes_minus_one + 1];
399
+
float lines_in_detc[number_of_planes_minus_one + 1];
400
+
float lines_in_detc_rounded_down_to_swath[number_of_planes_minus_one + 1];
401
+
float full_det_buffering_time_y[number_of_planes_minus_one + 1];
402
+
float full_det_buffering_time_c[number_of_planes_minus_one + 1];
403
+
float active_dram_clock_change_latency_margin[number_of_planes_minus_one + 1];
404
+
float v_blank_dram_clock_change_latency_margin[number_of_planes_minus_one + 1];
405
+
float dcfclk_deep_sleep_per_plane[number_of_planes_minus_one + 1];
406
+
float read_bandwidth_plane_luma[number_of_planes_minus_one + 1];
407
+
float read_bandwidth_plane_chroma[number_of_planes_minus_one + 1];
408
+
float display_pipe_line_delivery_time_luma[number_of_planes_minus_one + 1];
409
+
float display_pipe_line_delivery_time_chroma[number_of_planes_minus_one + 1];
410
+
float display_pipe_line_delivery_time_luma_prefetch[number_of_planes_minus_one + 1];
411
+
float display_pipe_line_delivery_time_chroma_prefetch[number_of_planes_minus_one + 1];
412
+
float pixel_pte_bytes_per_row[number_of_planes_minus_one + 1];
413
+
float meta_pte_bytes_frame[number_of_planes_minus_one + 1];
414
+
float meta_row_byte[number_of_planes_minus_one + 1];
415
+
float prefetch_source_lines_y[number_of_planes_minus_one + 1];
416
+
float prefetch_source_lines_c[number_of_planes_minus_one + 1];
417
+
float pscl_throughput[number_of_planes_minus_one + 1];
418
+
float pscl_throughput_chroma[number_of_planes_minus_one + 1];
419
+
float output_bpphdmi[number_of_planes_minus_one + 1];
420
+
float output_bppdp4_lane_hbr[number_of_planes_minus_one + 1];
421
+
float output_bppdp4_lane_hbr2[number_of_planes_minus_one + 1];
422
+
float output_bppdp4_lane_hbr3[number_of_planes_minus_one + 1];
423
+
float max_vstartup_lines[number_of_planes_minus_one + 1];
424
+
float dispclk_with_ramping;
425
+
float dispclk_without_ramping;
426
+
float dppclk_using_single_dpp_luma;
427
+
float dppclk_using_single_dpp;
428
+
float dppclk_using_single_dpp_chroma;
429
+
enum dcn_bw_defs odm_capable;
430
+
float dispclk;
431
+
float dppclk;
432
+
float return_bandwidth_to_dcn;
433
+
enum dcn_bw_defs dcc_enabled_any_plane;
434
+
float return_bw;
435
+
float critical_compression;
436
+
float total_data_read_bandwidth;
437
+
float total_active_dpp;
438
+
float total_dcc_active_dpp;
439
+
float urgent_round_trip_and_out_of_order_latency;
440
+
float last_pixel_of_line_extra_watermark;
441
+
float data_fabric_line_delivery_time_luma;
442
+
float data_fabric_line_delivery_time_chroma;
443
+
float urgent_extra_latency;
444
+
float urgent_watermark;
445
+
float ptemeta_urgent_watermark;
446
+
float dram_clock_change_watermark;
447
+
float total_active_writeback;
448
+
float writeback_dram_clock_change_watermark;
449
+
float min_full_det_buffering_time;
450
+
float frame_time_for_min_full_det_buffering_time;
451
+
float average_read_bandwidth_gbyte_per_second;
452
+
float part_of_burst_that_fits_in_rob;
453
+
float stutter_burst_time;
454
+
float stutter_efficiency_not_including_vblank;
455
+
float smallest_vblank;
456
+
float v_blank_time;
457
+
float stutter_efficiency;
458
+
float dcf_clk_deep_sleep;
459
+
float stutter_exit_watermark;
460
+
float stutter_enter_plus_exit_watermark;
461
+
float effective_det_plus_lb_lines_luma;
462
+
float urgent_latency_support_us_luma;
463
+
float effective_det_plus_lb_lines_chroma;
464
+
float urgent_latency_support_us_chroma;
465
+
float min_urgent_latency_support_us;
466
+
float non_urgent_latency_tolerance;
467
+
float block_height256_bytes_y;
468
+
float block_height256_bytes_c;
469
+
float meta_request_width_y;
470
+
float meta_surf_width_y;
471
+
float meta_surf_height_y;
472
+
float meta_pte_bytes_frame_y;
473
+
float meta_row_byte_y;
474
+
float macro_tile_size_byte_y;
475
+
float macro_tile_height_y;
476
+
float pixel_pte_req_height_y;
477
+
float pixel_pte_req_width_y;
478
+
float pixel_pte_bytes_per_row_y;
479
+
float meta_request_width_c;
480
+
float meta_surf_width_c;
481
+
float meta_surf_height_c;
482
+
float meta_pte_bytes_frame_c;
483
+
float meta_row_byte_c;
484
+
float macro_tile_size_bytes_c;
485
+
float macro_tile_height_c;
486
+
float pixel_pte_req_height_c;
487
+
float pixel_pte_req_width_c;
488
+
float pixel_pte_bytes_per_row_c;
489
+
float max_partial_swath_y;
490
+
float max_partial_swath_c;
491
+
float t_calc;
492
+
float next_prefetch_mode;
493
+
float v_startup_lines;
494
+
enum dcn_bw_defs planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw;
495
+
enum dcn_bw_defs planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4;
496
+
enum dcn_bw_defs planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2;
497
+
enum dcn_bw_defs v_ratio_prefetch_more_than4;
498
+
enum dcn_bw_defs destination_line_times_for_prefetch_less_than2;
499
+
float prefetch_mode;
500
+
float dstx_after_scaler;
501
+
float dsty_after_scaler;
502
+
float v_update_offset_pix;
503
+
float total_repeater_delay_time;
504
+
float v_update_width_pix;
505
+
float v_ready_offset_pix;
506
+
float t_setup;
507
+
float t_wait;
508
+
float bandwidth_available_for_immediate_flip;
509
+
float tot_immediate_flip_bytes;
510
+
float max_rd_bandwidth;
511
+
float time_for_fetching_meta_pte;
512
+
float time_for_fetching_row_in_vblank;
513
+
float lines_to_request_prefetch_pixel_data;
514
+
float required_prefetch_pix_data_bw;
515
+
enum dcn_bw_defs prefetch_mode_supported;
516
+
float active_dp_ps;
517
+
float lb_latency_hiding_source_lines_y;
518
+
float lb_latency_hiding_source_lines_c;
519
+
float effective_lb_latency_hiding_y;
520
+
float effective_lb_latency_hiding_c;
521
+
float dpp_output_buffer_lines_y;
522
+
float dpp_output_buffer_lines_c;
523
+
float dppopp_buffering_y;
524
+
float max_det_buffering_time_y;
525
+
float active_dram_clock_change_latency_margin_y;
526
+
float dppopp_buffering_c;
527
+
float max_det_buffering_time_c;
528
+
float active_dram_clock_change_latency_margin_c;
529
+
float writeback_dram_clock_change_latency_margin;
530
+
float min_active_dram_clock_change_margin;
531
+
float v_blank_of_min_active_dram_clock_change_margin;
532
+
float second_min_active_dram_clock_change_margin;
533
+
float min_vblank_dram_clock_change_margin;
534
+
float dram_clock_change_margin;
535
+
float dram_clock_change_support;
536
+
float wr_bandwidth;
537
+
float max_used_bw;
538
+
};
539
+
540
+
struct dcn_soc_bounding_box {
541
+
float sr_exit_time; /*us*/
542
+
float sr_enter_plus_exit_time; /*us*/
543
+
float urgent_latency; /*us*/
544
+
float write_back_latency; /*us*/
545
+
float percent_of_ideal_drambw_received_after_urg_latency; /*%*/
546
+
int max_request_size; /*bytes*/
547
+
float dcfclkv_max0p9; /*MHz*/
548
+
float dcfclkv_nom0p8; /*MHz*/
549
+
float dcfclkv_mid0p72; /*MHz*/
550
+
float dcfclkv_min0p65; /*MHz*/
551
+
float max_dispclk_vmax0p9; /*MHz*/
552
+
float max_dispclk_vmid0p72; /*MHz*/
553
+
float max_dispclk_vnom0p8; /*MHz*/
554
+
float max_dispclk_vmin0p65; /*MHz*/
555
+
float max_dppclk_vmax0p9; /*MHz*/
556
+
float max_dppclk_vnom0p8; /*MHz*/
557
+
float max_dppclk_vmid0p72; /*MHz*/
558
+
float max_dppclk_vmin0p65; /*MHz*/
559
+
float socclk; /*MHz*/
560
+
float fabric_and_dram_bandwidth_vmax0p9; /*GB/s*/
561
+
float fabric_and_dram_bandwidth_vnom0p8; /*GB/s*/
562
+
float fabric_and_dram_bandwidth_vmid0p72; /*GB/s*/
563
+
float fabric_and_dram_bandwidth_vmin0p65; /*GB/s*/
564
+
float phyclkv_max0p9; /*MHz*/
565
+
float phyclkv_nom0p8; /*MHz*/
566
+
float phyclkv_mid0p72; /*MHz*/
567
+
float phyclkv_min0p65; /*MHz*/
568
+
float downspreading; /*%*/
569
+
int round_trip_ping_latency_cycles; /*DCFCLK Cycles*/
570
+
int urgent_out_of_order_return_per_channel; /*bytes*/
571
+
int number_of_channels;
572
+
int vmm_page_size; /*bytes*/
573
+
float dram_clock_change_latency; /*us*/
574
+
int return_bus_width; /*bytes*/
575
+
};
576
+
extern const struct dcn_soc_bounding_box dcn10_soc_defaults;
577
+
578
+
struct dcn_ip_params {
579
+
float rob_buffer_size_in_kbyte;
580
+
float det_buffer_size_in_kbyte;
581
+
float dpp_output_buffer_pixels;
582
+
float opp_output_buffer_lines;
583
+
float pixel_chunk_size_in_kbyte;
584
+
enum dcn_bw_defs pte_enable;
585
+
int pte_chunk_size; /*kbytes*/
586
+
int meta_chunk_size; /*kbytes*/
587
+
int writeback_chunk_size; /*kbytes*/
588
+
enum dcn_bw_defs odm_capability;
589
+
enum dcn_bw_defs dsc_capability;
590
+
int line_buffer_size; /*bit*/
591
+
int max_line_buffer_lines;
592
+
enum dcn_bw_defs is_line_buffer_bpp_fixed;
593
+
int line_buffer_fixed_bpp;
594
+
int writeback_luma_buffer_size; /*kbytes*/
595
+
int writeback_chroma_buffer_size; /*kbytes*/
596
+
int max_num_dpp;
597
+
int max_num_writeback;
598
+
int max_dchub_topscl_throughput; /*pixels/dppclk*/
599
+
int max_pscl_tolb_throughput; /*pixels/dppclk*/
600
+
int max_lb_tovscl_throughput; /*pixels/dppclk*/
601
+
int max_vscl_tohscl_throughput; /*pixels/dppclk*/
602
+
float max_hscl_ratio;
603
+
float max_vscl_ratio;
604
+
int max_hscl_taps;
605
+
int max_vscl_taps;
606
+
int pte_buffer_size_in_requests;
607
+
float dispclk_ramping_margin; /*%*/
608
+
float under_scan_factor;
609
+
int max_inter_dcn_tile_repeaters;
610
+
enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
611
+
enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed;
612
+
int dcfclk_cstate_latency;
613
+
};
614
+
extern const struct dcn_ip_params dcn10_ip_defaults;
615
+
616
+
bool dcn_validate_bandwidth(
617
+
const struct core_dc *dc,
618
+
struct validate_context *context);
619
+
620
+
unsigned int dcn_find_dcfclk_suits_all(
621
+
const struct core_dc *dc,
622
+
struct clocks_value *clocks);
623
+
624
+
void dcn_bw_update_from_pplib(struct core_dc *dc);
625
+
void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc);
626
+
void dcn_bw_sync_calcs_and_dml(struct core_dc *dc);
627
+
628
+
#endif /* __DCN_CALCS_H__ */
629
+