tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
s390/lib: Use exrl instead of ex in xor functions
exrl is present in all machines currently supported, therefore prefer
it over ex. This saves one instruction and doesn't need an additional
register to hold the address of the target instruction.
Signed-off-by: Sven Schnelle <svens@linux.ibm.com>
Reviewed-by: Heiko Carstens <hca@linux.ibm.com>
Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
authored by
Sven Schnelle
and committed by
Alexander Gordeev
745600ed
9988df07
+29
-32
+29
-32
arch/s390/lib/xor.c
+29
-32
arch/s390/lib/xor.c
···
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const unsigned long * __restrict p2)
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{
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asm volatile(
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-
" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" srlg 0,%0,8\n"
···
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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"1: exrl %0,2f\n"
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" j 3f\n"
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"2: xc 0(1,%1),0(%2)\n"
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"3:\n"
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: : "d" (bytes), "a" (p1), "a" (p2)
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: "0", "1", "cc", "memory");
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: "0", "cc", "memory");
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}
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static void xor_xc_3(unsigned long bytes, unsigned long * __restrict p1,
···
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const unsigned long * __restrict p3)
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{
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asm volatile(
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" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" jm 4f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
···
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" la %2,256(%2)\n"
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" la %3,256(%3)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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" ex %0,6(1)\n"
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" j 3f\n"
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"1: exrl %0,2f\n"
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" exrl %0,3f\n"
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" j 4f\n"
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"2: xc 0(1,%1),0(%2)\n"
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" xc 0(1,%1),0(%3)\n"
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"3:\n"
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"3: xc 0(1,%1),0(%3)\n"
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"4:\n"
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: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3)
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: : "0", "1", "cc", "memory");
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: : "0", "cc", "memory");
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}
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static void xor_xc_4(unsigned long bytes, unsigned long * __restrict p1,
···
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const unsigned long * __restrict p4)
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{
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asm volatile(
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" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" jm 5f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
···
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" la %3,256(%3)\n"
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" la %4,256(%4)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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" ex %0,6(1)\n"
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" ex %0,12(1)\n"
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" j 3f\n"
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"1: exrl %0,2f\n"
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" exrl %0,3f\n"
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" exrl %0,4f\n"
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" j 5f\n"
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"2: xc 0(1,%1),0(%2)\n"
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" xc 0(1,%1),0(%3)\n"
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" xc 0(1,%1),0(%4)\n"
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"3:\n"
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"3: xc 0(1,%1),0(%3)\n"
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"4: xc 0(1,%1),0(%4)\n"
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"5:\n"
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: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4)
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: : "0", "1", "cc", "memory");
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: : "0", "cc", "memory");
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}
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static void xor_xc_5(unsigned long bytes, unsigned long * __restrict p1,
···
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asm volatile(
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" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" jm 6f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
···
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" la %4,256(%4)\n"
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" la %5,256(%5)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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" ex %0,6(1)\n"
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" ex %0,12(1)\n"
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" ex %0,18(1)\n"
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" j 3f\n"
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"1: exrl %0,2f\n"
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" exrl %0,3f\n"
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" exrl %0,4f\n"
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" exrl %0,5f\n"
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" j 6f\n"
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"2: xc 0(1,%1),0(%2)\n"
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" xc 0(1,%1),0(%3)\n"
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" xc 0(1,%1),0(%4)\n"
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" xc 0(1,%1),0(%5)\n"
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"3:\n"
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"3: xc 0(1,%1),0(%3)\n"
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"4: xc 0(1,%1),0(%4)\n"
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"5: xc 0(1,%1),0(%5)\n"
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"6:\n"
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: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4),
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"+a" (p5)
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: : "0", "1", "cc", "memory");
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: : "0", "cc", "memory");
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}
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struct xor_block_template xor_block_xc = {