Merge tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung into clk-next

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Pull Samsung clk driver changes from Sylwester Nawrocki:

Mostly correction of errors in the exynos5433 SoC
clocks definition, dropping read-only registers
from the suspend/resume register save/restore list
and exposition of two clocks required for the
exynos5433 HDMI subsystem operation.

* tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks
clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition
clk: samsung: exynos5433: Drop RO registers from the save/restore lists
clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocks
clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks
clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock names
clk/samsung: exynos5433: add pclk_decon clock
clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks

Stephen Boyd 10 years ago 7450ca6c 1594d568

+28 -119

2 changed files

expand all

drivers

clk

samsung

clk-exynos5433.c

include

dt-bindings

clock

exynos5433.h

+21 -117

drivers/clk/samsung/clk-exynos5433.c

··· 142 142 MUX_ENABLE_TOP_FSYS1, 143 143 MUX_ENABLE_TOP_PERIC0, 144 144 MUX_ENABLE_TOP_PERIC1, 145 - MUX_STAT_TOP0, 146 - MUX_STAT_TOP1, 147 - MUX_STAT_TOP2, 148 - MUX_STAT_TOP3, 149 - MUX_STAT_TOP4, 150 - MUX_STAT_TOP_MSCL, 151 - MUX_STAT_TOP_CAM1, 152 - MUX_STAT_TOP_FSYS0, 153 - MUX_STAT_TOP_FSYS1, 154 - MUX_STAT_TOP_PERIC0, 155 - MUX_STAT_TOP_PERIC1, 156 145 DIV_TOP0, 157 146 DIV_TOP1, 158 147 DIV_TOP2, ··· 159 170 DIV_TOP_PERIC3, 160 171 DIV_TOP_PERIC4, 161 172 DIV_TOP_PLL_FREQ_DET, 162 - DIV_STAT_TOP0, 163 - DIV_STAT_TOP1, 164 - DIV_STAT_TOP2, 165 - DIV_STAT_TOP3, 166 - DIV_STAT_TOP4, 167 - DIV_STAT_TOP_MSCL, 168 - DIV_STAT_TOP_CAM10, 169 - DIV_STAT_TOP_CAM11, 170 - DIV_STAT_TOP_FSYS0, 171 - DIV_STAT_TOP_FSYS1, 172 - DIV_STAT_TOP_FSYS2, 173 - DIV_STAT_TOP_PERIC0, 174 - DIV_STAT_TOP_PERIC1, 175 - DIV_STAT_TOP_PERIC2, 176 - DIV_STAT_TOP_PERIC3, 177 - DIV_STAT_TOP_PLL_FREQ_DET, 178 173 ENABLE_ACLK_TOP, 179 174 ENABLE_SCLK_TOP, 180 175 ENABLE_SCLK_TOP_MSCL, ··· 463 490 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a", 464 491 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4), 465 492 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b", 466 - "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 12, 4), 493 + "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4), 467 494 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a", 468 - "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 8, 4), 495 + "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4), 469 496 470 497 /* DIV_TOP_FSYS0 */ 471 498 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a", ··· 972 999 MUX_ENABLE_MIF5, 973 1000 MUX_ENABLE_MIF6, 974 1001 MUX_ENABLE_MIF7, 975 - MUX_STAT_MIF0, 976 - MUX_STAT_MIF1, 977 - MUX_STAT_MIF2, 978 - MUX_STAT_MIF3, 979 - MUX_STAT_MIF4, 980 - MUX_STAT_MIF5, 981 - MUX_STAT_MIF6, 982 - MUX_STAT_MIF7, 983 1002 DIV_MIF1, 984 1003 DIV_MIF2, 985 1004 DIV_MIF3, 986 1005 DIV_MIF4, 987 1006 DIV_MIF5, 988 1007 DIV_MIF_PLL_FREQ_DET, 989 - DIV_STAT_MIF1, 990 - DIV_STAT_MIF2, 991 - DIV_STAT_MIF3, 992 - DIV_STAT_MIF4, 993 - DIV_STAT_MIF5, 994 - DIV_STAT_MIF_PLL_FREQ_DET, 995 1008 ENABLE_ACLK_MIF0, 996 1009 ENABLE_ACLK_MIF1, 997 1010 ENABLE_ACLK_MIF2, ··· 1524 1565 1525 1566 static unsigned long peric_clk_regs[] __initdata = { 1526 1567 DIV_PERIC, 1527 - DIV_STAT_PERIC, 1528 1568 ENABLE_ACLK_PERIC, 1529 1569 ENABLE_PCLK_PERIC0, 1530 1570 ENABLE_PCLK_PERIC1, ··· 1970 2012 MUX_ENABLE_FSYS2, 1971 2013 MUX_ENABLE_FSYS3, 1972 2014 MUX_ENABLE_FSYS4, 1973 - MUX_STAT_FSYS0, 1974 - MUX_STAT_FSYS1, 1975 - MUX_STAT_FSYS2, 1976 - MUX_STAT_FSYS3, 1977 - MUX_STAT_FSYS4, 1978 2015 MUX_IGNORE_FSYS2, 1979 2016 MUX_IGNORE_FSYS3, 1980 2017 ENABLE_ACLK_FSYS0, ··· 2315 2362 static unsigned long g2d_clk_regs[] __initdata = { 2316 2363 MUX_SEL_G2D0, 2317 2364 MUX_SEL_ENABLE_G2D0, 2318 - MUX_SEL_STAT_G2D0, 2319 2365 DIV_G2D, 2320 - DIV_STAT_G2D, 2321 2366 DIV_ENABLE_ACLK_G2D, 2322 2367 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 2323 2368 DIV_ENABLE_PCLK_G2D, ··· 2471 2520 MUX_ENABLE_DISP2, 2472 2521 MUX_ENABLE_DISP3, 2473 2522 MUX_ENABLE_DISP4, 2474 - MUX_STAT_DISP0, 2475 - MUX_STAT_DISP1, 2476 - MUX_STAT_DISP2, 2477 - MUX_STAT_DISP3, 2478 - MUX_STAT_DISP4, 2479 2523 MUX_IGNORE_DISP2, 2480 2524 DIV_DISP, 2481 2525 DIV_DISP_PLL_FREQ_DET, 2482 - DIV_STAT_DISP, 2483 - DIV_STAT_DISP_PLL_FREQ_DET, 2484 2526 ENABLE_ACLK_DISP0, 2485 2527 ENABLE_ACLK_DISP1, 2486 2528 ENABLE_PCLK_DISP, ··· 2558 2614 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT, 2559 2615 100000000), 2560 2616 /* PHY clocks from HDMI_PHY */ 2561 - FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000), 2562 - FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000), 2617 + FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", 2618 + NULL, CLK_IS_ROOT, 300000000), 2619 + FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy", 2620 + NULL, CLK_IS_ROOT, 166000000), 2563 2621 }; 2564 2622 2565 2623 static struct samsung_mux_clock disp_mux_clks[] __initdata = { ··· 2766 2820 ENABLE_PCLK_DISP, 2, 0, 0), 2767 2821 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp", 2768 2822 ENABLE_PCLK_DISP, 1, 0, 0), 2823 + GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp", 2824 + ENABLE_PCLK_DISP, 0, 0, 0), 2769 2825 2770 2826 /* ENABLE_SCLK_DISP */ 2771 2827 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8", ··· 2867 2919 MUX_SEL_AUD1, 2868 2920 MUX_ENABLE_AUD0, 2869 2921 MUX_ENABLE_AUD1, 2870 - MUX_STAT_AUD0, 2871 2922 DIV_AUD0, 2872 2923 DIV_AUD1, 2873 - DIV_STAT_AUD0, 2874 - DIV_STAT_AUD1, 2875 2924 ENABLE_ACLK_AUD, 2876 2925 ENABLE_PCLK_AUD, 2877 2926 ENABLE_SCLK_AUD0, ··· 3032 3087 3033 3088 #define CMU_BUS_COMMON_CLK_REGS \ 3034 3089 DIV_BUS, \ 3035 - DIV_STAT_BUS, \ 3036 3090 ENABLE_ACLK_BUS, \ 3037 3091 ENABLE_PCLK_BUS, \ 3038 3092 ENABLE_IP_BUS0, \ ··· 3044 3100 static unsigned long bus2_clk_regs[] __initdata = { 3045 3101 MUX_SEL_BUS2, 3046 3102 MUX_ENABLE_BUS2, 3047 - MUX_STAT_BUS2, 3048 3103 CMU_BUS_COMMON_CLK_REGS, 3049 3104 }; 3050 3105 ··· 3202 3259 G3D_PLL_FREQ_DET, 3203 3260 MUX_SEL_G3D, 3204 3261 MUX_ENABLE_G3D, 3205 - MUX_STAT_G3D, 3206 3262 DIV_G3D, 3207 3263 DIV_G3D_PLL_FREQ_DET, 3208 - DIV_STAT_G3D, 3209 - DIV_STAT_G3D_PLL_FREQ_DET, 3210 3264 ENABLE_ACLK_G3D, 3211 3265 ENABLE_PCLK_G3D, 3212 3266 ENABLE_SCLK_G3D, ··· 3319 3379 static unsigned long gscl_clk_regs[] __initdata = { 3320 3380 MUX_SEL_GSCL, 3321 3381 MUX_ENABLE_GSCL, 3322 - MUX_STAT_GSCL, 3323 3382 ENABLE_ACLK_GSCL, 3324 3383 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 3325 3384 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, ··· 3411 3472 3412 3473 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */ 3413 3474 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user", 3414 - ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3475 + ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), 3415 3476 3416 3477 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */ 3417 3478 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user", 3418 - ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3479 + ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3419 3480 }; 3420 3481 3421 3482 static struct samsung_cmu_info gscl_cmu_info __initdata = { ··· 3482 3543 MUX_ENABLE_APOLLO0, 3483 3544 MUX_ENABLE_APOLLO1, 3484 3545 MUX_ENABLE_APOLLO2, 3485 - MUX_STAT_APOLLO0, 3486 - MUX_STAT_APOLLO1, 3487 - MUX_STAT_APOLLO2, 3488 3546 DIV_APOLLO0, 3489 3547 DIV_APOLLO1, 3490 3548 DIV_APOLLO_PLL_FREQ_DET, 3491 - DIV_STAT_APOLLO0, 3492 - DIV_STAT_APOLLO1, 3493 - DIV_STAT_APOLLO_PLL_FREQ_DET, 3494 3549 ENABLE_ACLK_APOLLO, 3495 3550 ENABLE_PCLK_APOLLO, 3496 3551 ENABLE_SCLK_APOLLO, ··· 3668 3735 MUX_ENABLE_ATLAS0, 3669 3736 MUX_ENABLE_ATLAS1, 3670 3737 MUX_ENABLE_ATLAS2, 3671 - MUX_STAT_ATLAS0, 3672 - MUX_STAT_ATLAS1, 3673 - MUX_STAT_ATLAS2, 3674 3738 DIV_ATLAS0, 3675 3739 DIV_ATLAS1, 3676 3740 DIV_ATLAS_PLL_FREQ_DET, 3677 - DIV_STAT_ATLAS0, 3678 - DIV_STAT_ATLAS1, 3679 - DIV_STAT_ATLAS_PLL_FREQ_DET, 3680 3741 ENABLE_ACLK_ATLAS, 3681 3742 ENABLE_PCLK_ATLAS, 3682 3743 ENABLE_SCLK_ATLAS, ··· 3864 3937 MUX_SEL_MSCL1, 3865 3938 MUX_ENABLE_MSCL0, 3866 3939 MUX_ENABLE_MSCL1, 3867 - MUX_STAT_MSCL0, 3868 - MUX_STAT_MSCL1, 3869 3940 DIV_MSCL, 3870 - DIV_STAT_MSCL, 3871 3941 ENABLE_ACLK_MSCL, 3872 3942 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, 3873 3943 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, ··· 4021 4097 static unsigned long mfc_clk_regs[] __initdata = { 4022 4098 MUX_SEL_MFC, 4023 4099 MUX_ENABLE_MFC, 4024 - MUX_STAT_MFC, 4025 4100 DIV_MFC, 4026 - DIV_STAT_MFC, 4027 4101 ENABLE_ACLK_MFC, 4028 4102 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4029 4103 ENABLE_PCLK_MFC, ··· 4129 4207 static unsigned long hevc_clk_regs[] __initdata = { 4130 4208 MUX_SEL_HEVC, 4131 4209 MUX_ENABLE_HEVC, 4132 - MUX_STAT_HEVC, 4133 4210 DIV_HEVC, 4134 - DIV_STAT_HEVC, 4135 4211 ENABLE_ACLK_HEVC, 4136 4212 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4137 4213 ENABLE_PCLK_HEVC, ··· 4241 4321 static unsigned long isp_clk_regs[] __initdata = { 4242 4322 MUX_SEL_ISP, 4243 4323 MUX_ENABLE_ISP, 4244 - MUX_STAT_ISP, 4245 4324 DIV_ISP, 4246 - DIV_STAT_ISP, 4247 4325 ENABLE_ACLK_ISP0, 4248 4326 ENABLE_ACLK_ISP1, 4249 4327 ENABLE_ACLK_ISP2, ··· 4521 4603 MUX_ENABLE_CAM02, 4522 4604 MUX_ENABLE_CAM03, 4523 4605 MUX_ENABLE_CAM04, 4524 - MUX_STAT_CAM00, 4525 - MUX_STAT_CAM01, 4526 - MUX_STAT_CAM02, 4527 - MUX_STAT_CAM03, 4528 - MUX_STAT_CAM04, 4529 4606 MUX_IGNORE_CAM01, 4530 4607 DIV_CAM00, 4531 4608 DIV_CAM01, 4532 4609 DIV_CAM02, 4533 4610 DIV_CAM03, 4534 - DIV_STAT_CAM00, 4535 - DIV_STAT_CAM01, 4536 - DIV_STAT_CAM02, 4537 - DIV_STAT_CAM03, 4538 4611 ENABLE_ACLK_CAM00, 4539 4612 ENABLE_ACLK_CAM01, 4540 4613 ENABLE_ACLK_CAM02, ··· 4658 4749 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c", 4659 4750 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1), 4660 4751 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b", 4661 - mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 24, 1), 4752 + mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1), 4662 4753 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a", 4663 - mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 24, 1), 4754 + mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1), 4664 4755 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b", 4665 - mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 24, 1), 4756 + mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1), 4666 4757 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a", 4667 - mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 24, 1), 4758 + mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1), 4668 4759 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B, 4669 4760 "mout_sclk_pixelasync_lite_c_init_b", 4670 4761 mout_sclk_pixelasync_lite_c_init_b_p, 4671 - MUX_SEL_CAM04, 24, 1), 4762 + MUX_SEL_CAM04, 4, 1), 4672 4763 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A, 4673 4764 "mout_sclk_pixelasync_lite_c_init_a", 4674 4765 mout_sclk_pixelasync_lite_c_init_a_p, 4675 - MUX_SEL_CAM04, 24, 1), 4766 + MUX_SEL_CAM04, 0, 1), 4676 4767 }; 4677 4768 4678 4769 static struct samsung_div_clock cam0_div_clks[] __initdata = { ··· 4983 5074 MUX_ENABLE_CAM10, 4984 5075 MUX_ENABLE_CAM11, 4985 5076 MUX_ENABLE_CAM12, 4986 - MUX_STAT_CAM10, 4987 - MUX_STAT_CAM11, 4988 - MUX_STAT_CAM12, 4989 5077 MUX_IGNORE_CAM11, 4990 5078 DIV_CAM10, 4991 5079 DIV_CAM11, 4992 - DIV_STAT_CAM10, 4993 - DIV_STAT_CAM11, 4994 5080 ENABLE_ACLK_CAM10, 4995 5081 ENABLE_ACLK_CAM11, 4996 5082 ENABLE_ACLK_CAM12, ··· 5038 5134 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user", 5039 5135 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1), 5040 5136 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user", 5041 - mout_aclk_cam1_400_user_p, MUX_SEL_CAM01, 4, 1), 5137 + mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1), 5042 5138 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user", 5043 - mout_aclk_cam1_552_user_p, MUX_SEL_CAM01, 0, 1), 5139 + mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1), 5044 5140 5045 5141 /* MUX_SEL_CAM11 */ 5046 5142 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER, ··· 5065 5161 5066 5162 static struct samsung_div_clock cam1_div_clks[] __initdata = { 5067 5163 /* DIV_CAM10 */ 5068 - DIV(CLK_DIV_SCLK_ISP_WPWM, "div_sclk_isp_wpwm", 5164 + DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm", 5069 5165 "div_pclk_cam1_83", DIV_CAM10, 16, 2), 5070 5166 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83", 5071 5167 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2), ··· 5259 5355 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0), 5260 5356 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83", 5261 5357 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0), 5262 - GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_wpwm", "div_pclk_cam1_83", 5358 + GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83", 5263 5359 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), 5264 5360 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd", 5265 5361 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), ··· 5292 5388 ENABLE_SCLK_CAM1, 5, 0, 0), 5293 5389 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user", 5294 5390 ENABLE_SCLK_CAM1, 4, 0, 0), 5295 - GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_wpwm", "div_sclk_isp_wpwm", 5391 + GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm", 5296 5392 ENABLE_SCLK_CAM1, 3, 0, 0), 5297 5393 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1", 5298 5394 ENABLE_SCLK_CAM1, 2, 0, 0),

+7 -2

include/dt-bindings/clock/exynos5433.h

··· 765 765 #define CLK_SCLK_RGB_VCLK 109 766 766 #define CLK_SCLK_RGB_TV_VCLK 110 767 767 768 - #define DISP_NR_CLK 111 768 + #define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111 769 + #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112 770 + 771 + #define CLK_PCLK_DECON 113 772 + 773 + #define DISP_NR_CLK 114 769 774 770 775 /* CMU_AUD */ 771 776 #define CLK_MOUT_AUD_PLL_USER 1 ··· 1303 1298 #define CLK_MOUT_ACLK_LITE_C_B 13 1304 1299 #define CLK_MOUT_ACLK_LITE_C_A 14 1305 1300 1306 - #define CLK_DIV_SCLK_ISP_WPWM 15 1301 + #define CLK_DIV_SCLK_ISP_MPWM 15 1307 1302 #define CLK_DIV_PCLK_CAM1_83 16 1308 1303 #define CLK_DIV_PCLK_CAM1_166 17 1309 1304 #define CLK_DIV_PCLK_DBG_CAM1 18