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dt-bindings: PCI: rockchip: Add DesignWare based PCIe Endpoint controller
Document DT bindings for PCIe Endpoint controller found in Rockchip SoCs.
Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-6-0a042d6b0049@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
authored by
Niklas Cassel
and committed by
Krzysztof Wilczyński
743025b0
5f262f67
+109
+14
Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
+14
Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
···
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- const: ref
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interrupts:
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minItems: 5
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items:
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- description:
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Combined system interrupt, which is used to signal the following
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interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
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tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
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nf_err_rx, f_err_rx, radm_qoverflow
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- description:
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eDMA write channel 0 interrupt
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- description:
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eDMA write channel 1 interrupt
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- description:
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eDMA read channel 0 interrupt
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- description:
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eDMA read channel 1 interrupt
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interrupt-names:
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minItems: 5
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items:
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- const: sys
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- const: pmc
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- const: msg
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- const: legacy
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- const: err
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- const: dma0
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- const: dma1
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- const: dma2
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- const: dma3
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num-lanes: true
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Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml
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Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
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maintainers:
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- Niklas Cassel <cassel@kernel.org>
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description: |+
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RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
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PCIe IP and thus inherits all the common properties defined in
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snps,dw-pcie-ep.yaml.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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- $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
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properties:
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compatible:
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enum:
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- rockchip,rk3568-pcie-ep
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- rockchip,rk3588-pcie-ep
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reg:
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items:
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- description: Data Bus Interface (DBI) registers
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- description: Data Bus Interface (DBI) shadow registers
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- description: Rockchip designed configuration registers
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- description: Memory region used to map remote RC address space
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- description: Internal Address Translation Unit (iATU) registers
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: apb
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- const: addr_space
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- const: atu
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required:
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- interrupts
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- interrupt-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/rk3588-power.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie3x4_ep: pcie-ep@fe150000 {
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compatible = "rockchip,rk3588-pcie-ep";
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reg = <0xa 0x40000000 0x0 0x00100000>,
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<0xa 0x40100000 0x0 0x00100000>,
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<0x0 0xfe150000 0x0 0x00010000>,
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<0x9 0x00000000 0x0 0x40000000>,
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<0xa 0x40300000 0x0 0x00100000>;
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reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
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clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
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<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
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<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err",
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"dma0", "dma1", "dma2", "dma3";
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max-link-speed = <3>;
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num-lanes = <4>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
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reset-names = "pwr", "pipe";
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};
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};
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...