tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu: simplify Raven, Raven2, and Picasso handling

Treat them all as Raven rather than adding a new picasso
asic type. This simplifies a lot of code and also handles the
case of rv2 chips with the 0x15d8 pci id. It also fixes dmcu
fw handling for picasso.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher 741deade 23ecdc61

+60 -113
+3 -7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 91 91 "VEGA12", 92 92 "VEGA20", 93 93 "RAVEN", 94 - "PICASSO", 95 94 "LAST", 96 95 }; 97 96 ··· 1336 1337 case CHIP_RAVEN: 1337 1338 if (adev->rev_id >= 8) 1338 1339 chip_name = "raven2"; 1340 + else if (adev->pdev->device == 0x15d8) 1341 + chip_name = "picasso"; 1339 1342 else 1340 1343 chip_name = "raven"; 1341 - break; 1342 - case CHIP_PICASSO: 1343 - chip_name = "picasso"; 1344 1344 break; 1345 1345 } 1346 1346 ··· 1466 1468 case CHIP_VEGA12: 1467 1469 case CHIP_VEGA20: 1468 1470 case CHIP_RAVEN: 1469 - case CHIP_PICASSO: 1470 - if ((adev->asic_type == CHIP_RAVEN) || (adev->asic_type == CHIP_PICASSO)) 1471 + if (adev->asic_type == CHIP_RAVEN) 1471 1472 adev->family = AMDGPU_FAMILY_RV; 1472 1473 else 1473 1474 adev->family = AMDGPU_FAMILY_AI; ··· 2180 2183 case CHIP_VEGA20: 2181 2184 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 2182 2185 case CHIP_RAVEN: 2183 - case CHIP_PICASSO: 2184 2186 #endif 2185 2187 return amdgpu_dc != 0; 2186 2188 #endif
+1 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 874 874 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 875 875 /* Raven */ 876 876 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 877 - /* Picasso */ 878 - {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PICASSO|AMD_IS_APU}, 877 + {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 879 878 880 879 {0, 0, 0} 881 880 };
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
··· 56 56 psp_v3_1_set_psp_funcs(psp); 57 57 break; 58 58 case CHIP_RAVEN: 59 - case CHIP_PICASSO: 60 59 psp_v10_0_set_psp_funcs(psp); 61 60 break; 62 61 case CHIP_VEGA20:
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
··· 303 303 return AMDGPU_FW_LOAD_SMU; 304 304 case CHIP_VEGA10: 305 305 case CHIP_RAVEN: 306 - case CHIP_PICASSO: 307 306 case CHIP_VEGA12: 308 307 case CHIP_VEGA20: 309 308 if (!load_type)
+3 -4
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
··· 63 63 64 64 switch (adev->asic_type) { 65 65 case CHIP_RAVEN: 66 - if (adev->rev_id >= 8) 66 + if (adev->rev_id >= 8) 67 67 fw_name = FIRMWARE_RAVEN2; 68 + else if (adev->pdev->device == 0x15d8) 69 + fw_name = FIRMWARE_PICASSO; 68 70 else 69 71 fw_name = FIRMWARE_RAVEN; 70 - break; 71 - case CHIP_PICASSO: 72 - fw_name = FIRMWARE_PICASSO; 73 72 break; 74 73 default: 75 74 return -EINVAL;
+2 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
··· 2981 2981 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & 2982 2982 AMDGPU_VM_USE_CPU_FOR_COMPUTE); 2983 2983 2984 - if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) 2984 + if (adev->asic_type == CHIP_RAVEN) 2985 2985 vm->pte_support_ats = true; 2986 2986 } else { 2987 2987 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & ··· 3073 3073 */ 3074 3074 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid) 3075 3075 { 3076 - bool pte_support_ats = (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO); 3076 + bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); 3077 3077 int r; 3078 3078 3079 3079 r = amdgpu_bo_reserve(vm->root.base.bo, true);
+5 -27
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 277 277 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 278 278 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 279 279 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 280 - #define PICASSO_GB_ADDR_CONFIG_GOLDEN 0x24000042 281 280 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 282 281 283 282 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); ··· 327 328 soc15_program_register_sequence(adev, 328 329 golden_settings_gc_9_1_rv1, 329 330 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 330 - break; 331 - case CHIP_PICASSO: 332 - soc15_program_register_sequence(adev, 333 - golden_settings_gc_9_1, 334 - ARRAY_SIZE(golden_settings_gc_9_1)); 335 - soc15_program_register_sequence(adev, 336 - golden_settings_gc_9_1_rv1, 337 - ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 338 331 break; 339 332 default: 340 333 break; ··· 608 617 case CHIP_RAVEN: 609 618 if (adev->rev_id >= 8) 610 619 chip_name = "raven2"; 620 + else if (adev->pdev->device == 0x15d8) 621 + chip_name = "picasso"; 611 622 else 612 623 chip_name = "raven"; 613 - break; 614 - case CHIP_PICASSO: 615 - chip_name = "picasso"; 616 624 break; 617 625 default: 618 626 BUG(); ··· 1066 1076 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1067 1077 } 1068 1078 1069 - if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) { 1079 + if (adev->asic_type == CHIP_RAVEN) { 1070 1080 /* TODO: double check the cp_table_size for RV */ 1071 1081 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1072 1082 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, ··· 1317 1327 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 1318 1328 else 1319 1329 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1320 - break; 1321 - case CHIP_PICASSO: 1322 - adev->gfx.config.max_hw_contexts = 8; 1323 - adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1324 - adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1325 - adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1326 - adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1327 - gb_addr_config = PICASSO_GB_ADDR_CONFIG_GOLDEN; 1328 1330 break; 1329 1331 default: 1330 1332 BUG(); ··· 1596 1614 case CHIP_VEGA12: 1597 1615 case CHIP_VEGA20: 1598 1616 case CHIP_RAVEN: 1599 - case CHIP_PICASSO: 1600 1617 adev->gfx.mec.num_mec = 2; 1601 1618 break; 1602 1619 default: ··· 1757 1776 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 1758 1777 &adev->gfx.rlc.clear_state_gpu_addr, 1759 1778 (void **)&adev->gfx.rlc.cs_ptr); 1760 - if ((adev->asic_type == CHIP_RAVEN) || (adev->asic_type == CHIP_PICASSO)) { 1779 + if (adev->asic_type == CHIP_RAVEN) { 1761 1780 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 1762 1781 &adev->gfx.rlc.cp_table_gpu_addr, 1763 1782 (void **)&adev->gfx.rlc.cp_table_ptr); ··· 2423 2442 return r; 2424 2443 } 2425 2444 2426 - if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) { 2445 + if (adev->asic_type == CHIP_RAVEN) { 2427 2446 if (amdgpu_lbpw != 0) 2428 2447 gfx_v9_0_enable_lbpw(adev, true); 2429 2448 else ··· 3827 3846 3828 3847 switch (adev->asic_type) { 3829 3848 case CHIP_RAVEN: 3830 - case CHIP_PICASSO: 3831 3849 if (!enable) { 3832 3850 amdgpu_gfx_off_ctrl(adev, false); 3833 3851 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); ··· 3881 3901 case CHIP_VEGA12: 3882 3902 case CHIP_VEGA20: 3883 3903 case CHIP_RAVEN: 3884 - case CHIP_PICASSO: 3885 3904 gfx_v9_0_update_gfx_clock_gating(adev, 3886 3905 state == AMD_CG_STATE_GATE ? true : false); 3887 3906 break; ··· 4890 4911 case CHIP_VEGA12: 4891 4912 case CHIP_VEGA20: 4892 4913 case CHIP_RAVEN: 4893 - case CHIP_PICASSO: 4894 4914 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 4895 4915 break; 4896 4916 default:
-4
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
··· 846 846 adev->gmc.gart_size = 512ULL << 20; 847 847 break; 848 848 case CHIP_RAVEN: /* DCE SG support */ 849 - case CHIP_PICASSO: /* DCE SG support */ 850 849 adev->gmc.gart_size = 1024ULL << 20; 851 850 break; 852 851 } ··· 934 935 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); 935 936 switch (adev->asic_type) { 936 937 case CHIP_RAVEN: 937 - case CHIP_PICASSO: 938 938 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 939 939 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 940 940 } else { ··· 1060 1062 case CHIP_VEGA12: 1061 1063 break; 1062 1064 case CHIP_RAVEN: 1063 - case CHIP_PICASSO: 1064 1065 soc15_program_register_sequence(adev, 1065 1066 golden_settings_athub_1_0_0, 1066 1067 ARRAY_SIZE(golden_settings_athub_1_0_0)); ··· 1094 1097 1095 1098 switch (adev->asic_type) { 1096 1099 case CHIP_RAVEN: 1097 - case CHIP_PICASSO: 1098 1100 mmhub_v1_0_update_power_gating(adev, true); 1099 1101 break; 1100 1102 default:
+5 -6
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
··· 412 412 413 413 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 414 414 415 - if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) { 415 + if (adev->asic_type != CHIP_RAVEN) { 416 416 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 417 417 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); 418 418 } else ··· 428 428 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 429 429 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 430 430 431 - if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) 431 + if (adev->asic_type != CHIP_RAVEN) 432 432 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 433 433 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 434 434 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | ··· 445 445 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 446 446 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 447 447 448 - if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) 448 + if (adev->asic_type != CHIP_RAVEN) 449 449 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 450 450 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 451 451 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | ··· 458 458 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 459 459 460 460 if (def1 != data1) { 461 - if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) 461 + if (adev->asic_type != CHIP_RAVEN) 462 462 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 463 463 else 464 464 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); 465 465 } 466 466 467 - if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO && def2 != data2) 467 + if (adev->asic_type != CHIP_RAVEN && def2 != data2) 468 468 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); 469 469 } 470 470 ··· 528 528 case CHIP_VEGA12: 529 529 case CHIP_VEGA20: 530 530 case CHIP_RAVEN: 531 - case CHIP_PICASSO: 532 531 mmhub_v1_0_update_medium_grain_clock_gating(adev, 533 532 state == AMD_CG_STATE_GATE ? true : false); 534 533 athub_update_medium_grain_clock_gating(adev,
+2 -3
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
··· 121 121 case CHIP_RAVEN: 122 122 if (adev->rev_id >= 0x8) 123 123 chip_name = "raven2"; 124 + else if (adev->pdev->device == 0x15d8) 125 + chip_name = "picasso"; 124 126 else 125 127 chip_name = "raven"; 126 - break; 127 - case CHIP_PICASSO: 128 - chip_name = "picasso"; 129 128 break; 130 129 default: BUG(); 131 130 }
+3 -8
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
··· 229 229 ARRAY_SIZE(golden_settings_sdma1_4_2)); 230 230 break; 231 231 case CHIP_RAVEN: 232 - case CHIP_PICASSO: 233 232 soc15_program_register_sequence(adev, 234 233 golden_settings_sdma_4_1, 235 234 ARRAY_SIZE(golden_settings_sdma_4_1)); ··· 282 283 case CHIP_RAVEN: 283 284 if (adev->rev_id >= 8) 284 285 chip_name = "raven2"; 286 + else if (adev->pdev->device == 0x15d8) 287 + chip_name = "picasso"; 285 288 else 286 289 chip_name = "raven"; 287 - break; 288 - case CHIP_PICASSO: 289 - chip_name = "picasso"; 290 290 break; 291 291 default: 292 292 BUG(); ··· 867 869 868 870 switch (adev->asic_type) { 869 871 case CHIP_RAVEN: 870 - case CHIP_PICASSO: 871 872 sdma_v4_1_init_power_gating(adev); 872 873 sdma_v4_1_update_power_gating(adev, true); 873 874 break; ··· 1274 1277 { 1275 1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1276 1279 1277 - if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) 1280 + if (adev->asic_type == CHIP_RAVEN) 1278 1281 adev->sdma.num_instances = 1; 1279 1282 else 1280 1283 adev->sdma.num_instances = 2; ··· 1617 1620 case CHIP_VEGA12: 1618 1621 case CHIP_VEGA20: 1619 1622 case CHIP_RAVEN: 1620 - case CHIP_PICASSO: 1621 1623 sdma_v4_0_update_medium_grain_clock_gating(adev, 1622 1624 state == AMD_CG_STATE_GATE ? true : false); 1623 1625 sdma_v4_0_update_medium_grain_light_sleep(adev, ··· 1635 1639 1636 1640 switch (adev->asic_type) { 1637 1641 case CHIP_RAVEN: 1638 - case CHIP_PICASSO: 1639 1642 sdma_v4_1_update_power_gating(adev, 1640 1643 state == AMD_PG_STATE_GATE ? true : false); 1641 1644 break;
+30 -36
drivers/gpu/drm/amd/amdgpu/soc15.c
··· 491 491 case CHIP_VEGA10: 492 492 case CHIP_VEGA12: 493 493 case CHIP_RAVEN: 494 - case CHIP_PICASSO: 495 494 vega10_reg_base_init(adev); 496 495 break; 497 496 case CHIP_VEGA20: ··· 545 546 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 546 547 break; 547 548 case CHIP_RAVEN: 548 - case CHIP_PICASSO: 549 549 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 550 550 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 551 551 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); ··· 696 698 break; 697 699 case CHIP_RAVEN: 698 700 if (adev->rev_id >= 0x8) 701 + adev->external_rev_id = adev->rev_id + 0x81; 702 + else if (adev->pdev->device == 0x15d8) 703 + adev->external_rev_id = adev->rev_id + 0x41; 704 + else 705 + adev->external_rev_id = 0x1; 706 + 707 + if (adev->rev_id >= 0x8) { 699 708 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 700 709 AMD_CG_SUPPORT_GFX_MGLS | 701 710 AMD_CG_SUPPORT_GFX_CP_LS | ··· 718 713 AMD_CG_SUPPORT_SDMA_MGCG | 719 714 AMD_CG_SUPPORT_SDMA_LS | 720 715 AMD_CG_SUPPORT_VCN_MGCG; 721 - else 716 + 717 + adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 718 + } else if (adev->pdev->device == 0x15d8) { 719 + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS | 720 + AMD_CG_SUPPORT_GFX_CP_LS | 721 + AMD_CG_SUPPORT_GFX_3D_CGCG | 722 + AMD_CG_SUPPORT_GFX_3D_CGLS | 723 + AMD_CG_SUPPORT_GFX_CGCG | 724 + AMD_CG_SUPPORT_GFX_CGLS | 725 + AMD_CG_SUPPORT_BIF_LS | 726 + AMD_CG_SUPPORT_HDP_LS | 727 + AMD_CG_SUPPORT_ROM_MGCG | 728 + AMD_CG_SUPPORT_MC_MGCG | 729 + AMD_CG_SUPPORT_MC_LS | 730 + AMD_CG_SUPPORT_SDMA_MGCG | 731 + AMD_CG_SUPPORT_SDMA_LS; 732 + 733 + adev->pg_flags = AMD_PG_SUPPORT_SDMA | 734 + AMD_PG_SUPPORT_MMHUB | 735 + AMD_PG_SUPPORT_VCN; 736 + } else { 722 737 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 723 738 AMD_CG_SUPPORT_GFX_MGLS | 724 739 AMD_CG_SUPPORT_GFX_RLC_LS | ··· 760 735 AMD_CG_SUPPORT_SDMA_LS | 761 736 AMD_CG_SUPPORT_VCN_MGCG; 762 737 763 - adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 738 + adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 739 + } 764 740 765 741 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) 766 742 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 767 743 AMD_PG_SUPPORT_CP | 768 744 AMD_PG_SUPPORT_RLC_SMU_HS; 769 - 770 - if (adev->rev_id >= 0x8) 771 - adev->external_rev_id = adev->rev_id + 0x81; 772 - else 773 - adev->external_rev_id = 0x1; 774 - break; 775 - case CHIP_PICASSO: 776 - adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS | 777 - AMD_CG_SUPPORT_GFX_CP_LS | 778 - AMD_CG_SUPPORT_GFX_3D_CGCG | 779 - AMD_CG_SUPPORT_GFX_3D_CGLS | 780 - AMD_CG_SUPPORT_GFX_CGCG | 781 - AMD_CG_SUPPORT_GFX_CGLS | 782 - AMD_CG_SUPPORT_BIF_LS | 783 - AMD_CG_SUPPORT_HDP_LS | 784 - AMD_CG_SUPPORT_ROM_MGCG | 785 - AMD_CG_SUPPORT_MC_MGCG | 786 - AMD_CG_SUPPORT_MC_LS | 787 - AMD_CG_SUPPORT_SDMA_MGCG | 788 - AMD_CG_SUPPORT_SDMA_LS; 789 - 790 - adev->pg_flags = AMD_PG_SUPPORT_SDMA | 791 - AMD_PG_SUPPORT_MMHUB | 792 - AMD_PG_SUPPORT_VCN; 793 - 794 - if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) 795 - adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 796 - AMD_PG_SUPPORT_CP | 797 - AMD_PG_SUPPORT_RLC_SMU_HS; 798 - 799 - adev->external_rev_id = adev->rev_id + 0x41; 800 745 break; 801 746 default: 802 747 /* FIXME: not supported yet */ ··· 968 973 state == AMD_CG_STATE_GATE ? true : false); 969 974 break; 970 975 case CHIP_RAVEN: 971 - case CHIP_PICASSO: 972 976 adev->nbio_funcs->update_medium_grain_clock_gating(adev, 973 977 state == AMD_CG_STATE_GATE ? true : false); 974 978 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
+2 -6
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 1215 1215 if (adev->asic_type == CHIP_VEGA10 || 1216 1216 adev->asic_type == CHIP_VEGA12 || 1217 1217 adev->asic_type == CHIP_VEGA20 || 1218 - adev->asic_type == CHIP_RAVEN || 1219 - adev->asic_type == CHIP_PICASSO) 1218 + adev->asic_type == CHIP_RAVEN) 1220 1219 client_id = SOC15_IH_CLIENTID_DCE; 1221 1220 1222 1221 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; ··· 1634 1635 break; 1635 1636 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1636 1637 case CHIP_RAVEN: 1637 - case CHIP_PICASSO: 1638 1638 if (dcn10_register_irq_handlers(dm->adev)) { 1639 1639 DRM_ERROR("DM: Failed to initialize IRQ\n"); 1640 1640 goto fail; ··· 1860 1862 break; 1861 1863 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1862 1864 case CHIP_RAVEN: 1863 - case CHIP_PICASSO: 1864 1865 adev->mode_info.num_crtc = 4; 1865 1866 adev->mode_info.num_hpd = 4; 1866 1867 adev->mode_info.num_dig = 4; ··· 2108 2111 if (adev->asic_type == CHIP_VEGA10 || 2109 2112 adev->asic_type == CHIP_VEGA12 || 2110 2113 adev->asic_type == CHIP_VEGA20 || 2111 - adev->asic_type == CHIP_RAVEN || 2112 - adev->asic_type == CHIP_PICASSO) { 2114 + adev->asic_type == CHIP_RAVEN) { 2113 2115 /* Fill GFX9 params */ 2114 2116 plane_state->tiling_info.gfx9.num_pipes = 2115 2117 adev->gfx.config.gb_addr_config_fields.num_pipes;
-1
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
··· 171 171 case AMDGPU_FAMILY_RV: 172 172 switch (hwmgr->chip_id) { 173 173 case CHIP_RAVEN: 174 - case CHIP_PICASSO: 175 174 hwmgr->od_enabled = false; 176 175 hwmgr->smumgr_funcs = &smu10_smu_funcs; 177 176 smu10_init_function_pointers(hwmgr);
+4 -4
drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
··· 832 832 uint16_t size; 833 833 834 834 if (!table_addr) { 835 - if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) { 835 + if (hwmgr->chip_id == CHIP_RAVEN) { 836 836 table_addr = &soft_dummy_pp_table[0]; 837 837 hwmgr->soft_pp_table = &soft_dummy_pp_table[0]; 838 838 hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table); ··· 1055 1055 hwmgr->platform_descriptor.maxOverdriveVDDC = 0; 1056 1056 hwmgr->platform_descriptor.overdriveVDDCStep = 0; 1057 1057 1058 - if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) 1058 + if (hwmgr->chip_id == CHIP_RAVEN) 1059 1059 return 0; 1060 1060 1061 1061 /* We assume here that fw_info is unchanged if this call fails.*/ ··· 1595 1595 int result; 1596 1596 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table; 1597 1597 1598 - if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) 1598 + if (hwmgr->chip_id == CHIP_RAVEN) 1599 1599 return 0; 1600 1600 1601 1601 hwmgr->need_pp_table_upload = true; ··· 1644 1644 1645 1645 static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) 1646 1646 { 1647 - if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) 1647 + if (hwmgr->chip_id == CHIP_RAVEN) 1648 1648 return 0; 1649 1649 1650 1650 kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
-1
include/drm/amd_asic_type.h
··· 49 49 CHIP_VEGA12, 50 50 CHIP_VEGA20, 51 51 CHIP_RAVEN, 52 - CHIP_PICASSO, 53 52 CHIP_LAST, 54 53 }; 55 54