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dt-bindings: add SMP enable-method for Broadcom NSP
Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
Northstar Plus CPU to the 32-bit ARM CPU device tree binding
documentation file and create a new binding documentation for
Northstar Plus CPU.
Signed-off-by: Kapil Hali <kapilh@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
authored by
Kapil Hali
and committed by
Florian Fainelli
7418111f
ea2d8975
+40
+39
Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
+39
Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
···
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Broadcom Northstar Plus SoC CPU Enable Method
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---------------------------------------------
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This binding defines the enable method used for starting secondary
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CPU in the following Broadcom SoCs:
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BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
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The enable method is specified by defining the following required
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properties in the corresponding secondary "cpu" device tree node:
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- enable-method = "brcm,bcm-nsp-smp";
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- secondary-boot-reg = <...>;
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The secondary-boot-reg property is a u32 value that specifies the
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physical address of the register which should hold the common
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entry point for a secondary CPU. This entry is cpu node specific
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and should be added per cpu. E.g., in case of NSP (BCM58625) which
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is a dual core CPU SoC, this entry should be added to cpu1 node.
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Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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enable-method = "brcm,bcm-nsp-smp";
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secondary-boot-reg = <0xffff042c>;
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reg = <1>;
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};
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};