Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

dt-bindings: power: Add MT8195 power domains

Add power domains dt-bindings for MT8195.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220130012104.5292-2-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

authored by

Chun-Jie Chen and committed by
Matthias Brugger
73c022e1 e783362e

+48
+2
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
··· 27 27 - mediatek,mt8173-power-controller 28 28 - mediatek,mt8183-power-controller 29 29 - mediatek,mt8192-power-controller 30 + - mediatek,mt8195-power-controller 30 31 31 32 '#power-domain-cells': 32 33 const: 1 ··· 65 64 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. 66 65 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. 67 66 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. 67 + "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. 68 68 maxItems: 1 69 69 70 70 clocks:
+46
include/dt-bindings/power/mt8195-power.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 + /* 3 + * Copyright (c) 2021 MediaTek Inc. 4 + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_POWER_MT8195_POWER_H 8 + #define _DT_BINDINGS_POWER_MT8195_POWER_H 9 + 10 + #define MT8195_POWER_DOMAIN_PCIE_MAC_P0 0 11 + #define MT8195_POWER_DOMAIN_PCIE_MAC_P1 1 12 + #define MT8195_POWER_DOMAIN_PCIE_PHY 2 13 + #define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 3 14 + #define MT8195_POWER_DOMAIN_CSI_RX_TOP 4 15 + #define MT8195_POWER_DOMAIN_ETHER 5 16 + #define MT8195_POWER_DOMAIN_ADSP 6 17 + #define MT8195_POWER_DOMAIN_AUDIO 7 18 + #define MT8195_POWER_DOMAIN_MFG0 8 19 + #define MT8195_POWER_DOMAIN_MFG1 9 20 + #define MT8195_POWER_DOMAIN_MFG2 10 21 + #define MT8195_POWER_DOMAIN_MFG3 11 22 + #define MT8195_POWER_DOMAIN_MFG4 12 23 + #define MT8195_POWER_DOMAIN_MFG5 13 24 + #define MT8195_POWER_DOMAIN_MFG6 14 25 + #define MT8195_POWER_DOMAIN_VPPSYS0 15 26 + #define MT8195_POWER_DOMAIN_VDOSYS0 16 27 + #define MT8195_POWER_DOMAIN_VPPSYS1 17 28 + #define MT8195_POWER_DOMAIN_VDOSYS1 18 29 + #define MT8195_POWER_DOMAIN_DP_TX 19 30 + #define MT8195_POWER_DOMAIN_EPD_TX 20 31 + #define MT8195_POWER_DOMAIN_HDMI_TX 21 32 + #define MT8195_POWER_DOMAIN_WPESYS 22 33 + #define MT8195_POWER_DOMAIN_VDEC0 23 34 + #define MT8195_POWER_DOMAIN_VDEC1 24 35 + #define MT8195_POWER_DOMAIN_VDEC2 25 36 + #define MT8195_POWER_DOMAIN_VENC 26 37 + #define MT8195_POWER_DOMAIN_VENC_CORE1 27 38 + #define MT8195_POWER_DOMAIN_IMG 28 39 + #define MT8195_POWER_DOMAIN_DIP 29 40 + #define MT8195_POWER_DOMAIN_IPE 30 41 + #define MT8195_POWER_DOMAIN_CAM 31 42 + #define MT8195_POWER_DOMAIN_CAM_RAWA 32 43 + #define MT8195_POWER_DOMAIN_CAM_RAWB 33 44 + #define MT8195_POWER_DOMAIN_CAM_MRAW 34 45 + 46 + #endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */