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tulip: dmfe: Fix global namespace pollution of phy accessors.

The dmfe driver has "phy_read()" and "phy_write()" functions, which
we need to rename because the generic phy layer is about to export
generic interfaces with the same name.

Signed-off-by: David S. Miller <davem@davemloft.net>

David S. Miller 73852b2b c2c0e8b2

+76 -76
+76 -76
drivers/net/ethernet/dec/tulip/dmfe.c
··· 328 328 static void update_cr6(u32, void __iomem *); 329 329 static void send_filter_frame(struct DEVICE *); 330 330 static void dm9132_id_table(struct DEVICE *); 331 - static u16 phy_read(void __iomem *, u8, u8, u32); 332 - static void phy_write(void __iomem *, u8, u8, u16, u32); 333 - static void phy_write_1bit(void __iomem *, u32); 334 - static u16 phy_read_1bit(void __iomem *); 331 + static u16 dmfe_phy_read(void __iomem *, u8, u8, u32); 332 + static void dmfe_phy_write(void __iomem *, u8, u8, u16, u32); 333 + static void dmfe_phy_write_1bit(void __iomem *, u32); 334 + static u16 dmfe_phy_read_1bit(void __iomem *); 335 335 static u8 dmfe_sense_speed(struct dmfe_board_info *); 336 336 static void dmfe_process_mode(struct dmfe_board_info *); 337 337 static void dmfe_timer(unsigned long); ··· 770 770 /* Reset & stop DM910X board */ 771 771 dw32(DCR0, DM910X_RESET); 772 772 udelay(100); 773 - phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); 773 + dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); 774 774 775 775 /* free interrupt */ 776 776 free_irq(db->pdev->irq, dev); ··· 1154 1154 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) { 1155 1155 db->cr6_data &= ~0x40000; 1156 1156 update_cr6(db->cr6_data, ioaddr); 1157 - phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); 1157 + dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); 1158 1158 db->cr6_data |= 0x40000; 1159 1159 update_cr6(db->cr6_data, ioaddr); 1160 1160 db->timer.expires = DMFE_TIMER_WUT + HZ * 2; ··· 1230 1230 */ 1231 1231 1232 1232 /* need a dummy read because of PHY's register latch*/ 1233 - phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id); 1234 - link_ok_phy = (phy_read (db->ioaddr, 1235 - db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0; 1233 + dmfe_phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id); 1234 + link_ok_phy = (dmfe_phy_read (db->ioaddr, 1235 + db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0; 1236 1236 1237 1237 if (link_ok_phy != link_ok) { 1238 1238 DMFE_DBUG (0, "PHY and chip report different link status", 0); ··· 1247 1247 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */ 1248 1248 /* AUTO or force 1M Homerun/Longrun don't need */ 1249 1249 if ( !(db->media_mode & 0x38) ) 1250 - phy_write(db->ioaddr, db->phy_addr, 1251 - 0, 0x1000, db->chip_id); 1250 + dmfe_phy_write(db->ioaddr, db->phy_addr, 1251 + 0, 0x1000, db->chip_id); 1252 1252 1253 1253 /* AUTO mode, if INT phyxcer link failed, select EXT device */ 1254 1254 if (db->media_mode & DMFE_AUTO) { ··· 1649 1649 /* CR6 bit18=0, select 10/100M */ 1650 1650 update_cr6(db->cr6_data & ~0x40000, ioaddr); 1651 1651 1652 - phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); 1653 - phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); 1652 + phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); 1653 + phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); 1654 1654 1655 1655 if ( (phy_mode & 0x24) == 0x24 ) { 1656 1656 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */ 1657 - phy_mode = phy_read(db->ioaddr, 1658 - db->phy_addr, 7, db->chip_id) & 0xf000; 1657 + phy_mode = dmfe_phy_read(db->ioaddr, 1658 + db->phy_addr, 7, db->chip_id) & 0xf000; 1659 1659 else /* DM9102/DM9102A */ 1660 - phy_mode = phy_read(db->ioaddr, 1661 - db->phy_addr, 17, db->chip_id) & 0xf000; 1660 + phy_mode = dmfe_phy_read(db->ioaddr, 1661 + db->phy_addr, 17, db->chip_id) & 0xf000; 1662 1662 switch (phy_mode) { 1663 1663 case 0x1000: db->op_mode = DMFE_10MHF; break; 1664 1664 case 0x2000: db->op_mode = DMFE_10MFD; break; ··· 1695 1695 1696 1696 /* DM9009 Chip: Phyxcer reg18 bit12=0 */ 1697 1697 if (db->chip_id == PCI_DM9009_ID) { 1698 - phy_reg = phy_read(db->ioaddr, 1699 - db->phy_addr, 18, db->chip_id) & ~0x1000; 1698 + phy_reg = dmfe_phy_read(db->ioaddr, 1699 + db->phy_addr, 18, db->chip_id) & ~0x1000; 1700 1700 1701 - phy_write(db->ioaddr, 1702 - db->phy_addr, 18, phy_reg, db->chip_id); 1701 + dmfe_phy_write(db->ioaddr, 1702 + db->phy_addr, 18, phy_reg, db->chip_id); 1703 1703 } 1704 1704 1705 1705 /* Phyxcer capability setting */ 1706 - phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; 1706 + phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; 1707 1707 1708 1708 if (db->media_mode & DMFE_AUTO) { 1709 1709 /* AUTO Mode */ ··· 1724 1724 phy_reg|=db->PHY_reg4; 1725 1725 db->media_mode|=DMFE_AUTO; 1726 1726 } 1727 - phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); 1727 + dmfe_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); 1728 1728 1729 1729 /* Restart Auto-Negotiation */ 1730 1730 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) ) 1731 - phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id); 1731 + dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id); 1732 1732 if ( !db->chip_type ) 1733 - phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); 1733 + dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); 1734 1734 } 1735 1735 1736 1736 ··· 1762 1762 /* 10/100M phyxcer force mode need */ 1763 1763 if ( !(db->media_mode & 0x18)) { 1764 1764 /* Forece Mode */ 1765 - phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id); 1765 + phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id); 1766 1766 if ( !(phy_reg & 0x1) ) { 1767 1767 /* parter without N-Way capability */ 1768 1768 phy_reg = 0x0; ··· 1772 1772 case DMFE_100MHF: phy_reg = 0x2000; break; 1773 1773 case DMFE_100MFD: phy_reg = 0x2100; break; 1774 1774 } 1775 - phy_write(db->ioaddr, 1776 - db->phy_addr, 0, phy_reg, db->chip_id); 1775 + dmfe_phy_write(db->ioaddr, 1776 + db->phy_addr, 0, phy_reg, db->chip_id); 1777 1777 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) ) 1778 1778 mdelay(20); 1779 - phy_write(db->ioaddr, 1780 - db->phy_addr, 0, phy_reg, db->chip_id); 1779 + dmfe_phy_write(db->ioaddr, 1780 + db->phy_addr, 0, phy_reg, db->chip_id); 1781 1781 } 1782 1782 } 1783 1783 } ··· 1787 1787 * Write a word to Phy register 1788 1788 */ 1789 1789 1790 - static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset, 1791 - u16 phy_data, u32 chip_id) 1790 + static void dmfe_phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset, 1791 + u16 phy_data, u32 chip_id) 1792 1792 { 1793 1793 u16 i; 1794 1794 ··· 1799 1799 1800 1800 /* Send 33 synchronization clock to Phy controller */ 1801 1801 for (i = 0; i < 35; i++) 1802 - phy_write_1bit(ioaddr, PHY_DATA_1); 1802 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_1); 1803 1803 1804 1804 /* Send start command(01) to Phy */ 1805 - phy_write_1bit(ioaddr, PHY_DATA_0); 1806 - phy_write_1bit(ioaddr, PHY_DATA_1); 1805 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_0); 1806 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_1); 1807 1807 1808 1808 /* Send write command(01) to Phy */ 1809 - phy_write_1bit(ioaddr, PHY_DATA_0); 1810 - phy_write_1bit(ioaddr, PHY_DATA_1); 1809 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_0); 1810 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_1); 1811 1811 1812 1812 /* Send Phy address */ 1813 1813 for (i = 0x10; i > 0; i = i >> 1) 1814 - phy_write_1bit(ioaddr, 1815 - phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); 1814 + dmfe_phy_write_1bit(ioaddr, 1815 + phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); 1816 1816 1817 1817 /* Send register address */ 1818 1818 for (i = 0x10; i > 0; i = i >> 1) 1819 - phy_write_1bit(ioaddr, 1820 - offset & i ? PHY_DATA_1 : PHY_DATA_0); 1819 + dmfe_phy_write_1bit(ioaddr, 1820 + offset & i ? PHY_DATA_1 : PHY_DATA_0); 1821 1821 1822 1822 /* written trasnition */ 1823 - phy_write_1bit(ioaddr, PHY_DATA_1); 1824 - phy_write_1bit(ioaddr, PHY_DATA_0); 1823 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_1); 1824 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_0); 1825 1825 1826 1826 /* Write a word data to PHY controller */ 1827 1827 for ( i = 0x8000; i > 0; i >>= 1) 1828 - phy_write_1bit(ioaddr, 1829 - phy_data & i ? PHY_DATA_1 : PHY_DATA_0); 1828 + dmfe_phy_write_1bit(ioaddr, 1829 + phy_data & i ? PHY_DATA_1 : PHY_DATA_0); 1830 1830 } 1831 1831 } 1832 1832 ··· 1835 1835 * Read a word data from phy register 1836 1836 */ 1837 1837 1838 - static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id) 1838 + static u16 dmfe_phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id) 1839 1839 { 1840 1840 int i; 1841 1841 u16 phy_data; ··· 1848 1848 1849 1849 /* Send 33 synchronization clock to Phy controller */ 1850 1850 for (i = 0; i < 35; i++) 1851 - phy_write_1bit(ioaddr, PHY_DATA_1); 1851 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_1); 1852 1852 1853 1853 /* Send start command(01) to Phy */ 1854 - phy_write_1bit(ioaddr, PHY_DATA_0); 1855 - phy_write_1bit(ioaddr, PHY_DATA_1); 1854 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_0); 1855 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_1); 1856 1856 1857 1857 /* Send read command(10) to Phy */ 1858 - phy_write_1bit(ioaddr, PHY_DATA_1); 1859 - phy_write_1bit(ioaddr, PHY_DATA_0); 1858 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_1); 1859 + dmfe_phy_write_1bit(ioaddr, PHY_DATA_0); 1860 1860 1861 1861 /* Send Phy address */ 1862 1862 for (i = 0x10; i > 0; i = i >> 1) 1863 - phy_write_1bit(ioaddr, 1864 - phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); 1863 + dmfe_phy_write_1bit(ioaddr, 1864 + phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); 1865 1865 1866 1866 /* Send register address */ 1867 1867 for (i = 0x10; i > 0; i = i >> 1) 1868 - phy_write_1bit(ioaddr, 1869 - offset & i ? PHY_DATA_1 : PHY_DATA_0); 1868 + dmfe_phy_write_1bit(ioaddr, 1869 + offset & i ? PHY_DATA_1 : PHY_DATA_0); 1870 1870 1871 1871 /* Skip transition state */ 1872 - phy_read_1bit(ioaddr); 1872 + dmfe_phy_read_1bit(ioaddr); 1873 1873 1874 1874 /* read 16bit data */ 1875 1875 for (phy_data = 0, i = 0; i < 16; i++) { 1876 1876 phy_data <<= 1; 1877 - phy_data |= phy_read_1bit(ioaddr); 1877 + phy_data |= dmfe_phy_read_1bit(ioaddr); 1878 1878 } 1879 1879 } 1880 1880 ··· 1886 1886 * Write one bit data to Phy Controller 1887 1887 */ 1888 1888 1889 - static void phy_write_1bit(void __iomem *ioaddr, u32 phy_data) 1889 + static void dmfe_phy_write_1bit(void __iomem *ioaddr, u32 phy_data) 1890 1890 { 1891 1891 dw32(DCR9, phy_data); /* MII Clock Low */ 1892 1892 udelay(1); ··· 1901 1901 * Read one bit phy data from PHY controller 1902 1902 */ 1903 1903 1904 - static u16 phy_read_1bit(void __iomem *ioaddr) 1904 + static u16 dmfe_phy_read_1bit(void __iomem *ioaddr) 1905 1905 { 1906 1906 u16 phy_data; 1907 1907 ··· 1995 1995 /* Check DM9801 or DM9802 present or not */ 1996 1996 db->HPNA_present = 0; 1997 1997 update_cr6(db->cr6_data | 0x40000, db->ioaddr); 1998 - tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id); 1998 + tmp_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id); 1999 1999 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) { 2000 2000 /* DM9801 or DM9802 present */ 2001 2001 db->HPNA_timer = 8; 2002 - if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) { 2002 + if ( dmfe_phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) { 2003 2003 /* DM9801 HomeRun */ 2004 2004 db->HPNA_present = 1; 2005 2005 dmfe_program_DM9801(db, tmp_reg); ··· 2025 2025 switch(HPNA_rev) { 2026 2026 case 0xb900: /* DM9801 E3 */ 2027 2027 db->HPNA_command |= 0x1000; 2028 - reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id); 2028 + reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id); 2029 2029 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000; 2030 - reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); 2030 + reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); 2031 2031 break; 2032 2032 case 0xb901: /* DM9801 E4 */ 2033 - reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); 2033 + reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); 2034 2034 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor; 2035 - reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); 2035 + reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); 2036 2036 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3; 2037 2037 break; 2038 2038 case 0xb902: /* DM9801 E5 */ 2039 2039 case 0xb903: /* DM9801 E6 */ 2040 2040 default: 2041 2041 db->HPNA_command |= 0x1000; 2042 - reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); 2042 + reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); 2043 2043 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5; 2044 - reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); 2044 + reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); 2045 2045 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor; 2046 2046 break; 2047 2047 } 2048 - phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id); 2049 - phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id); 2050 - phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id); 2048 + dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id); 2049 + dmfe_phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id); 2050 + dmfe_phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id); 2051 2051 } 2052 2052 2053 2053 ··· 2060 2060 uint phy_reg; 2061 2061 2062 2062 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR; 2063 - phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id); 2064 - phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); 2063 + dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id); 2064 + phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); 2065 2065 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor; 2066 - phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id); 2066 + dmfe_phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id); 2067 2067 } 2068 2068 2069 2069 ··· 2077 2077 uint phy_reg; 2078 2078 2079 2079 /* Got remote device status */ 2080 - phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60; 2080 + phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60; 2081 2081 switch(phy_reg) { 2082 2082 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */ 2083 2083 case 0x20: phy_reg = 0x0900;break; /* LP/HS */ ··· 2087 2087 2088 2088 /* Check remote device status match our setting ot not */ 2089 2089 if ( phy_reg != (db->HPNA_command & 0x0f00) ) { 2090 - phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, 2091 - db->chip_id); 2090 + dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, 2091 + db->chip_id); 2092 2092 db->HPNA_timer=8; 2093 2093 } else 2094 2094 db->HPNA_timer=600; /* Match, every 10 minutes, check */