Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

KVM: arm: Add ARMv7 API to flush TLBs

This patch adds ARMv7 architecture TLB Flush function.

Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Mario Smarduch <m.smarduch@samsung.com>

authored by

Mario Smarduch and committed by
Christoffer Dall
72fc36b6 e108ff2f

+25
+1
arch/arm/include/asm/kvm_asm.h
··· 96 96 97 97 extern void __kvm_flush_vm_context(void); 98 98 extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa); 99 + extern void __kvm_tlb_flush_vmid(struct kvm *kvm); 99 100 100 101 extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu); 101 102 #endif
+12
arch/arm/include/asm/kvm_host.h
··· 221 221 kvm_call_hyp((void*)hyp_stack_ptr, vector_ptr, pgd_ptr); 222 222 } 223 223 224 + /** 225 + * kvm_flush_remote_tlbs() - flush all VM TLB entries 226 + * @kvm: pointer to kvm structure. 227 + * 228 + * Interface to HYP function to flush all VM TLB entries without address 229 + * parameter. 230 + */ 231 + static inline void kvm_flush_remote_tlbs(struct kvm *kvm) 232 + { 233 + kvm_call_hyp(__kvm_tlb_flush_vmid, kvm); 234 + } 235 + 224 236 static inline int kvm_arch_dev_ioctl_check_extension(long ext) 225 237 { 226 238 return 0;
+1
arch/arm/kvm/Kconfig
··· 21 21 select PREEMPT_NOTIFIERS 22 22 select ANON_INODES 23 23 select HAVE_KVM_CPU_RELAX_INTERCEPT 24 + select HAVE_KVM_ARCH_TLB_FLUSH_ALL 24 25 select KVM_MMIO 25 26 select KVM_ARM_HOST 26 27 depends on ARM_VIRT_EXT && ARM_LPAE
+11
arch/arm/kvm/interrupts.S
··· 66 66 bx lr 67 67 ENDPROC(__kvm_tlb_flush_vmid_ipa) 68 68 69 + /** 70 + * void __kvm_tlb_flush_vmid(struct kvm *kvm) - Flush per-VMID TLBs 71 + * 72 + * Reuses __kvm_tlb_flush_vmid_ipa() for ARMv7, without passing address 73 + * parameter 74 + */ 75 + 76 + ENTRY(__kvm_tlb_flush_vmid) 77 + b __kvm_tlb_flush_vmid_ipa 78 + ENDPROC(__kvm_tlb_flush_vmid) 79 + 69 80 /******************************************************************** 70 81 * Flush TLBs and instruction caches of all CPUs inside the inner-shareable 71 82 * domain, for all VMIDs