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Merge tag 'apple-soc-drivers-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/drivers

Apple SoC driver updates for 6.18

Krzysztof Kozlowski asked us to move away from generic compatibles:
- Adjust all dt-bindings to use apple,t8103-XXXX instead of apple,XXXX
as fallback and add a comment that the old generic list should no
longer be extended.
- Add new fallback compatibles to pinctrl, pmdomain, spi, and mca
drivers. These changes have been Acked by their subsystem maintainers
to be merged through our tree together with the dt-bindings.

Support for pre-M1 Apple Silicon:
- SART and mailbox gain support for Apple's A11, which are both
required for NVMe.
- NVMe also gains support for Apple's A11 and the nvme maintainers
prefer that we merge this through the soc tree together with
the mailbox and SART changes.
- SPMI compatibles for A11 and T2 have been added, also going through
the soc tree due to conflicts with the generic compatible removal and
because no driver change is required.

Signed-off-by: Sven Peter <sven@kernel.org>

* tag 'apple-soc-drivers-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux: (32 commits)
pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
dt-bindings: spmi: Add Apple A11 and T2 compatible
spi: apple: Add "apple,t8103-spi" compatible
ASoC: apple: mca: Add "apple,t8103-mca" compatible
pinctrl: apple: Add "apple,t8103-pinctrl" as compatible
spi: dt-bindings: apple,spi: Add t6020-spi compatible
ASoC: dt-bindings: apple,mca: Add t6020-mca compatible
dt-bindings: dma: apple,admac: Add t6020-admac compatible
dt-bindings: clock: apple,nco: Add t6020-nco compatible
dt-bindings: watchdog: apple,wdt: Add t6020-wdt compatible
dt-bindings: spmi: apple,spmi: Add t6020-spmi compatible
dt-bindings: mfd: apple,smc: Add t6020-smc compatible
dt-bindings: net: bcm4329-fmac: Add BCM4388 PCI compatible
dt-bindings: net: bcm4377-bluetooth: Add BCM4388 compatible
dt-bindings: nvme: apple: Add apple,t6020-nvme-ans2 compatible
dt-bindings: iommu: apple,sart: Add apple,t6020-sart compatible
dt-bindings: gpu: apple,agx: Add agx-{g14s,g14c,g14d} compatibles
dt-bindings: mailbox: apple,mailbox: Add t6020 compatible
dt-bindings: pinctrl: apple,pinctrl: Add apple,t6020-pinctrl compatible
dt-bindings: iommu: dart: Add apple,t6020-dart compatible
...

Link: https://lore.kernel.org/r/20250920123028.49973-1-sven@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 72af4030 3783cdc1

+404 -166
+20 -13
Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml
··· 20 20 pattern: "^power-management@[0-9a-f]+$" 21 21 22 22 compatible: 23 - items: 24 - - enum: 25 - - apple,s5l8960x-pmgr 26 - - apple,t7000-pmgr 27 - - apple,s8000-pmgr 28 - - apple,t8010-pmgr 29 - - apple,t8015-pmgr 30 - - apple,t8103-pmgr 31 - - apple,t8112-pmgr 32 - - apple,t6000-pmgr 33 - - const: apple,pmgr 34 - - const: syscon 35 - - const: simple-mfd 23 + oneOf: 24 + - items: 25 + - enum: 26 + # Do not add additional SoC to this list. 27 + - apple,s5l8960x-pmgr 28 + - apple,t7000-pmgr 29 + - apple,s8000-pmgr 30 + - apple,t8010-pmgr 31 + - apple,t8015-pmgr 32 + - apple,t8103-pmgr 33 + - apple,t8112-pmgr 34 + - apple,t6000-pmgr 35 + - const: apple,pmgr 36 + - const: syscon 37 + - const: simple-mfd 38 + - items: 39 + - const: apple,t6020-pmgr 40 + - const: apple,t8103-pmgr 41 + - const: syscon 42 + - const: simple-mfd 36 43 37 44 reg: 38 45 maxItems: 1
+11 -6
Documentation/devicetree/bindings/clock/apple,nco.yaml
··· 19 19 20 20 properties: 21 21 compatible: 22 - items: 23 - - enum: 24 - - apple,t6000-nco 25 - - apple,t8103-nco 26 - - apple,t8112-nco 27 - - const: apple,nco 22 + oneOf: 23 + - items: 24 + - const: apple,t6020-nco 25 + - const: apple,t8103-nco 26 + - items: 27 + - enum: 28 + # Do not add additional SoC to this list. 29 + - apple,t6000-nco 30 + - apple,t8103-nco 31 + - apple,t8112-nco 32 + - const: apple,nco 28 33 29 34 clocks: 30 35 description:
+3
Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml
··· 35 35 - const: apple,t7000-cluster-cpufreq 36 36 - const: apple,s5l8960x-cluster-cpufreq 37 37 - const: apple,s5l8960x-cluster-cpufreq 38 + - items: 39 + - const: apple,t6020-cluster-cpufreq 40 + - const: apple,t8112-cluster-cpufreq 38 41 39 42 reg: 40 43 maxItems: 1
+11 -6
Documentation/devicetree/bindings/dma/apple,admac.yaml
··· 22 22 23 23 properties: 24 24 compatible: 25 - items: 26 - - enum: 27 - - apple,t6000-admac 28 - - apple,t8103-admac 29 - - apple,t8112-admac 30 - - const: apple,admac 25 + oneOf: 26 + - items: 27 + - const: apple,t6020-admac 28 + - const: apple,t8103-admac 29 + - items: 30 + - enum: 31 + # Do not add additional SoC to this list. 32 + - apple,t6000-admac 33 + - apple,t8103-admac 34 + - apple,t8112-admac 35 + - const: apple,admac 31 36 32 37 reg: 33 38 maxItems: 1
+6
Documentation/devicetree/bindings/gpu/apple,agx.yaml
··· 16 16 - apple,agx-g13g 17 17 - apple,agx-g13s 18 18 - apple,agx-g14g 19 + - apple,agx-g14s 19 20 - items: 20 21 - enum: 21 22 - apple,agx-g13c 22 23 - apple,agx-g13d 23 24 - const: apple,agx-g13s 25 + - items: 26 + - enum: 27 + - apple,agx-g14c 28 + - apple,agx-g14d 29 + - const: apple,agx-g14s 24 30 25 31 reg: 26 32 items:
+1
Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml
··· 34 34 - enum: 35 35 - apple,t8112-aic 36 36 - apple,t6000-aic 37 + - apple,t6020-aic 37 38 - const: apple,aic2 38 39 39 40 interrupt-controller: true
+9 -5
Documentation/devicetree/bindings/iommu/apple,dart.yaml
··· 22 22 23 23 properties: 24 24 compatible: 25 - enum: 26 - - apple,t8103-dart 27 - - apple,t8103-usb4-dart 28 - - apple,t8110-dart 29 - - apple,t6000-dart 25 + oneOf: 26 + - enum: 27 + - apple,t8103-dart 28 + - apple,t8103-usb4-dart 29 + - apple,t8110-dart 30 + - apple,t6000-dart 31 + - items: 32 + - const: apple,t6020-dart 33 + - const: apple,t8110-dart 30 34 31 35 reg: 32 36 maxItems: 1
+4 -1
Documentation/devicetree/bindings/iommu/apple,sart.yaml
··· 30 30 compatible: 31 31 oneOf: 32 32 - items: 33 - - const: apple,t8112-sart 33 + - enum: 34 + - apple,t6020-sart 35 + - apple,t8112-sart 34 36 - const: apple,t6000-sart 35 37 - enum: 36 38 - apple,t6000-sart 39 + - apple,t8015-sart 37 40 - apple,t8103-sart 38 41 39 42 reg:
+8
Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
··· 31 31 - apple,t8103-asc-mailbox 32 32 - apple,t8112-asc-mailbox 33 33 - apple,t6000-asc-mailbox 34 + - apple,t6020-asc-mailbox 34 35 - const: apple,asc-mailbox-v4 36 + 37 + - description: 38 + An older ASC mailbox interface found on T2 and A11 that is also 39 + used for the NVMe coprocessor and the system management 40 + controller. 41 + items: 42 + - const: apple,t8015-asc-mailbox 35 43 36 44 - description: 37 45 M3 mailboxes are an older variant with a slightly different MMIO
+11 -6
Documentation/devicetree/bindings/mfd/apple,smc.yaml
··· 15 15 16 16 properties: 17 17 compatible: 18 - items: 19 - - enum: 20 - - apple,t6000-smc 21 - - apple,t8103-smc 22 - - apple,t8112-smc 23 - - const: apple,smc 18 + oneOf: 19 + - items: 20 + - const: apple,t6020-smc 21 + - const: apple,t8103-smc 22 + - items: 23 + - enum: 24 + # Do not add additional SoC to this list. 25 + - apple,t6000-smc 26 + - apple,t8103-smc 27 + - apple,t8112-smc 28 + - const: apple,smc 24 29 25 30 reg: 26 31 items:
+1
Documentation/devicetree/bindings/net/bluetooth/brcm,bcm4377-bluetooth.yaml
··· 23 23 - pci14e4,5fa0 # BCM4377 24 24 - pci14e4,5f69 # BCM4378 25 25 - pci14e4,5f71 # BCM4387 26 + - pci14e4,5f72 # BCM4388 26 27 27 28 reg: 28 29 maxItems: 1
+1
Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml
··· 53 53 - pci14e4,4488 # BCM4377 54 54 - pci14e4,4425 # BCM4378 55 55 - pci14e4,4433 # BCM4387 56 + - pci14e4,4434 # BCM4388 56 57 - pci14e4,449d # BCM43752 57 58 58 59 reg:
+18 -12
Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml
··· 11 11 12 12 properties: 13 13 compatible: 14 - items: 15 - - enum: 16 - - apple,t8103-nvme-ans2 17 - - apple,t8112-nvme-ans2 18 - - apple,t6000-nvme-ans2 19 - - const: apple,nvme-ans2 14 + oneOf: 15 + - const: apple,t8015-nvme-ans2 16 + - items: 17 + - const: apple,t6020-nvme-ans2 18 + - const: apple,t8103-nvme-ans2 19 + - items: 20 + - enum: 21 + # Do not add additional SoC to this list. 22 + - apple,t8103-nvme-ans2 23 + - apple,t8112-nvme-ans2 24 + - apple,t6000-nvme-ans2 25 + - const: apple,nvme-ans2 20 26 21 27 reg: 22 28 items: ··· 73 67 compatible: 74 68 contains: 75 69 enum: 76 - - apple,t8103-nvme-ans2 77 - - apple,t8112-nvme-ans2 70 + - apple,t6000-nvme-ans2 71 + - apple,t6020-nvme-ans2 78 72 then: 79 73 properties: 80 74 power-domains: 81 - maxItems: 2 75 + minItems: 3 82 76 power-domain-names: 83 - maxItems: 2 77 + minItems: 3 84 78 else: 85 79 properties: 86 80 power-domains: 87 - minItems: 3 81 + maxItems: 2 88 82 power-domain-names: 89 - minItems: 3 83 + maxItems: 2 90 84 91 85 required: 92 86 - compatible
+16 -11
Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
··· 16 16 17 17 properties: 18 18 compatible: 19 - items: 20 - - enum: 21 - - apple,s5l8960x-pinctrl 22 - - apple,t7000-pinctrl 23 - - apple,s8000-pinctrl 24 - - apple,t8010-pinctrl 25 - - apple,t8015-pinctrl 26 - - apple,t8103-pinctrl 27 - - apple,t8112-pinctrl 28 - - apple,t6000-pinctrl 29 - - const: apple,pinctrl 19 + oneOf: 20 + - items: 21 + - const: apple,t6020-pinctrl 22 + - const: apple,t8103-pinctrl 23 + - items: 24 + # Do not add additional SoC to this list. 25 + - enum: 26 + - apple,s5l8960x-pinctrl 27 + - apple,t7000-pinctrl 28 + - apple,s8000-pinctrl 29 + - apple,t8010-pinctrl 30 + - apple,t8015-pinctrl 31 + - apple,t8103-pinctrl 32 + - apple,t8112-pinctrl 33 + - apple,t6000-pinctrl 34 + - const: apple,pinctrl 30 35 31 36 reg: 32 37 maxItems: 1
+16 -11
Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml
··· 29 29 30 30 properties: 31 31 compatible: 32 - items: 33 - - enum: 34 - - apple,s5l8960x-pmgr-pwrstate 35 - - apple,t7000-pmgr-pwrstate 36 - - apple,s8000-pmgr-pwrstate 37 - - apple,t8010-pmgr-pwrstate 38 - - apple,t8015-pmgr-pwrstate 39 - - apple,t8103-pmgr-pwrstate 40 - - apple,t8112-pmgr-pwrstate 41 - - apple,t6000-pmgr-pwrstate 42 - - const: apple,pmgr-pwrstate 32 + oneOf: 33 + - items: 34 + - enum: 35 + # Do not add additional SoC to this list. 36 + - apple,s5l8960x-pmgr-pwrstate 37 + - apple,t7000-pmgr-pwrstate 38 + - apple,s8000-pmgr-pwrstate 39 + - apple,t8010-pmgr-pwrstate 40 + - apple,t8015-pmgr-pwrstate 41 + - apple,t8103-pmgr-pwrstate 42 + - apple,t8112-pmgr-pwrstate 43 + - apple,t6000-pmgr-pwrstate 44 + - const: apple,pmgr-pwrstate 45 + - items: 46 + - const: apple,t6020-pmgr-pwrstate 47 + - const: apple,t8103-pmgr-pwrstate 43 48 44 49 reg: 45 50 maxItems: 1
+11 -6
Documentation/devicetree/bindings/sound/apple,mca.yaml
··· 19 19 20 20 properties: 21 21 compatible: 22 - items: 23 - - enum: 24 - - apple,t6000-mca 25 - - apple,t8103-mca 26 - - apple,t8112-mca 27 - - const: apple,mca 22 + oneOf: 23 + - items: 24 + - const: apple,t6020-mca 25 + - const: apple,t8103-mca 26 + - items: 27 + - enum: 28 + # Do not add additional SoC to this list. 29 + - apple,t6000-mca 30 + - apple,t8103-mca 31 + - apple,t8112-mca 32 + - const: apple,mca 28 33 29 34 reg: 30 35 items:
+10 -6
Documentation/devicetree/bindings/spi/apple,spi.yaml
··· 14 14 15 15 properties: 16 16 compatible: 17 - items: 18 - - enum: 19 - - apple,t8103-spi 20 - - apple,t8112-spi 21 - - apple,t6000-spi 22 - - const: apple,spi 17 + oneOf: 18 + - items: 19 + - const: apple,t6020-spi 20 + - const: apple,t8103-spi 21 + - items: 22 + - enum: 23 + - apple,t8103-spi 24 + - apple,t8112-spi 25 + - apple,t6000-spi 26 + - const: apple,spi 23 27 24 28 reg: 25 29 maxItems: 1
+14 -6
Documentation/devicetree/bindings/spmi/apple,spmi.yaml
··· 16 16 17 17 properties: 18 18 compatible: 19 - items: 20 - - enum: 21 - - apple,t8103-spmi 22 - - apple,t6000-spmi 23 - - apple,t8112-spmi 24 - - const: apple,spmi 19 + oneOf: 20 + - items: 21 + - enum: 22 + - apple,t6020-spmi 23 + - apple,t8012-spmi 24 + - apple,t8015-spmi 25 + - const: apple,t8103-spmi 26 + - items: 27 + - enum: 28 + # Do not add additional SoC to this list. 29 + - apple,t8103-spmi 30 + - apple,t6000-spmi 31 + - apple,t8112-spmi 32 + - const: apple,spmi 25 33 26 34 reg: 27 35 maxItems: 1
+16 -11
Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
··· 14 14 15 15 properties: 16 16 compatible: 17 - items: 18 - - enum: 19 - - apple,s5l8960x-wdt 20 - - apple,t7000-wdt 21 - - apple,s8000-wdt 22 - - apple,t8010-wdt 23 - - apple,t8015-wdt 24 - - apple,t8103-wdt 25 - - apple,t8112-wdt 26 - - apple,t6000-wdt 27 - - const: apple,wdt 17 + oneOf: 18 + - items: 19 + - const: apple,t6020-wdt 20 + - const: apple,t8103-wdt 21 + - items: 22 + - enum: 23 + # Do not add additional SoC to this list. 24 + - apple,s5l8960x-wdt 25 + - apple,t7000-wdt 26 + - apple,s8000-wdt 27 + - apple,t8010-wdt 28 + - apple,t8015-wdt 29 + - apple,t8103-wdt 30 + - apple,t8112-wdt 31 + - apple,t6000-wdt 32 + - const: apple,wdt 28 33 29 34 reg: 30 35 maxItems: 1
+137 -60
drivers/nvme/host/apple.c
··· 35 35 #include "nvme.h" 36 36 37 37 #define APPLE_ANS_BOOT_TIMEOUT USEC_PER_SEC 38 - #define APPLE_ANS_MAX_QUEUE_DEPTH 64 39 38 40 39 #define APPLE_ANS_COPROC_CPU_CONTROL 0x44 41 40 #define APPLE_ANS_COPROC_CPU_CONTROL_RUN BIT(4) ··· 73 74 */ 74 75 #define APPLE_NVME_AQ_DEPTH 2 75 76 #define APPLE_NVME_AQ_MQ_TAG_DEPTH (APPLE_NVME_AQ_DEPTH - 1) 77 + 78 + #define APPLE_NVME_IOSQES 7 76 79 77 80 /* 78 81 * These can be higher, but we need to ensure that any command doesn't ··· 143 142 u32 __iomem *sq_db; 144 143 u32 __iomem *cq_db; 145 144 145 + u16 sq_tail; 146 146 u16 cq_head; 147 147 u8 cq_phase; 148 148 ··· 168 166 struct scatterlist *sg; 169 167 }; 170 168 169 + struct apple_nvme_hw { 170 + bool has_lsq_nvmmu; 171 + u32 max_queue_depth; 172 + }; 173 + 171 174 struct apple_nvme { 172 175 struct device *dev; 173 176 174 177 void __iomem *mmio_coproc; 175 178 void __iomem *mmio_nvme; 179 + const struct apple_nvme_hw *hw; 176 180 177 181 struct device **pd_dev; 178 182 struct device_link **pd_link; ··· 223 215 224 216 static unsigned int apple_nvme_queue_depth(struct apple_nvme_queue *q) 225 217 { 226 - if (q->is_adminq) 218 + struct apple_nvme *anv = queue_to_apple_nvme(q); 219 + 220 + if (q->is_adminq && anv->hw->has_lsq_nvmmu) 227 221 return APPLE_NVME_AQ_DEPTH; 228 222 229 - return APPLE_ANS_MAX_QUEUE_DEPTH; 223 + return anv->hw->max_queue_depth; 230 224 } 231 225 232 226 static void apple_nvme_rtkit_crashed(void *cookie, const void *crashlog, size_t crashlog_size) ··· 290 280 "NVMMU TCB invalidation failed\n"); 291 281 } 292 282 293 - static void apple_nvme_submit_cmd(struct apple_nvme_queue *q, 283 + static void apple_nvme_submit_cmd_t8015(struct apple_nvme_queue *q, 284 + struct nvme_command *cmd) 285 + { 286 + struct apple_nvme *anv = queue_to_apple_nvme(q); 287 + 288 + spin_lock_irq(&anv->lock); 289 + 290 + if (q->is_adminq) 291 + memcpy(&q->sqes[q->sq_tail], cmd, sizeof(*cmd)); 292 + else 293 + memcpy((void *)q->sqes + (q->sq_tail << APPLE_NVME_IOSQES), 294 + cmd, sizeof(*cmd)); 295 + 296 + if (++q->sq_tail == anv->hw->max_queue_depth) 297 + q->sq_tail = 0; 298 + 299 + writel(q->sq_tail, q->sq_db); 300 + spin_unlock_irq(&anv->lock); 301 + } 302 + 303 + 304 + static void apple_nvme_submit_cmd_t8103(struct apple_nvme_queue *q, 294 305 struct nvme_command *cmd) 295 306 { 296 307 struct apple_nvme *anv = queue_to_apple_nvme(q); ··· 621 590 __u16 command_id = READ_ONCE(cqe->command_id); 622 591 struct request *req; 623 592 624 - apple_nvmmu_inval(q, command_id); 593 + if (anv->hw->has_lsq_nvmmu) 594 + apple_nvmmu_inval(q, command_id); 625 595 626 596 req = nvme_find_rq(apple_nvme_queue_tagset(anv, q), command_id); 627 597 if (unlikely(!req)) { ··· 717 685 c.create_cq.opcode = nvme_admin_create_cq; 718 686 c.create_cq.prp1 = cpu_to_le64(anv->ioq.cq_dma_addr); 719 687 c.create_cq.cqid = cpu_to_le16(1); 720 - c.create_cq.qsize = cpu_to_le16(APPLE_ANS_MAX_QUEUE_DEPTH - 1); 688 + c.create_cq.qsize = cpu_to_le16(anv->hw->max_queue_depth - 1); 721 689 c.create_cq.cq_flags = cpu_to_le16(NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED); 722 690 c.create_cq.irq_vector = cpu_to_le16(0); 723 691 ··· 745 713 c.create_sq.opcode = nvme_admin_create_sq; 746 714 c.create_sq.prp1 = cpu_to_le64(anv->ioq.sq_dma_addr); 747 715 c.create_sq.sqid = cpu_to_le16(1); 748 - c.create_sq.qsize = cpu_to_le16(APPLE_ANS_MAX_QUEUE_DEPTH - 1); 716 + c.create_sq.qsize = cpu_to_le16(anv->hw->max_queue_depth - 1); 749 717 c.create_sq.sq_flags = cpu_to_le16(NVME_QUEUE_PHYS_CONTIG); 750 718 c.create_sq.cqid = cpu_to_le16(1); 751 719 ··· 797 765 } 798 766 799 767 nvme_start_request(req); 800 - apple_nvme_submit_cmd(q, cmnd); 768 + 769 + if (anv->hw->has_lsq_nvmmu) 770 + apple_nvme_submit_cmd_t8103(q, cmnd); 771 + else 772 + apple_nvme_submit_cmd_t8015(q, cmnd); 773 + 801 774 return BLK_STS_OK; 802 775 803 776 out_free_cmd: ··· 1007 970 static void apple_nvme_init_queue(struct apple_nvme_queue *q) 1008 971 { 1009 972 unsigned int depth = apple_nvme_queue_depth(q); 973 + struct apple_nvme *anv = queue_to_apple_nvme(q); 1010 974 1011 975 q->cq_head = 0; 1012 976 q->cq_phase = 1; 1013 - memset(q->tcbs, 0, 1014 - APPLE_ANS_MAX_QUEUE_DEPTH * sizeof(struct apple_nvmmu_tcb)); 977 + if (anv->hw->has_lsq_nvmmu) 978 + memset(q->tcbs, 0, anv->hw->max_queue_depth 979 + * sizeof(struct apple_nvmmu_tcb)); 1015 980 memset(q->cqes, 0, depth * sizeof(struct nvme_completion)); 1016 981 WRITE_ONCE(q->enabled, true); 1017 982 wmb(); /* ensure the first interrupt sees the initialization */ ··· 1108 1069 1109 1070 dma_set_max_seg_size(anv->dev, 0xffffffff); 1110 1071 1111 - /* 1112 - * Enable NVMMU and linear submission queues. 1113 - * While we could keep those disabled and pretend this is slightly 1114 - * more common NVMe controller we'd still need some quirks (e.g. 1115 - * sq entries will be 128 bytes) and Apple might drop support for 1116 - * that mode in the future. 1117 - */ 1118 - writel(APPLE_ANS_LINEAR_SQ_EN, 1119 - anv->mmio_nvme + APPLE_ANS_LINEAR_SQ_CTRL); 1072 + if (anv->hw->has_lsq_nvmmu) { 1073 + /* 1074 + * Enable NVMMU and linear submission queues which is required 1075 + * since T6000. 1076 + */ 1077 + writel(APPLE_ANS_LINEAR_SQ_EN, 1078 + anv->mmio_nvme + APPLE_ANS_LINEAR_SQ_CTRL); 1120 1079 1121 - /* Allow as many pending command as possible for both queues */ 1122 - writel(APPLE_ANS_MAX_QUEUE_DEPTH | (APPLE_ANS_MAX_QUEUE_DEPTH << 16), 1123 - anv->mmio_nvme + APPLE_ANS_MAX_PEND_CMDS_CTRL); 1080 + /* Allow as many pending command as possible for both queues */ 1081 + writel(anv->hw->max_queue_depth 1082 + | (anv->hw->max_queue_depth << 16), anv->mmio_nvme 1083 + + APPLE_ANS_MAX_PEND_CMDS_CTRL); 1124 1084 1125 - /* Setup the NVMMU for the maximum admin and IO queue depth */ 1126 - writel(APPLE_ANS_MAX_QUEUE_DEPTH - 1, 1127 - anv->mmio_nvme + APPLE_NVMMU_NUM_TCBS); 1085 + /* Setup the NVMMU for the maximum admin and IO queue depth */ 1086 + writel(anv->hw->max_queue_depth - 1, 1087 + anv->mmio_nvme + APPLE_NVMMU_NUM_TCBS); 1128 1088 1129 - /* 1130 - * This is probably a chicken bit: without it all commands where any PRP 1131 - * is set to zero (including those that don't use that field) fail and 1132 - * the co-processor complains about "completed with err BAD_CMD-" or 1133 - * a "NULL_PRP_PTR_ERR" in the syslog 1134 - */ 1135 - writel(readl(anv->mmio_nvme + APPLE_ANS_UNKNOWN_CTRL) & 1136 - ~APPLE_ANS_PRP_NULL_CHECK, 1137 - anv->mmio_nvme + APPLE_ANS_UNKNOWN_CTRL); 1089 + /* 1090 + * This is probably a chicken bit: without it all commands 1091 + * where any PRP is set to zero (including those that don't use 1092 + * that field) fail and the co-processor complains about 1093 + * "completed with err BAD_CMD-" or a "NULL_PRP_PTR_ERR" in the 1094 + * syslog 1095 + */ 1096 + writel(readl(anv->mmio_nvme + APPLE_ANS_UNKNOWN_CTRL) & 1097 + ~APPLE_ANS_PRP_NULL_CHECK, 1098 + anv->mmio_nvme + APPLE_ANS_UNKNOWN_CTRL); 1099 + } 1138 1100 1139 1101 /* Setup the admin queue */ 1140 - aqa = APPLE_NVME_AQ_DEPTH - 1; 1102 + if (anv->hw->has_lsq_nvmmu) 1103 + aqa = APPLE_NVME_AQ_DEPTH - 1; 1104 + else 1105 + aqa = anv->hw->max_queue_depth - 1; 1141 1106 aqa |= aqa << 16; 1142 1107 writel(aqa, anv->mmio_nvme + NVME_REG_AQA); 1143 1108 writeq(anv->adminq.sq_dma_addr, anv->mmio_nvme + NVME_REG_ASQ); 1144 1109 writeq(anv->adminq.cq_dma_addr, anv->mmio_nvme + NVME_REG_ACQ); 1145 1110 1146 - /* Setup NVMMU for both queues */ 1147 - writeq(anv->adminq.tcb_dma_addr, 1148 - anv->mmio_nvme + APPLE_NVMMU_ASQ_TCB_BASE); 1149 - writeq(anv->ioq.tcb_dma_addr, 1150 - anv->mmio_nvme + APPLE_NVMMU_IOSQ_TCB_BASE); 1111 + if (anv->hw->has_lsq_nvmmu) { 1112 + /* Setup NVMMU for both queues */ 1113 + writeq(anv->adminq.tcb_dma_addr, 1114 + anv->mmio_nvme + APPLE_NVMMU_ASQ_TCB_BASE); 1115 + writeq(anv->ioq.tcb_dma_addr, 1116 + anv->mmio_nvme + APPLE_NVMMU_IOSQ_TCB_BASE); 1117 + } 1151 1118 1152 1119 anv->ctrl.sqsize = 1153 - APPLE_ANS_MAX_QUEUE_DEPTH - 1; /* 0's based queue depth */ 1120 + anv->hw->max_queue_depth - 1; /* 0's based queue depth */ 1154 1121 anv->ctrl.cap = readq(anv->mmio_nvme + NVME_REG_CAP); 1155 1122 1156 1123 dev_dbg(anv->dev, "Enabling controller now"); ··· 1327 1282 * both queues. The admin queue gets the first APPLE_NVME_AQ_DEPTH which 1328 1283 * must be marked as reserved in the IO queue. 1329 1284 */ 1330 - anv->tagset.reserved_tags = APPLE_NVME_AQ_DEPTH; 1331 - anv->tagset.queue_depth = APPLE_ANS_MAX_QUEUE_DEPTH - 1; 1285 + if (anv->hw->has_lsq_nvmmu) 1286 + anv->tagset.reserved_tags = APPLE_NVME_AQ_DEPTH; 1287 + anv->tagset.queue_depth = anv->hw->max_queue_depth - 1; 1332 1288 anv->tagset.timeout = NVME_IO_TIMEOUT; 1333 1289 anv->tagset.numa_node = NUMA_NO_NODE; 1334 1290 anv->tagset.cmd_size = sizeof(struct apple_nvme_iod); ··· 1353 1307 struct apple_nvme_queue *q) 1354 1308 { 1355 1309 unsigned int depth = apple_nvme_queue_depth(q); 1310 + size_t iosq_size; 1356 1311 1357 1312 q->cqes = dmam_alloc_coherent(anv->dev, 1358 1313 depth * sizeof(struct nvme_completion), ··· 1361 1314 if (!q->cqes) 1362 1315 return -ENOMEM; 1363 1316 1364 - q->sqes = dmam_alloc_coherent(anv->dev, 1365 - depth * sizeof(struct nvme_command), 1317 + if (anv->hw->has_lsq_nvmmu) 1318 + iosq_size = depth * sizeof(struct nvme_command); 1319 + else 1320 + iosq_size = depth << APPLE_NVME_IOSQES; 1321 + 1322 + q->sqes = dmam_alloc_coherent(anv->dev, iosq_size, 1366 1323 &q->sq_dma_addr, GFP_KERNEL); 1367 1324 if (!q->sqes) 1368 1325 return -ENOMEM; 1369 1326 1370 - /* 1371 - * We need the maximum queue depth here because the NVMMU only has a 1372 - * single depth configuration shared between both queues. 1373 - */ 1374 - q->tcbs = dmam_alloc_coherent(anv->dev, 1375 - APPLE_ANS_MAX_QUEUE_DEPTH * 1376 - sizeof(struct apple_nvmmu_tcb), 1377 - &q->tcb_dma_addr, GFP_KERNEL); 1378 - if (!q->tcbs) 1379 - return -ENOMEM; 1327 + if (anv->hw->has_lsq_nvmmu) { 1328 + /* 1329 + * We need the maximum queue depth here because the NVMMU only 1330 + * has a single depth configuration shared between both queues. 1331 + */ 1332 + q->tcbs = dmam_alloc_coherent(anv->dev, 1333 + anv->hw->max_queue_depth * 1334 + sizeof(struct apple_nvmmu_tcb), 1335 + &q->tcb_dma_addr, GFP_KERNEL); 1336 + if (!q->tcbs) 1337 + return -ENOMEM; 1338 + } 1380 1339 1381 1340 /* 1382 1341 * initialize phase to make sure the allocated and empty memory ··· 1466 1413 anv->adminq.is_adminq = true; 1467 1414 platform_set_drvdata(pdev, anv); 1468 1415 1416 + anv->hw = of_device_get_match_data(&pdev->dev); 1417 + if (!anv->hw) { 1418 + ret = -ENODEV; 1419 + goto put_dev; 1420 + } 1421 + 1469 1422 ret = apple_nvme_attach_genpd(anv); 1470 1423 if (ret < 0) { 1471 1424 dev_err_probe(dev, ret, "Failed to attach power domains"); ··· 1503 1444 goto put_dev; 1504 1445 } 1505 1446 1506 - anv->adminq.sq_db = anv->mmio_nvme + APPLE_ANS_LINEAR_ASQ_DB; 1507 - anv->adminq.cq_db = anv->mmio_nvme + APPLE_ANS_ACQ_DB; 1508 - anv->ioq.sq_db = anv->mmio_nvme + APPLE_ANS_LINEAR_IOSQ_DB; 1509 - anv->ioq.cq_db = anv->mmio_nvme + APPLE_ANS_IOCQ_DB; 1447 + if (anv->hw->has_lsq_nvmmu) { 1448 + anv->adminq.sq_db = anv->mmio_nvme + APPLE_ANS_LINEAR_ASQ_DB; 1449 + anv->adminq.cq_db = anv->mmio_nvme + APPLE_ANS_ACQ_DB; 1450 + anv->ioq.sq_db = anv->mmio_nvme + APPLE_ANS_LINEAR_IOSQ_DB; 1451 + anv->ioq.cq_db = anv->mmio_nvme + APPLE_ANS_IOCQ_DB; 1452 + } else { 1453 + anv->adminq.sq_db = anv->mmio_nvme + NVME_REG_DBS; 1454 + anv->adminq.cq_db = anv->mmio_nvme + APPLE_ANS_ACQ_DB; 1455 + anv->ioq.sq_db = anv->mmio_nvme + NVME_REG_DBS + 8; 1456 + anv->ioq.cq_db = anv->mmio_nvme + APPLE_ANS_IOCQ_DB; 1457 + } 1510 1458 1511 1459 anv->sart = devm_apple_sart_get(dev); 1512 1460 if (IS_ERR(anv->sart)) { ··· 1691 1625 static DEFINE_SIMPLE_DEV_PM_OPS(apple_nvme_pm_ops, apple_nvme_suspend, 1692 1626 apple_nvme_resume); 1693 1627 1628 + static const struct apple_nvme_hw apple_nvme_t8015_hw = { 1629 + .has_lsq_nvmmu = false, 1630 + .max_queue_depth = 16, 1631 + }; 1632 + 1633 + static const struct apple_nvme_hw apple_nvme_t8103_hw = { 1634 + .has_lsq_nvmmu = true, 1635 + .max_queue_depth = 64, 1636 + }; 1637 + 1694 1638 static const struct of_device_id apple_nvme_of_match[] = { 1695 - { .compatible = "apple,nvme-ans2" }, 1639 + { .compatible = "apple,t8015-nvme-ans2", .data = &apple_nvme_t8015_hw }, 1640 + { .compatible = "apple,nvme-ans2", .data = &apple_nvme_t8103_hw }, 1696 1641 {}, 1697 1642 }; 1698 1643 MODULE_DEVICE_TABLE(of, apple_nvme_of_match);
+1
drivers/pinctrl/pinctrl-apple-gpio.c
··· 515 515 } 516 516 517 517 static const struct of_device_id apple_gpio_pinctrl_of_match[] = { 518 + { .compatible = "apple,t8103-pinctrl", }, 518 519 { .compatible = "apple,pinctrl", }, 519 520 { } 520 521 };
+1
drivers/pmdomain/apple/pmgr-pwrstate.c
··· 306 306 } 307 307 308 308 static const struct of_device_id apple_pmgr_ps_of_match[] = { 309 + { .compatible = "apple,t8103-pmgr-pwrstate" }, 309 310 { .compatible = "apple,pmgr-pwrstate" }, 310 311 {} 311 312 };
-3
drivers/soc/apple/Kconfig
··· 8 8 tristate "Apple SoC mailboxes" 9 9 depends on PM 10 10 depends on ARCH_APPLE || (64BIT && COMPILE_TEST) 11 - default ARCH_APPLE 12 11 help 13 12 Apple SoCs have various co-processors required for certain 14 13 peripherals to work (NVMe, display controller, etc.). This ··· 20 21 tristate "Apple RTKit co-processor IPC protocol" 21 22 depends on APPLE_MAILBOX 22 23 depends on ARCH_APPLE || COMPILE_TEST 23 - default ARCH_APPLE 24 24 help 25 25 Apple SoCs such as the M1 come with various co-processors running 26 26 their proprietary RTKit operating system. This option enables support ··· 31 33 config APPLE_SART 32 34 tristate "Apple SART DMA address filter" 33 35 depends on ARCH_APPLE || COMPILE_TEST 34 - default ARCH_APPLE 35 36 help 36 37 Apple SART is a simple DMA address filter used on Apple SoCs such 37 38 as the M1. It is usually required for the NVMe coprocessor which does
+19
drivers/soc/apple/mailbox.c
··· 47 47 #define APPLE_ASC_MBOX_I2A_RECV0 0x830 48 48 #define APPLE_ASC_MBOX_I2A_RECV1 0x838 49 49 50 + #define APPLE_T8015_MBOX_A2I_CONTROL 0x108 51 + #define APPLE_T8015_MBOX_I2A_CONTROL 0x10c 52 + 50 53 #define APPLE_M3_MBOX_CONTROL_FULL BIT(16) 51 54 #define APPLE_M3_MBOX_CONTROL_EMPTY BIT(17) 52 55 ··· 385 382 return 0; 386 383 } 387 384 385 + static const struct apple_mbox_hw apple_mbox_t8015_hw = { 386 + .control_full = APPLE_ASC_MBOX_CONTROL_FULL, 387 + .control_empty = APPLE_ASC_MBOX_CONTROL_EMPTY, 388 + 389 + .a2i_control = APPLE_T8015_MBOX_A2I_CONTROL, 390 + .a2i_send0 = APPLE_ASC_MBOX_A2I_SEND0, 391 + .a2i_send1 = APPLE_ASC_MBOX_A2I_SEND1, 392 + 393 + .i2a_control = APPLE_T8015_MBOX_I2A_CONTROL, 394 + .i2a_recv0 = APPLE_ASC_MBOX_I2A_RECV0, 395 + .i2a_recv1 = APPLE_ASC_MBOX_I2A_RECV1, 396 + 397 + .has_irq_controls = false, 398 + }; 399 + 388 400 static const struct apple_mbox_hw apple_mbox_asc_hw = { 389 401 .control_full = APPLE_ASC_MBOX_CONTROL_FULL, 390 402 .control_empty = APPLE_ASC_MBOX_CONTROL_EMPTY, ··· 436 418 437 419 static const struct of_device_id apple_mbox_of_match[] = { 438 420 { .compatible = "apple,asc-mailbox-v4", .data = &apple_mbox_asc_hw }, 421 + { .compatible = "apple,t8015-asc-mailbox", .data = &apple_mbox_t8015_hw }, 439 422 { .compatible = "apple,m3-mailbox-v2", .data = &apple_mbox_m3_hw }, 440 423 {} 441 424 };
+57 -3
drivers/soc/apple/sart.c
··· 25 25 26 26 #define APPLE_SART_MAX_ENTRIES 16 27 27 28 - /* This is probably a bitfield but the exact meaning of each bit is unknown. */ 29 - #define APPLE_SART_FLAGS_ALLOW 0xff 28 + /* SARTv0 registers */ 29 + #define APPLE_SART0_CONFIG(idx) (0x00 + 4 * (idx)) 30 + #define APPLE_SART0_CONFIG_FLAGS GENMASK(28, 24) 31 + #define APPLE_SART0_CONFIG_SIZE GENMASK(18, 0) 32 + #define APPLE_SART0_CONFIG_SIZE_SHIFT 12 33 + #define APPLE_SART0_CONFIG_SIZE_MAX GENMASK(18, 0) 34 + 35 + #define APPLE_SART0_PADDR(idx) (0x40 + 4 * (idx)) 36 + #define APPLE_SART0_PADDR_SHIFT 12 37 + 38 + #define APPLE_SART0_FLAGS_ALLOW 0xf 30 39 31 40 /* SARTv2 registers */ 32 41 #define APPLE_SART2_CONFIG(idx) (0x00 + 4 * (idx)) ··· 47 38 #define APPLE_SART2_PADDR(idx) (0x40 + 4 * (idx)) 48 39 #define APPLE_SART2_PADDR_SHIFT 12 49 40 41 + #define APPLE_SART2_FLAGS_ALLOW 0xff 42 + 50 43 /* SARTv3 registers */ 51 44 #define APPLE_SART3_CONFIG(idx) (0x00 + 4 * (idx)) 52 45 ··· 59 48 #define APPLE_SART3_SIZE_SHIFT 12 60 49 #define APPLE_SART3_SIZE_MAX GENMASK(29, 0) 61 50 51 + #define APPLE_SART3_FLAGS_ALLOW 0xff 52 + 62 53 struct apple_sart_ops { 63 54 void (*get_entry)(struct apple_sart *sart, int index, u8 *flags, 64 55 phys_addr_t *paddr, size_t *size); 65 56 void (*set_entry)(struct apple_sart *sart, int index, u8 flags, 66 57 phys_addr_t paddr_shifted, size_t size_shifted); 58 + /* This is probably a bitfield but the exact meaning of each bit is unknown. */ 59 + unsigned int flags_allow; 67 60 unsigned int size_shift; 68 61 unsigned int paddr_shift; 69 62 size_t size_max; ··· 81 66 82 67 unsigned long protected_entries; 83 68 unsigned long used_entries; 69 + }; 70 + 71 + static void sart0_get_entry(struct apple_sart *sart, int index, u8 *flags, 72 + phys_addr_t *paddr, size_t *size) 73 + { 74 + u32 cfg = readl(sart->regs + APPLE_SART0_CONFIG(index)); 75 + phys_addr_t paddr_ = readl(sart->regs + APPLE_SART0_PADDR(index)); 76 + size_t size_ = FIELD_GET(APPLE_SART0_CONFIG_SIZE, cfg); 77 + 78 + *flags = FIELD_GET(APPLE_SART0_CONFIG_FLAGS, cfg); 79 + *size = size_ << APPLE_SART0_CONFIG_SIZE_SHIFT; 80 + *paddr = paddr_ << APPLE_SART0_PADDR_SHIFT; 81 + } 82 + 83 + static void sart0_set_entry(struct apple_sart *sart, int index, u8 flags, 84 + phys_addr_t paddr_shifted, size_t size_shifted) 85 + { 86 + u32 cfg; 87 + 88 + cfg = FIELD_PREP(APPLE_SART0_CONFIG_FLAGS, flags); 89 + cfg |= FIELD_PREP(APPLE_SART0_CONFIG_SIZE, size_shifted); 90 + 91 + writel(paddr_shifted, sart->regs + APPLE_SART0_PADDR(index)); 92 + writel(cfg, sart->regs + APPLE_SART0_CONFIG(index)); 93 + } 94 + 95 + static struct apple_sart_ops sart_ops_v0 = { 96 + .get_entry = sart0_get_entry, 97 + .set_entry = sart0_set_entry, 98 + .flags_allow = APPLE_SART0_FLAGS_ALLOW, 99 + .size_shift = APPLE_SART0_CONFIG_SIZE_SHIFT, 100 + .paddr_shift = APPLE_SART0_PADDR_SHIFT, 101 + .size_max = APPLE_SART0_CONFIG_SIZE_MAX, 84 102 }; 85 103 86 104 static void sart2_get_entry(struct apple_sart *sart, int index, u8 *flags, ··· 143 95 static struct apple_sart_ops sart_ops_v2 = { 144 96 .get_entry = sart2_get_entry, 145 97 .set_entry = sart2_set_entry, 98 + .flags_allow = APPLE_SART2_FLAGS_ALLOW, 146 99 .size_shift = APPLE_SART2_CONFIG_SIZE_SHIFT, 147 100 .paddr_shift = APPLE_SART2_PADDR_SHIFT, 148 101 .size_max = APPLE_SART2_CONFIG_SIZE_MAX, ··· 171 122 static struct apple_sart_ops sart_ops_v3 = { 172 123 .get_entry = sart3_get_entry, 173 124 .set_entry = sart3_set_entry, 125 + .flags_allow = APPLE_SART3_FLAGS_ALLOW, 174 126 .size_shift = APPLE_SART3_SIZE_SHIFT, 175 127 .paddr_shift = APPLE_SART3_PADDR_SHIFT, 176 128 .size_max = APPLE_SART3_SIZE_MAX, ··· 283 233 if (test_and_set_bit(i, &sart->used_entries)) 284 234 continue; 285 235 286 - ret = sart_set_entry(sart, i, APPLE_SART_FLAGS_ALLOW, paddr, 236 + ret = sart_set_entry(sart, i, sart->ops->flags_allow, paddr, 287 237 size); 288 238 if (ret) { 289 239 dev_dbg(sart->dev, ··· 363 313 { 364 314 .compatible = "apple,t8103-sart", 365 315 .data = &sart_ops_v2, 316 + }, 317 + { 318 + .compatible = "apple,t8015-sart", 319 + .data = &sart_ops_v0, 366 320 }, 367 321 {} 368 322 };
+1
drivers/spi/spi-apple.c
··· 511 511 } 512 512 513 513 static const struct of_device_id apple_spi_of_match[] = { 514 + { .compatible = "apple,t8103-spi", }, 514 515 { .compatible = "apple,spi", }, 515 516 {} 516 517 };
+1
sound/soc/apple/mca.c
··· 1191 1191 } 1192 1192 1193 1193 static const struct of_device_id apple_mca_of_match[] = { 1194 + { .compatible = "apple,t8103-mca", }, 1194 1195 { .compatible = "apple,mca", }, 1195 1196 {} 1196 1197 };