clk: samsung: Remove CLK_IS_ROOT · tjh.dev/kernel@728f288

+6 -6

drivers/clk/samsung/clk-exynos4.c

··· 500 500 501 501 /* fixed rate clocks generated outside the soc */ 502 502 static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 503 - FRATE(CLK_XXTI, "xxti", NULL, CLK_IS_ROOT, 0), 504 - FRATE(CLK_XUSBXTI, "xusbxti", NULL, CLK_IS_ROOT, 0), 503 + FRATE(CLK_XXTI, "xxti", NULL, 0, 0), 504 + FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0), 505 505 }; 506 506 507 507 /* fixed rate clocks generated inside the soc */ 508 508 static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 509 - FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), 509 + FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000), 510 510 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000), 511 - FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 511 + FRATE(0, "sclk_usbphy0", NULL, 0, 48000000), 512 512 }; 513 513 514 514 static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { 515 - FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 515 + FRATE(0, "sclk_usbphy1", NULL, 0, 48000000), 516 516 }; 517 517 518 518 static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata = { ··· 1251 1251 fclk.id = CLK_FIN_PLL; 1252 1252 fclk.name = "fin_pll"; 1253 1253 fclk.parent_name = NULL; 1254 - fclk.flags = CLK_IS_ROOT; 1254 + fclk.flags = 0; 1255 1255 fclk.fixed_rate = finpll_f; 1256 1256 samsung_clk_register_fixed_rate(ctx, &fclk, 1); 1257 1257

+1 -1

drivers/clk/samsung/clk-exynos4415.c

··· 274 274 }; 275 275 276 276 static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = { 277 - FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 277 + FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000), 278 278 }; 279 279 280 280 static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = {

+5 -5

drivers/clk/samsung/clk-exynos5250.c

··· 262 262 263 263 /* fixed rate clocks generated outside the soc */ 264 264 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { 265 - FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 265 + FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 266 266 }; 267 267 268 268 /* fixed rate clocks generated inside the soc */ 269 269 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { 270 - FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 271 - FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), 272 - FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000), 273 - FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000), 270 + FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 271 + FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000), 272 + FRATE(0, "sclk_dptxphy", NULL, 0, 24000000), 273 + FRATE(0, "sclk_uhostphy", NULL, 0, 48000000), 274 274 }; 275 275 276 276 static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {

+16 -20

drivers/clk/samsung/clk-exynos5260.c

··· 1432 1432 /* fixed rate clocks generated inside the soc */ 1433 1433 static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = { 1434 1434 FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL, 1435 - CLK_IS_ROOT, 270000000), 1435 + 0, 270000000), 1436 1436 FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL, 1437 - CLK_IS_ROOT, 270000000), 1437 + 0, 270000000), 1438 1438 FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL, 1439 - CLK_IS_ROOT, 270000000), 1439 + 0, 270000000), 1440 1440 FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL, 1441 - CLK_IS_ROOT, 270000000), 1441 + 0, 270000000), 1442 1442 FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL, 1443 - CLK_IS_ROOT, 250000000), 1443 + 0, 250000000), 1444 1444 FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL, 1445 - CLK_IS_ROOT, 1660000000), 1445 + 0, 1660000000), 1446 1446 FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi", 1447 - NULL, CLK_IS_ROOT, 125000000), 1447 + NULL, 0, 125000000), 1448 1448 FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS, 1449 1449 "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL, 1450 - CLK_IS_ROOT, 187500000), 1450 + 0, 187500000), 1451 1451 FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m", 1452 - NULL, CLK_IS_ROOT, 24000000), 1452 + NULL, 0, 24000000), 1453 1453 FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL, 1454 - CLK_IS_ROOT, 135000000), 1454 + 0, 135000000), 1455 1455 FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0, 1456 - "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 1457 - CLK_IS_ROOT, 20000000), 1456 + "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 0, 20000000), 1458 1457 FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock", 1459 - NULL, CLK_IS_ROOT, 60000000), 1458 + NULL, 0, 60000000), 1460 1459 FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk", 1461 - NULL, CLK_IS_ROOT, 60000000), 1460 + NULL, 0, 60000000), 1462 1461 FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI, 1463 - "phyclk_usbhost20_phy_clk48mohci", 1464 - NULL, CLK_IS_ROOT, 48000000), 1462 + "phyclk_usbhost20_phy_clk48mohci", NULL, 0, 48000000), 1465 1463 FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, 1466 - "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 1467 - CLK_IS_ROOT, 125000000), 1464 + "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 0, 125000000), 1468 1465 FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK, 1469 - "phyclk_usbdrd30_udrd30_phyclock", NULL, 1470 - CLK_IS_ROOT, 60000000), 1466 + "phyclk_usbdrd30_udrd30_phyclock", NULL, 0, 60000000), 1471 1467 }; 1472 1468 1473 1469 PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"};

+6 -6

drivers/clk/samsung/clk-exynos5420.c

··· 480 480 /* fixed rate clocks generated outside the soc */ 481 481 static struct samsung_fixed_rate_clock 482 482 exynos5x_fixed_rate_ext_clks[] __initdata = { 483 - FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 483 + FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 484 484 }; 485 485 486 486 /* fixed rate clocks generated inside the soc */ 487 487 static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = { 488 - FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 489 - FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 490 - FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 491 - FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 492 - FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 488 + FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 489 + FRATE(0, "sclk_pwi", NULL, 0, 24000000), 490 + FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 491 + FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 492 + FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 493 493 }; 494 494 495 495 static struct samsung_fixed_factor_clock

+34 -40

drivers/clk/samsung/clk-exynos5433.c

··· 224 224 225 225 static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = { 226 226 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ 227 - FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000), 228 - FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000), 227 + FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000), 228 + FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000), 229 229 /* Xi2s1SDI input clock for SPDIF */ 230 - FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000), 230 + FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000), 231 231 /* XspiCLK[4:0] input clock for SPI */ 232 - FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000), 233 - FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000), 234 - FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000), 235 - FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000), 236 - FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000), 232 + FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000), 233 + FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000), 234 + FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000), 235 + FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000), 236 + FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000), 237 237 /* Xi2s1SCLK input clock for I2S1_BCLK */ 238 - FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000), 238 + FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000), 239 239 }; 240 240 241 241 static struct samsung_mux_clock top_mux_clks[] __initdata = { ··· 1984 1984 /* PHY clocks from USBDRD30_PHY */ 1985 1985 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, 1986 1986 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, 1987 - CLK_IS_ROOT, 60000000), 1987 + 0, 60000000), 1988 1988 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY, 1989 1989 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL, 1990 - CLK_IS_ROOT, 125000000), 1990 + 0, 125000000), 1991 1991 /* PHY clocks from USBHOST30_PHY */ 1992 1992 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY, 1993 1993 "phyclk_usbhost30_uhost30_phyclock_phy", NULL, 1994 - CLK_IS_ROOT, 60000000), 1994 + 0, 60000000), 1995 1995 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY, 1996 1996 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL, 1997 - CLK_IS_ROOT, 125000000), 1997 + 0, 125000000), 1998 1998 /* PHY clocks from USBHOST20_PHY */ 1999 1999 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY, 2000 - "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT, 2001 - 60000000), 2000 + "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000), 2002 2001 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY, 2003 - "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT, 2004 - 60000000), 2002 + "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000), 2005 2003 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY, 2006 2004 "phyclk_usbhost20_phy_clk48mohci_phy", NULL, 2007 - CLK_IS_ROOT, 48000000), 2005 + 0, 48000000), 2008 2006 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY, 2009 - "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT, 2007 + "phyclk_usbhost20_phy_hsic1_phy", NULL, 0, 2010 2008 60000000), 2011 2009 /* PHY clocks from UFS_PHY */ 2012 2010 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy", 2013 - NULL, CLK_IS_ROOT, 300000000), 2011 + NULL, 0, 300000000), 2014 2012 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy", 2015 - NULL, CLK_IS_ROOT, 300000000), 2013 + NULL, 0, 300000000), 2016 2014 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy", 2017 - NULL, CLK_IS_ROOT, 300000000), 2015 + NULL, 0, 300000000), 2018 2016 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy", 2019 - NULL, CLK_IS_ROOT, 300000000), 2017 + NULL, 0, 300000000), 2020 2018 /* PHY clocks from LLI_PHY */ 2021 2019 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy", 2022 - NULL, CLK_IS_ROOT, 26000000), 2020 + NULL, 0, 26000000), 2023 2021 }; 2024 2022 2025 2023 static struct samsung_mux_clock fsys_mux_clks[] __initdata = { ··· 2546 2548 2547 2549 static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = { 2548 2550 /* PHY clocks from MIPI_DPHY1 */ 2549 - FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT, 2550 - 188000000), 2551 - FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT, 2552 - 100000000), 2551 + FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), 2552 + FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), 2553 2553 /* PHY clocks from MIPI_DPHY0 */ 2554 - FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT, 2555 - 188000000), 2556 - FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT, 2557 - 100000000), 2554 + FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000), 2555 + FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000), 2558 2556 /* PHY clocks from HDMI_PHY */ 2559 2557 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", 2560 - NULL, CLK_IS_ROOT, 300000000), 2558 + NULL, 0, 300000000), 2561 2559 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy", 2562 - NULL, CLK_IS_ROOT, 166000000), 2560 + NULL, 0, 166000000), 2563 2561 }; 2564 2562 2565 2563 static struct samsung_mux_clock disp_mux_clks[] __initdata = { ··· 2876 2882 PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; 2877 2883 2878 2884 static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = { 2879 - FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000), 2880 - FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000), 2881 - FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000), 2885 + FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000), 2886 + FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000), 2887 + FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000), 2882 2888 }; 2883 2889 2884 2890 static struct samsung_mux_clock aud_mux_clks[] __initdata = { ··· 4590 4596 4591 4597 static struct samsung_fixed_rate_clock cam0_fixed_clks[] __initdata = { 4592 4598 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy", 4593 - NULL, CLK_IS_ROOT, 100000000), 4599 + NULL, 0, 100000000), 4594 4600 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy", 4595 - NULL, CLK_IS_ROOT, 100000000), 4601 + NULL, 0, 100000000), 4596 4602 }; 4597 4603 4598 4604 static struct samsung_mux_clock cam0_mux_clks[] __initdata = { ··· 5018 5024 5019 5025 static struct samsung_fixed_rate_clock cam1_fixed_clks[] __initdata = { 5020 5026 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL, 5021 - CLK_IS_ROOT, 100000000), 5027 + 0, 100000000), 5022 5028 }; 5023 5029 5024 5030 static struct samsung_mux_clock cam1_mux_clks[] __initdata = {

+6 -6

drivers/clk/samsung/clk-exynos5440.c

··· 31 31 32 32 /* fixed rate clocks generated outside the soc */ 33 33 static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = { 34 - FRATE(0, "xtal", NULL, CLK_IS_ROOT, 0), 34 + FRATE(0, "xtal", NULL, 0, 0), 35 35 }; 36 36 37 37 /* fixed rate clocks */ 38 38 static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = { 39 - FRATE(0, "ppll", NULL, CLK_IS_ROOT, 1000000000), 40 - FRATE(0, "usb_phy0", NULL, CLK_IS_ROOT, 60000000), 41 - FRATE(0, "usb_phy1", NULL, CLK_IS_ROOT, 60000000), 42 - FRATE(0, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000), 43 - FRATE(0, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000), 39 + FRATE(0, "ppll", NULL, 0, 1000000000), 40 + FRATE(0, "usb_phy0", NULL, 0, 60000000), 41 + FRATE(0, "usb_phy1", NULL, 0, 60000000), 42 + FRATE(0, "usb_ohci12", NULL, 0, 12000000), 43 + FRATE(0, "usb_ohci48", NULL, 0, 48000000), 44 44 }; 45 45 46 46 /* fixed factor clocks */

+5 -7

drivers/clk/samsung/clk-exynos7.c

··· 894 894 895 895 /* fixed rate clocks used in the FSYS0 block */ 896 896 static struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { 897 - FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 898 - CLK_IS_ROOT, 60000000), 899 - FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 900 - CLK_IS_ROOT, 125000000), 897 + FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000), 898 + FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000), 901 899 }; 902 900 903 901 static unsigned long fsys0_clk_regs[] __initdata = { ··· 1007 1009 /* fixed rate clocks used in the FSYS1 block */ 1008 1010 static struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = { 1009 1011 FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL, 1010 - CLK_IS_ROOT, 300000000), 1012 + 0, 300000000), 1011 1013 FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL, 1012 - CLK_IS_ROOT, 300000000), 1014 + 0, 300000000), 1013 1015 FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL, 1014 - CLK_IS_ROOT, 300000000), 1016 + 0, 300000000), 1015 1017 }; 1016 1018 1017 1019 static unsigned long fsys1_clk_regs[] __initdata = {

+1 -1

drivers/clk/samsung/clk-s3c2410.c

··· 344 344 */ 345 345 #define XTI 1 346 346 struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = { 347 - FRATE(XTI, "xti", NULL, CLK_IS_ROOT, 0), 347 + FRATE(XTI, "xti", NULL, 0, 0), 348 348 }; 349 349 350 350 static void __init s3c2410_common_clk_register_fixed_ext(

+2 -2

drivers/clk/samsung/clk-s3c2412.c

··· 232 232 */ 233 233 #define XTI 1 234 234 struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = { 235 - FRATE(XTI, "xti", NULL, CLK_IS_ROOT, 0), 236 - FRATE(0, "ext", NULL, CLK_IS_ROOT, 0), 235 + FRATE(XTI, "xti", NULL, 0, 0), 236 + FRATE(0, "ext", NULL, 0, 0), 237 237 }; 238 238 239 239 static void __init s3c2412_common_clk_register_fixed_ext(

+4 -4

drivers/clk/samsung/clk-s3c2443.c

··· 371 371 * Only necessary until the devicetree-move is complete 372 372 */ 373 373 struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = { 374 - FRATE(0, "xti", NULL, CLK_IS_ROOT, 0), 375 - FRATE(0, "ext", NULL, CLK_IS_ROOT, 0), 376 - FRATE(0, "ext_i2s", NULL, CLK_IS_ROOT, 0), 377 - FRATE(0, "ext_uart", NULL, CLK_IS_ROOT, 0), 374 + FRATE(0, "xti", NULL, 0, 0), 375 + FRATE(0, "ext", NULL, 0, 0), 376 + FRATE(0, "ext_i2s", NULL, 0, 0), 377 + FRATE(0, "ext_uart", NULL, 0, 0), 378 378 }; 379 379 380 380 static void __init s3c2443_common_clk_register_fixed_ext(

+4 -4

drivers/clk/samsung/clk-s3c64xx.c

··· 176 176 177 177 /* Fixed rate clocks generated outside the SoC. */ 178 178 FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = { 179 - FRATE(0, "fin_pll", NULL, CLK_IS_ROOT, 0), 180 - FRATE(0, "xusbxti", NULL, CLK_IS_ROOT, 0), 179 + FRATE(0, "fin_pll", NULL, 0, 0), 180 + FRATE(0, "xusbxti", NULL, 0, 0), 181 181 }; 182 182 183 183 /* Fixed rate clocks generated inside the SoC. */ 184 184 FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = { 185 - FRATE(CLK27M, "clk27m", NULL, CLK_IS_ROOT, 27000000), 186 - FRATE(CLK48M, "clk48m", NULL, CLK_IS_ROOT, 48000000), 185 + FRATE(CLK27M, "clk27m", NULL, 0, 27000000), 186 + FRATE(CLK48M, "clk48m", NULL, 0, 48000000), 187 187 }; 188 188 189 189 /* List of clock muxes present on all S3C64xx SoCs. */

+5 -5

drivers/clk/samsung/clk-s5pv210.c

··· 503 503 504 504 /* S5PV210-specific fixed rate clocks generated inside the SoC. */ 505 505 static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = { 506 - FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), 507 - FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 508 - FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 509 - FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 506 + FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, 0, 27000000), 507 + FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000), 508 + FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 48000000), 509 + FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, 0, 48000000), 510 510 }; 511 511 512 512 /* S5P6442-specific fixed rate clocks generated inside the SoC. */ 513 513 static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = { 514 - FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 30000000), 514 + FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 30000000), 515 515 }; 516 516 517 517 /* Common clock dividers. */