tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: dts: Add missing omap5 secure clocks
The secure clocks on omap5 are similar to what we already have for dra7
with dra7_l4sec_clkctrl_regs and documented in the omap5432 TRM in
"Table 3-1044. CORE_CM_CORE Registers Mapping Summary".
The secure clocks are part of the l4per clock manager. As the l4per
clock manager has now two clock domains as children, let's also update
the l4per clockdomain node name to follow the "clock" node naming with
a domain specific compatible property.
Compared to omap4, omap5 has more clocks working in hardare autogating
mode.
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
+32
-2
+8
-2
arch/arm/boot/dts/omap54xx-clocks.dtsi
+8
-2
arch/arm/boot/dts/omap54xx-clocks.dtsi
···
1125
1125
#size-cells = <1>;
1126
1126
ranges = <0 0x1000 0x200>;
1127
1127
1128
-
l4per_clkctrl: clk@20 {
1129
-
compatible = "ti,clkctrl";
1128
+
l4per_clkctrl: clock@20 {
1129
+
compatible = "ti,clkctrl-l4per", "ti,clkctrl";
1130
1130
reg = <0x20 0x15c>;
1131
+
#clock-cells = <2>;
1132
+
};
1133
+
1134
+
l4sec_clkctrl: clock@1a0 {
1135
+
compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
1136
+
reg = <0x1a0 0x3c>;
1131
1137
#clock-cells = <2>;
1132
1138
};
1133
1139
};
+13
drivers/clk/ti/clk-54xx.c
+13
drivers/clk/ti/clk-54xx.c
···
301
301
{ 0 },
302
302
};
303
303
304
+
static const struct
305
+
omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = {
306
+
{ OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "" },
307
+
{ OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "" },
308
+
{ OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "" },
309
+
{ OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "" },
310
+
{ OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
311
+
{ OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "" },
312
+
{ OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
313
+
{ 0 },
314
+
};
315
+
304
316
static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
305
317
{ OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
306
318
{ OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
···
535
523
{ 0x4a008d20, omap5_l4cfg_clkctrl_regs },
536
524
{ 0x4a008e20, omap5_l3instr_clkctrl_regs },
537
525
{ 0x4a009020, omap5_l4per_clkctrl_regs },
526
+
{ 0x4a0091a0, omap5_l4_secure_clkctrl_regs },
538
527
{ 0x4a009220, omap5_iva_clkctrl_regs },
539
528
{ 0x4a009420, omap5_dss_clkctrl_regs },
540
529
{ 0x4a009520, omap5_gpu_clkctrl_regs },
+11
include/dt-bindings/clock/omap5.h
+11
include/dt-bindings/clock/omap5.h
···
87
87
#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
88
88
#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
89
89
90
+
/* l4_secure clocks */
91
+
#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0
92
+
#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
93
+
#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
94
+
#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
95
+
#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
96
+
#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
97
+
#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
98
+
#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
99
+
#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
100
+
90
101
/* iva clocks */
91
102
#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
92
103
#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)