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dt-bindings: mailbox: Convert rockchip,rk3368-mailbox to DT schema
Convert the rockchip,rk3368-mailbox binding to DT schema format. Add
the missing 'clocks' and 'clock-names' properties. Document that it's
one interrupt per mailbox channel (and there are 4 channels).
Link: https://lore.kernel.org/r/20250812181348.62137-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Documentation/devicetree/bindings/mailbox/rockchip,rk3368-mailbox.yaml
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Documentation/devicetree/bindings/mailbox/rockchip,rk3368-mailbox.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/rockchip,rk3368-mailbox.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip RK3368 Mailbox Controller
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maintainers:
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- Heiko Stuebner <heiko@sntech.de>
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description:
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The Rockchip mailbox is used by the Rockchip CPU cores to communicate
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requests to MCU processor.
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properties:
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compatible:
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const: rockchip,rk3368-mailbox
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: pclk_mailbox
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interrupts:
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description: One interrupt for each channel
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maxItems: 4
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'#mbox-cells':
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- '#mbox-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mailbox@ff6b0000 {
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compatible = "rockchip,rk3368-mailbox";
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reg = <0xff6b0000 0x1000>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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};
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Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
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Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
···
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Rockchip mailbox
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The Rockchip mailbox is used by the Rockchip CPU cores to communicate
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requests to MCU processor.
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Refer to ./mailbox.txt for generic information about mailbox device-tree
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bindings.
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Required properties:
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- compatible: should be one of the following.
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- "rockchip,rk3368-mbox" for rk3368
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: The interrupt number to the cpu. The interrupt specifier format
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depends on the interrupt controller.
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- #mbox-cells: Common mailbox binding property to identify the number
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of cells required for the mailbox specifier. Should be 1
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Example:
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--------
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/* RK3368 */
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mbox: mbox@ff6b0000 {
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compatible = "rockchip,rk3368-mailbox";
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reg = <0x0 0xff6b0000 0x0 0x1000>,
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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};