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dt-bindings: interrupt-controller: migrate MIPS CPU interrupt controller text bindings to YAML

MIPS CPU interrupt controller bindings used text format, so migrate them
to YAML.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220921072405.610739-1-sergio.paracuellos@gmail.com
Signed-off-by: Rob Herring <robh@kernel.org>

authored by

Sergio Paracuellos and committed by
Rob Herring
72271420 e7c21940

+46 -47
+46
Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: MIPS CPU Interrupt Controller 8 + 9 + description: > 10 + On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU 11 + IRQs from a devicetree file and create a irq_domain for IRQ controller. 12 + 13 + With the irq_domain in place we can describe how the 8 IRQs are wired to the 14 + platforms internal interrupt controller cascade. 15 + 16 + maintainers: 17 + - Thomas Bogendoerfer <tsbogend@alpha.franken.de> 18 + 19 + properties: 20 + compatible: 21 + const: mti,cpu-interrupt-controller 22 + 23 + '#interrupt-cells': 24 + const: 1 25 + 26 + '#address-cells': 27 + const: 0 28 + 29 + interrupt-controller: true 30 + 31 + additionalProperties: false 32 + 33 + required: 34 + - compatible 35 + - '#interrupt-cells' 36 + - '#address-cells' 37 + - interrupt-controller 38 + 39 + examples: 40 + - | 41 + interrupt-controller { 42 + compatible = "mti,cpu-interrupt-controller"; 43 + #address-cells = <0>; 44 + #interrupt-cells = <1>; 45 + interrupt-controller; 46 + };
-47
Documentation/devicetree/bindings/mips/cpu_irq.txt
··· 1 - MIPS CPU interrupt controller 2 - 3 - On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU 4 - IRQs from a devicetree file and create a irq_domain for IRQ controller. 5 - 6 - With the irq_domain in place we can describe how the 8 IRQs are wired to the 7 - platforms internal interrupt controller cascade. 8 - 9 - Below is an example of a platform describing the cascade inside the devicetree 10 - and the code used to load it inside arch_init_irq(). 11 - 12 - Required properties: 13 - - compatible : Should be "mti,cpu-interrupt-controller" 14 - 15 - Example devicetree: 16 - cpu-irq: cpu-irq { 17 - #address-cells = <0>; 18 - 19 - interrupt-controller; 20 - #interrupt-cells = <1>; 21 - 22 - compatible = "mti,cpu-interrupt-controller"; 23 - }; 24 - 25 - intc: intc@200 { 26 - compatible = "ralink,rt2880-intc"; 27 - reg = <0x200 0x100>; 28 - 29 - interrupt-controller; 30 - #interrupt-cells = <1>; 31 - 32 - interrupt-parent = <&cpu-irq>; 33 - interrupts = <2>; 34 - }; 35 - 36 - 37 - Example platform irq.c: 38 - static struct of_device_id __initdata of_irq_ids[] = { 39 - { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, 40 - { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, 41 - {}, 42 - }; 43 - 44 - void __init arch_init_irq(void) 45 - { 46 - of_irq_init(of_irq_ids); 47 - }