tjh.dev / kernel
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drm/amd/display: Add missing debug registers for DCN2/3/3.1

This commit add some missing debug registers for DPCS and RDPC debug.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rodrigo Siqueira and committed by
Alex Deucher 71dfa617 af864412

+33 -2
+24
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_offset.h
··· 24 24 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 25 25 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d 26 26 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 27 + #define mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e 28 + #define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 27 29 28 30 29 31 // addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec ··· 52 50 #define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2 53 51 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c 54 52 #define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 53 + #define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d 54 + #define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 55 55 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 56 56 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 57 57 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 ··· 124 120 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 125 121 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05 126 122 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 123 + #define mmDPCSTX1_DPCSTX_DEBUG_CONFIG 0x2a06 124 + #define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 127 125 128 126 129 127 // addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec ··· 152 146 #define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2 153 147 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14 154 148 #define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 149 + #define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15 150 + #define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 155 151 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 156 152 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 157 153 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 ··· 224 216 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 225 217 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0x2add 226 218 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 219 + #define mmDPCSTX2_DPCSTX_DEBUG_CONFIG 0x2ade 220 + #define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 227 221 228 222 229 223 // addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec ··· 252 242 #define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2 253 243 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec 254 244 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 245 + #define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed 246 + #define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 255 247 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0 256 248 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2 257 249 #define mmRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1 ··· 324 312 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 325 313 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0x2bb5 326 314 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 315 + #define mmDPCSTX3_DPCSTX_DEBUG_CONFIG 0x2bb6 316 + #define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 327 317 328 318 329 319 // addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec ··· 352 338 #define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2 353 339 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4 354 340 #define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 341 + #define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5 342 + #define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 355 343 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8 356 344 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2 357 345 #define mmRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9 ··· 424 408 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 425 409 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0x2c8d 426 410 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 411 + #define mmDPCSTX4_DPCSTX_DEBUG_CONFIG 0x2c8e 412 + #define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 427 413 428 414 429 415 // addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec ··· 452 434 #define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX 2 453 435 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c 454 436 #define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 437 + #define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0x2c9d 438 + #define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 455 439 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0 456 440 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2 457 441 #define mmRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1 ··· 524 504 #define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 525 505 #define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA 0x2d65 526 506 #define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 507 + #define mmDPCSTX5_DPCSTX_DEBUG_CONFIG 0x2d66 508 + #define mmDPCSTX5_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 527 509 528 510 529 511 // addressBlock: dpcssys_dpcs0_rdpcstx5_dispdec ··· 552 530 #define mmRDPCSTX5_RDPCSTX_CNTL2_BASE_IDX 2 553 531 #define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2d74 554 532 #define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 533 + #define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG 0x2d75 534 + #define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 555 535 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL0 0x2d78 556 536 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL0_BASE_IDX 2 557 537 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL1 0x2d79
+3 -1
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_sh_mask.h
··· 70 70 //DPCSTX0_DPCSTX_PLL_UPDATE_DATA 71 71 #define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0 72 72 #define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xFFFFFFFFL 73 - 73 + //DPCSTX0_DPCSTX_DEBUG_CONFIG 74 + #define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe 75 + #define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK 0x00004000L 74 76 75 77 // addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec 76 78 //RDPCSTX0_RDPCSTX_CNTL