tjh.dev / kernel
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clk: qcom: gcc-sc8280xp: don't use parking clk_ops for QUPs

A recent change started parking the RCG at an always on parent during
registration, something which specifically breaks handover from an early
serial console.

Quoting Stephen Boyd who fixed this issue for SM8550 [1]:

The QUPs aren't shared in a way that requires parking the RCG at
an always on parent in case some other entity turns on the clk.
The hardware is capable of setting a new frequency itself with
the DFS mode, so parking is unnecessary. Furthermore, there
aren't any GDSCs for these devices, so there isn't a possibility
of the GDSC turning on the clks for housekeeping purposes.

This wasn't a problem to mark these clks shared until we started
parking shared RCGs at clk registration time in commit
01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration").
Parking at init is actually harmful to the UART when earlycon is
used. If the device is pumping out data while the frequency
changes you'll see garbage on the serial console until the
driver can probe and actually set a proper frequency.

Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration")
Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver")
Link: https://lore.kernel.org/all/20240819233628.2074654-2-swboyd@chromium.org/ [1]
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240902070830.8535-1-johan+linaro@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by Johan Hovold and committed by Stephen Boyd 71c03a8c 538d5477

+24 -24
unified split
+24 -24
drivers/clk/qcom/gcc-sc8280xp.c
··· 1500 1500 .parent_data = gcc_parent_data_0, 1501 1501 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1502 1502 .flags = CLK_SET_RATE_PARENT, 1503 - .ops = &clk_rcg2_shared_ops, 1503 + .ops = &clk_rcg2_ops, 1504 1504 }; 1505 1505 1506 1506 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { ··· 1517 1517 .parent_data = gcc_parent_data_0, 1518 1518 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1519 1519 .flags = CLK_SET_RATE_PARENT, 1520 - .ops = &clk_rcg2_shared_ops, 1520 + .ops = &clk_rcg2_ops, 1521 1521 }; 1522 1522 1523 1523 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { ··· 1534 1534 .parent_data = gcc_parent_data_0, 1535 1535 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1536 1536 .flags = CLK_SET_RATE_PARENT, 1537 - .ops = &clk_rcg2_shared_ops, 1537 + .ops = &clk_rcg2_ops, 1538 1538 }; 1539 1539 1540 1540 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { ··· 1551 1551 .parent_data = gcc_parent_data_0, 1552 1552 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1553 1553 .flags = CLK_SET_RATE_PARENT, 1554 - .ops = &clk_rcg2_shared_ops, 1554 + .ops = &clk_rcg2_ops, 1555 1555 }; 1556 1556 1557 1557 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { ··· 1568 1568 .parent_data = gcc_parent_data_0, 1569 1569 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1570 1570 .flags = CLK_SET_RATE_PARENT, 1571 - .ops = &clk_rcg2_shared_ops, 1571 + .ops = &clk_rcg2_ops, 1572 1572 }; 1573 1573 1574 1574 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { ··· 1585 1585 .parent_data = gcc_parent_data_0, 1586 1586 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1587 1587 .flags = CLK_SET_RATE_PARENT, 1588 - .ops = &clk_rcg2_shared_ops, 1588 + .ops = &clk_rcg2_ops, 1589 1589 }; 1590 1590 1591 1591 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { ··· 1617 1617 .parent_data = gcc_parent_data_0, 1618 1618 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1619 1619 .flags = CLK_SET_RATE_PARENT, 1620 - .ops = &clk_rcg2_shared_ops, 1620 + .ops = &clk_rcg2_ops, 1621 1621 }; 1622 1622 1623 1623 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { ··· 1634 1634 .parent_data = gcc_parent_data_0, 1635 1635 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1636 1636 .flags = CLK_SET_RATE_PARENT, 1637 - .ops = &clk_rcg2_shared_ops, 1637 + .ops = &clk_rcg2_ops, 1638 1638 }; 1639 1639 1640 1640 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { ··· 1651 1651 .parent_data = gcc_parent_data_0, 1652 1652 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1653 1653 .flags = CLK_SET_RATE_PARENT, 1654 - .ops = &clk_rcg2_shared_ops, 1654 + .ops = &clk_rcg2_ops, 1655 1655 }; 1656 1656 1657 1657 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { ··· 1668 1668 .parent_data = gcc_parent_data_0, 1669 1669 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1670 1670 .flags = CLK_SET_RATE_PARENT, 1671 - .ops = &clk_rcg2_shared_ops, 1671 + .ops = &clk_rcg2_ops, 1672 1672 }; 1673 1673 1674 1674 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { ··· 1685 1685 .parent_data = gcc_parent_data_0, 1686 1686 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1687 1687 .flags = CLK_SET_RATE_PARENT, 1688 - .ops = &clk_rcg2_shared_ops, 1688 + .ops = &clk_rcg2_ops, 1689 1689 }; 1690 1690 1691 1691 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { ··· 1702 1702 .parent_data = gcc_parent_data_0, 1703 1703 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1704 1704 .flags = CLK_SET_RATE_PARENT, 1705 - .ops = &clk_rcg2_shared_ops, 1705 + .ops = &clk_rcg2_ops, 1706 1706 }; 1707 1707 1708 1708 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { ··· 1719 1719 .parent_data = gcc_parent_data_0, 1720 1720 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1721 1721 .flags = CLK_SET_RATE_PARENT, 1722 - .ops = &clk_rcg2_shared_ops, 1722 + .ops = &clk_rcg2_ops, 1723 1723 }; 1724 1724 1725 1725 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { ··· 1736 1736 .parent_data = gcc_parent_data_0, 1737 1737 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1738 1738 .flags = CLK_SET_RATE_PARENT, 1739 - .ops = &clk_rcg2_shared_ops, 1739 + .ops = &clk_rcg2_ops, 1740 1740 }; 1741 1741 1742 1742 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { ··· 1753 1753 .parent_data = gcc_parent_data_0, 1754 1754 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1755 1755 .flags = CLK_SET_RATE_PARENT, 1756 - .ops = &clk_rcg2_shared_ops, 1756 + .ops = &clk_rcg2_ops, 1757 1757 }; 1758 1758 1759 1759 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { ··· 1770 1770 .parent_data = gcc_parent_data_0, 1771 1771 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1772 1772 .flags = CLK_SET_RATE_PARENT, 1773 - .ops = &clk_rcg2_shared_ops, 1773 + .ops = &clk_rcg2_ops, 1774 1774 }; 1775 1775 1776 1776 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { ··· 1787 1787 .parent_data = gcc_parent_data_0, 1788 1788 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1789 1789 .flags = CLK_SET_RATE_PARENT, 1790 - .ops = &clk_rcg2_shared_ops, 1790 + .ops = &clk_rcg2_ops, 1791 1791 }; 1792 1792 1793 1793 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { ··· 1804 1804 .parent_data = gcc_parent_data_0, 1805 1805 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1806 1806 .flags = CLK_SET_RATE_PARENT, 1807 - .ops = &clk_rcg2_shared_ops, 1807 + .ops = &clk_rcg2_ops, 1808 1808 }; 1809 1809 1810 1810 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { ··· 1821 1821 .parent_data = gcc_parent_data_0, 1822 1822 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1823 1823 .flags = CLK_SET_RATE_PARENT, 1824 - .ops = &clk_rcg2_shared_ops, 1824 + .ops = &clk_rcg2_ops, 1825 1825 }; 1826 1826 1827 1827 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { ··· 1838 1838 .parent_data = gcc_parent_data_0, 1839 1839 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1840 1840 .flags = CLK_SET_RATE_PARENT, 1841 - .ops = &clk_rcg2_shared_ops, 1841 + .ops = &clk_rcg2_ops, 1842 1842 }; 1843 1843 1844 1844 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { ··· 1855 1855 .parent_data = gcc_parent_data_0, 1856 1856 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1857 1857 .flags = CLK_SET_RATE_PARENT, 1858 - .ops = &clk_rcg2_shared_ops, 1858 + .ops = &clk_rcg2_ops, 1859 1859 }; 1860 1860 1861 1861 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { ··· 1872 1872 .parent_data = gcc_parent_data_0, 1873 1873 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1874 1874 .flags = CLK_SET_RATE_PARENT, 1875 - .ops = &clk_rcg2_shared_ops, 1875 + .ops = &clk_rcg2_ops, 1876 1876 }; 1877 1877 1878 1878 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { ··· 1889 1889 .parent_data = gcc_parent_data_0, 1890 1890 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1891 1891 .flags = CLK_SET_RATE_PARENT, 1892 - .ops = &clk_rcg2_shared_ops, 1892 + .ops = &clk_rcg2_ops, 1893 1893 }; 1894 1894 1895 1895 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { ··· 1906 1906 .parent_data = gcc_parent_data_0, 1907 1907 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1908 1908 .flags = CLK_SET_RATE_PARENT, 1909 - .ops = &clk_rcg2_shared_ops, 1909 + .ops = &clk_rcg2_ops, 1910 1910 }; 1911 1911 1912 1912 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {