[IA64] Allow /proc/pal/cpu0/vm_info under the simulator

Not all of the PAL VM calls are implemented for the SKI simulator.
Don't just give up if one fails, print information from the calls
that succeed.

Signed-off-by: Peter Chubb <peterc@gelato.unsw.edu.au>
Signed-off-by: Tony Luck <tony.luck@intel.com>

authored by

Peter Chubb and committed by
Tony Luck
714d2dc1 dc90e95f

+66 -61
+66 -61
arch/ia64/kernel/palinfo.c
··· 307 307 308 308 if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) { 309 309 printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status); 310 - return 0; 311 - } 310 + } else { 312 311 313 - 314 - p += sprintf(p, 312 + p += sprintf(p, 315 313 "Physical Address Space : %d bits\n" 316 314 "Virtual Address Space : %d bits\n" 317 315 "Protection Key Registers(PKR) : %d\n" ··· 317 319 "Hash Tag ID : 0x%x\n" 318 320 "Size of RR.rid : %d\n", 319 321 vm_info_1.pal_vm_info_1_s.phys_add_size, 320 - vm_info_2.pal_vm_info_2_s.impl_va_msb+1, vm_info_1.pal_vm_info_1_s.max_pkr+1, 321 - vm_info_1.pal_vm_info_1_s.key_size, vm_info_1.pal_vm_info_1_s.hash_tag_id, 322 + vm_info_2.pal_vm_info_2_s.impl_va_msb+1, 323 + vm_info_1.pal_vm_info_1_s.max_pkr+1, 324 + vm_info_1.pal_vm_info_1_s.key_size, 325 + vm_info_1.pal_vm_info_1_s.hash_tag_id, 322 326 vm_info_2.pal_vm_info_2_s.rid_size); 323 - 324 - if (ia64_pal_mem_attrib(&attrib) != 0) 325 - return 0; 326 - 327 - p += sprintf(p, "Supported memory attributes : "); 328 - sep = ""; 329 - for (i = 0; i < 8; i++) { 330 - if (attrib & (1 << i)) { 331 - p += sprintf(p, "%s%s", sep, mem_attrib[i]); 332 - sep = ", "; 333 - } 334 327 } 335 - p += sprintf(p, "\n"); 328 + 329 + if (ia64_pal_mem_attrib(&attrib) == 0) { 330 + p += sprintf(p, "Supported memory attributes : "); 331 + sep = ""; 332 + for (i = 0; i < 8; i++) { 333 + if (attrib & (1 << i)) { 334 + p += sprintf(p, "%s%s", sep, mem_attrib[i]); 335 + sep = ", "; 336 + } 337 + } 338 + p += sprintf(p, "\n"); 339 + } 336 340 337 341 if ((status = ia64_pal_vm_page_size(&tr_pages, &vw_pages)) !=0) { 338 342 printk(KERN_ERR "ia64_pal_vm_page_size=%ld\n", status); 339 - return 0; 343 + } else { 344 + 345 + p += sprintf(p, 346 + "\nTLB walker : %simplemented\n" 347 + "Number of DTR : %d\n" 348 + "Number of ITR : %d\n" 349 + "TLB insertable page sizes : ", 350 + vm_info_1.pal_vm_info_1_s.vw ? "" : "not ", 351 + vm_info_1.pal_vm_info_1_s.max_dtr_entry+1, 352 + vm_info_1.pal_vm_info_1_s.max_itr_entry+1); 353 + 354 + 355 + p = bitvector_process(p, tr_pages); 356 + 357 + p += sprintf(p, "\nTLB purgeable page sizes : "); 358 + 359 + p = bitvector_process(p, vw_pages); 340 360 } 341 - 342 - p += sprintf(p, 343 - "\nTLB walker : %simplemented\n" 344 - "Number of DTR : %d\n" 345 - "Number of ITR : %d\n" 346 - "TLB insertable page sizes : ", 347 - vm_info_1.pal_vm_info_1_s.vw ? "" : "not ", 348 - vm_info_1.pal_vm_info_1_s.max_dtr_entry+1, 349 - vm_info_1.pal_vm_info_1_s.max_itr_entry+1); 350 - 351 - 352 - p = bitvector_process(p, tr_pages); 353 - 354 - p += sprintf(p, "\nTLB purgeable page sizes : "); 355 - 356 - p = bitvector_process(p, vw_pages); 357 - 358 361 if ((status=ia64_get_ptce(&ptce)) != 0) { 359 362 printk(KERN_ERR "ia64_get_ptce=%ld\n", status); 360 - return 0; 361 - } 362 - 363 - p += sprintf(p, 363 + } else { 364 + p += sprintf(p, 364 365 "\nPurge base address : 0x%016lx\n" 365 366 "Purge outer loop count : %d\n" 366 367 "Purge inner loop count : %d\n" 367 368 "Purge outer loop stride : %d\n" 368 369 "Purge inner loop stride : %d\n", 369 - ptce.base, ptce.count[0], ptce.count[1], ptce.stride[0], ptce.stride[1]); 370 + ptce.base, ptce.count[0], ptce.count[1], 371 + ptce.stride[0], ptce.stride[1]); 370 372 371 - p += sprintf(p, 373 + p += sprintf(p, 372 374 "TC Levels : %d\n" 373 375 "Unique TC(s) : %d\n", 374 376 vm_info_1.pal_vm_info_1_s.num_tc_levels, 375 377 vm_info_1.pal_vm_info_1_s.max_unique_tcs); 376 378 377 - for(i=0; i < vm_info_1.pal_vm_info_1_s.num_tc_levels; i++) { 378 - for (j=2; j>0 ; j--) { 379 - tc_pages = 0; /* just in case */ 379 + for(i=0; i < vm_info_1.pal_vm_info_1_s.num_tc_levels; i++) { 380 + for (j=2; j>0 ; j--) { 381 + tc_pages = 0; /* just in case */ 380 382 381 383 382 - /* even without unification, some levels may not be present */ 383 - if ((status=ia64_pal_vm_info(i,j, &tc_info, &tc_pages)) != 0) { 384 - continue; 385 - } 384 + /* even without unification, some levels may not be present */ 385 + if ((status=ia64_pal_vm_info(i,j, &tc_info, &tc_pages)) != 0) { 386 + continue; 387 + } 386 388 387 - p += sprintf(p, 389 + p += sprintf(p, 388 390 "\n%s Translation Cache Level %d:\n" 389 391 "\tHash sets : %d\n" 390 392 "\tAssociativity : %d\n" 391 393 "\tNumber of entries : %d\n" 392 394 "\tFlags : ", 393 - cache_types[j+tc_info.tc_unified], i+1, tc_info.tc_num_sets, 394 - tc_info.tc_associativity, tc_info.tc_num_entries); 395 + cache_types[j+tc_info.tc_unified], i+1, 396 + tc_info.tc_num_sets, 397 + tc_info.tc_associativity, 398 + tc_info.tc_num_entries); 395 399 396 - if (tc_info.tc_pf) p += sprintf(p, "PreferredPageSizeOptimized "); 397 - if (tc_info.tc_unified) p += sprintf(p, "Unified "); 398 - if (tc_info.tc_reduce_tr) p += sprintf(p, "TCReduction"); 400 + if (tc_info.tc_pf) 401 + p += sprintf(p, "PreferredPageSizeOptimized "); 402 + if (tc_info.tc_unified) 403 + p += sprintf(p, "Unified "); 404 + if (tc_info.tc_reduce_tr) 405 + p += sprintf(p, "TCReduction"); 399 406 400 - p += sprintf(p, "\n\tSupported page sizes: "); 407 + p += sprintf(p, "\n\tSupported page sizes: "); 401 408 402 - p = bitvector_process(p, tc_pages); 409 + p = bitvector_process(p, tc_pages); 403 410 404 - /* when unified date (j=2) is enough */ 405 - if (tc_info.tc_unified) break; 411 + /* when unified date (j=2) is enough */ 412 + if (tc_info.tc_unified) 413 + break; 414 + } 406 415 } 407 416 } 408 417 p += sprintf(p, "\n"); ··· 445 440 p += sprintf(p, "\n"); 446 441 } 447 442 448 - if (ia64_pal_rse_info(&phys_stacked, &hints) != 0) return 0; 443 + if (ia64_pal_rse_info(&phys_stacked, &hints) == 0) { 449 444 450 445 p += sprintf(p, 451 446 "RSE stacked physical registers : %ld\n" 452 447 "RSE load/store hints : %ld (%s)\n", 453 448 phys_stacked, hints.ph_data, 454 449 hints.ph_data < RSE_HINTS_COUNT ? rse_hints[hints.ph_data]: "(??)"); 455 - 450 + } 456 451 if (ia64_pal_debug_info(&iregs, &dregs)) 457 452 return 0; 458 453