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dt-bindings: dma: Convert stm32 MDMA bindings to json-schema

Convert the STM32 MDMA binding to DT schema format using json-schema

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Rob Herring <robh@kernel.org>

authored by

Benjamin Gaignard and committed by
Rob Herring
71021f3f b80103f6

+105 -94
+105
Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: STMicroelectronics STM32 MDMA Controller bindings 8 + 9 + description: | 10 + The STM32 MDMA is a general-purpose direct memory access controller capable of 11 + supporting 64 independent DMA channels with 256 HW requests. 12 + DMA clients connected to the STM32 MDMA controller must use the format 13 + described in the dma.txt file, using a five-cell specifier for each channel: 14 + a phandle to the MDMA controller plus the following five integer cells: 15 + 1. The request line number 16 + 2. The priority level 17 + 0x0: Low 18 + 0x1: Medium 19 + 0x2: High 20 + 0x3: Very high 21 + 3. A 32bit mask specifying the DMA channel configuration 22 + -bit 0-1: Source increment mode 23 + 0x0: Source address pointer is fixed 24 + 0x2: Source address pointer is incremented after each data transfer 25 + 0x3: Source address pointer is decremented after each data transfer 26 + -bit 2-3: Destination increment mode 27 + 0x0: Destination address pointer is fixed 28 + 0x2: Destination address pointer is incremented after each data transfer 29 + 0x3: Destination address pointer is decremented after each data transfer 30 + -bit 8-9: Source increment offset size 31 + 0x0: byte (8bit) 32 + 0x1: half-word (16bit) 33 + 0x2: word (32bit) 34 + 0x3: double-word (64bit) 35 + -bit 10-11: Destination increment offset size 36 + 0x0: byte (8bit) 37 + 0x1: half-word (16bit) 38 + 0x2: word (32bit) 39 + 0x3: double-word (64bit) 40 + -bit 25-18: The number of bytes to be transferred in a single transfer 41 + (min = 1 byte, max = 128 bytes) 42 + -bit 29:28: Trigger Mode 43 + 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes) 44 + 0x1: Each MDMA request triggers a block transfer (max 64K bytes) 45 + 0x2: Each MDMA request triggers a repeated block transfer 46 + 0x3: Each MDMA request triggers a linked list transfer 47 + 4. A 32bit value specifying the register to be used to acknowledge the request 48 + if no HW ack signal is used by the MDMA client 49 + 5. A 32bit mask specifying the value to be written to acknowledge the request 50 + if no HW ack signal is used by the MDMA client 51 + 52 + maintainers: 53 + - Amelie Delaunay <amelie.delaunay@st.com> 54 + 55 + allOf: 56 + - $ref: "dma-controller.yaml#" 57 + 58 + properties: 59 + "#dma-cells": 60 + const: 5 61 + 62 + compatible: 63 + const: st,stm32h7-mdma 64 + 65 + reg: 66 + maxItems: 1 67 + 68 + clocks: 69 + maxItems: 1 70 + 71 + interrupts: 72 + maxItems: 1 73 + 74 + resets: 75 + maxItems: 1 76 + 77 + st,ahb-addr-masks: 78 + $ref: /schemas/types.yaml#/definitions/uint32-array 79 + description: Array of u32 mask to list memory devices addressed via AHB bus. 80 + 81 + required: 82 + - compatible 83 + - reg 84 + - clocks 85 + - interrupts 86 + 87 + examples: 88 + - | 89 + #include <dt-bindings/interrupt-controller/arm-gic.h> 90 + #include <dt-bindings/clock/stm32mp1-clks.h> 91 + #include <dt-bindings/reset/stm32mp1-resets.h> 92 + dma-controller@52000000 { 93 + compatible = "st,stm32h7-mdma"; 94 + reg = <0x52000000 0x1000>; 95 + interrupts = <122>; 96 + clocks = <&timer_clk>; 97 + resets = <&rcc 992>; 98 + #dma-cells = <5>; 99 + dma-channels = <16>; 100 + dma-requests = <32>; 101 + st,ahb-addr-masks = <0x20000000>, <0x00000000>; 102 + }; 103 + 104 + ... 105 +
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Documentation/devicetree/bindings/dma/stm32-mdma.txt
··· 1 - * STMicroelectronics STM32 MDMA controller 2 - 3 - The STM32 MDMA is a general-purpose direct memory access controller capable of 4 - supporting 64 independent DMA channels with 256 HW requests. 5 - 6 - Required properties: 7 - - compatible: Should be "st,stm32h7-mdma" 8 - - reg: Should contain MDMA registers location and length. This should include 9 - all of the per-channel registers. 10 - - interrupts: Should contain the MDMA interrupt. 11 - - clocks: Should contain the input clock of the DMA instance. 12 - - resets: Reference to a reset controller asserting the DMA controller. 13 - - #dma-cells : Must be <5>. See DMA client paragraph for more details. 14 - 15 - Optional properties: 16 - - dma-channels: Number of DMA channels supported by the controller. 17 - - dma-requests: Number of DMA request signals supported by the controller. 18 - - st,ahb-addr-masks: Array of u32 mask to list memory devices addressed via 19 - AHB bus. 20 - 21 - Example: 22 - 23 - mdma1: dma@52000000 { 24 - compatible = "st,stm32h7-mdma"; 25 - reg = <0x52000000 0x1000>; 26 - interrupts = <122>; 27 - clocks = <&timer_clk>; 28 - resets = <&rcc 992>; 29 - #dma-cells = <5>; 30 - dma-channels = <16>; 31 - dma-requests = <32>; 32 - st,ahb-addr-masks = <0x20000000>, <0x00000000>; 33 - }; 34 - 35 - * DMA client 36 - 37 - DMA clients connected to the STM32 MDMA controller must use the format 38 - described in the dma.txt file, using a five-cell specifier for each channel: 39 - a phandle to the MDMA controller plus the following five integer cells: 40 - 41 - 1. The request line number 42 - 2. The priority level 43 - 0x00: Low 44 - 0x01: Medium 45 - 0x10: High 46 - 0x11: Very high 47 - 3. A 32bit mask specifying the DMA channel configuration 48 - -bit 0-1: Source increment mode 49 - 0x00: Source address pointer is fixed 50 - 0x10: Source address pointer is incremented after each data transfer 51 - 0x11: Source address pointer is decremented after each data transfer 52 - -bit 2-3: Destination increment mode 53 - 0x00: Destination address pointer is fixed 54 - 0x10: Destination address pointer is incremented after each data 55 - transfer 56 - 0x11: Destination address pointer is decremented after each data 57 - transfer 58 - -bit 8-9: Source increment offset size 59 - 0x00: byte (8bit) 60 - 0x01: half-word (16bit) 61 - 0x10: word (32bit) 62 - 0x11: double-word (64bit) 63 - -bit 10-11: Destination increment offset size 64 - 0x00: byte (8bit) 65 - 0x01: half-word (16bit) 66 - 0x10: word (32bit) 67 - 0x11: double-word (64bit) 68 - -bit 25-18: The number of bytes to be transferred in a single transfer 69 - (min = 1 byte, max = 128 bytes) 70 - -bit 29:28: Trigger Mode 71 - 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes) 72 - 0x01: Each MDMA request triggers a block transfer (max 64K bytes) 73 - 0x10: Each MDMA request triggers a repeated block transfer 74 - 0x11: Each MDMA request triggers a linked list transfer 75 - 4. A 32bit value specifying the register to be used to acknowledge the request 76 - if no HW ack signal is used by the MDMA client 77 - 5. A 32bit mask specifying the value to be written to acknowledge the request 78 - if no HW ack signal is used by the MDMA client 79 - 80 - Example: 81 - 82 - i2c4: i2c@5c002000 { 83 - compatible = "st,stm32f7-i2c"; 84 - reg = <0x5c002000 0x400>; 85 - interrupts = <95>, 86 - <96>; 87 - clocks = <&timer_clk>; 88 - #address-cells = <1>; 89 - #size-cells = <0>; 90 - dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>, 91 - <&mdma1 37 0x0 0x40002 0x0 0x0>; 92 - dma-names = "rx", "tx"; 93 - status = "disabled"; 94 - };