powerpc/8xx: Use patch_site for perf counters setup

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

The 8xx TLB miss routines are patched when (de)activating
perf counters.

This patch uses the new patch_site functionality in order
to get a better code readability and avoid a label mess when
dumping the code with 'objdump -d'

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

authored by

Christophe Leroy and committed by

Michael Ellerman 7 years ago 709cf19c 1a210878

+35 -29

3 changed files

expand all

arch

powerpc

include

asm

mmu-8xx.h

kernel

head_8xx.S

perf

8xx-pmu.c

arch/powerpc/include/asm/mmu-8xx.h

··· 234 234 extern s32 patch__dtlbmiss_linmem_top, patch__dtlbmiss_immr_jmp; 235 235 extern s32 patch__fixupdar_linmem_top; 236 236 237 + extern s32 patch__itlbmiss_exit_1, patch__itlbmiss_exit_2; 238 + extern s32 patch__dtlbmiss_exit_1, patch__dtlbmiss_exit_2, patch__dtlbmiss_exit_3; 239 + extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf; 240 + 237 241 #endif /* !__ASSEMBLY__ */ 238 242 239 243 #if defined(CONFIG_PPC_4K_PAGES)

+19 -14

arch/powerpc/kernel/head_8xx.S

··· 374 374 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 375 375 376 376 /* Restore registers */ 377 - _ENTRY(itlb_miss_exit_1) 378 - mfspr r10, SPRN_SPRG_SCRATCH0 377 + 0: mfspr r10, SPRN_SPRG_SCRATCH0 379 378 mfspr r11, SPRN_SPRG_SCRATCH1 380 379 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 381 380 mfspr r12, SPRN_SPRG_SCRATCH2 382 381 #endif 383 382 rfi 383 + patch_site 0b, patch__itlbmiss_exit_1 384 + 384 385 #ifdef CONFIG_PERF_EVENTS 385 - _ENTRY(itlb_miss_perf) 386 - lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha 386 + patch_site 0f, patch__itlbmiss_perf 387 + 0: lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha 387 388 lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) 388 389 addi r11, r11, 1 389 390 stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) ··· 500 499 501 500 /* Restore registers */ 502 501 mtspr SPRN_DAR, r11 /* Tag DAR */ 503 - _ENTRY(dtlb_miss_exit_1) 504 - mfspr r10, SPRN_SPRG_SCRATCH0 502 + 503 + 0: mfspr r10, SPRN_SPRG_SCRATCH0 505 504 mfspr r11, SPRN_SPRG_SCRATCH1 506 505 mfspr r12, SPRN_SPRG_SCRATCH2 507 506 rfi 507 + patch_site 0b, patch__dtlbmiss_exit_1 508 + 508 509 #ifdef CONFIG_PERF_EVENTS 509 - _ENTRY(dtlb_miss_perf) 510 - lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha 510 + patch_site 0f, patch__dtlbmiss_perf 511 + 0: lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha 511 512 lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) 512 513 addi r11, r11, 1 513 514 stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) ··· 661 658 662 659 li r11, RPN_PATTERN 663 660 mtspr SPRN_DAR, r11 /* Tag DAR */ 664 - _ENTRY(dtlb_miss_exit_2) 665 - mfspr r10, SPRN_SPRG_SCRATCH0 661 + 662 + 0: mfspr r10, SPRN_SPRG_SCRATCH0 666 663 mfspr r11, SPRN_SPRG_SCRATCH1 667 664 mfspr r12, SPRN_SPRG_SCRATCH2 668 665 rfi 666 + patch_site 0b, patch__dtlbmiss_exit_2 669 667 670 668 DTLBMissLinear: 671 669 mtcr r12 ··· 680 676 681 677 li r11, RPN_PATTERN 682 678 mtspr SPRN_DAR, r11 /* Tag DAR */ 683 - _ENTRY(dtlb_miss_exit_3) 684 - mfspr r10, SPRN_SPRG_SCRATCH0 679 + 680 + 0: mfspr r10, SPRN_SPRG_SCRATCH0 685 681 mfspr r11, SPRN_SPRG_SCRATCH1 686 682 mfspr r12, SPRN_SPRG_SCRATCH2 687 683 rfi 684 + patch_site 0b, patch__dtlbmiss_exit_3 688 685 689 686 #ifndef CONFIG_PIN_TLB_TEXT 690 687 ITLBMissLinear: ··· 698 693 _PAGE_PRESENT 699 694 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 700 695 701 - _ENTRY(itlb_miss_exit_2) 702 - mfspr r10, SPRN_SPRG_SCRATCH0 696 + 0: mfspr r10, SPRN_SPRG_SCRATCH0 703 697 mfspr r11, SPRN_SPRG_SCRATCH1 704 698 mfspr r12, SPRN_SPRG_SCRATCH2 705 699 rfi 700 + patch_site 0b, patch__itlbmiss_exit_2 706 701 #endif 707 702 708 703 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions

+12 -15

arch/powerpc/perf/8xx-pmu.c

··· 31 31 32 32 extern unsigned long itlb_miss_counter, dtlb_miss_counter; 33 33 extern atomic_t instruction_counter; 34 - extern unsigned int itlb_miss_perf, dtlb_miss_perf; 35 - extern unsigned int itlb_miss_exit_1, itlb_miss_exit_2; 36 - extern unsigned int dtlb_miss_exit_1, dtlb_miss_exit_2, dtlb_miss_exit_3; 37 34 38 35 static atomic_t insn_ctr_ref; 39 36 static atomic_t itlb_miss_ref; ··· 100 103 break; 101 104 case PERF_8xx_ID_ITLB_LOAD_MISS: 102 105 if (atomic_inc_return(&itlb_miss_ref) == 1) { 103 - unsigned long target = (unsigned long)&itlb_miss_perf; 106 + unsigned long target = patch_site_addr(&patch__itlbmiss_perf); 104 107 105 - patch_branch(&itlb_miss_exit_1, target, 0); 108 + patch_branch_site(&patch__itlbmiss_exit_1, target, 0); 106 109 #ifndef CONFIG_PIN_TLB_TEXT 107 - patch_branch(&itlb_miss_exit_2, target, 0); 110 + patch_branch_site(&patch__itlbmiss_exit_2, target, 0); 108 111 #endif 109 112 } 110 113 val = itlb_miss_counter; 111 114 break; 112 115 case PERF_8xx_ID_DTLB_LOAD_MISS: 113 116 if (atomic_inc_return(&dtlb_miss_ref) == 1) { 114 - unsigned long target = (unsigned long)&dtlb_miss_perf; 117 + unsigned long target = patch_site_addr(&patch__dtlbmiss_perf); 115 118 116 - patch_branch(&dtlb_miss_exit_1, target, 0); 117 - patch_branch(&dtlb_miss_exit_2, target, 0); 118 - patch_branch(&dtlb_miss_exit_3, target, 0); 119 + patch_branch_site(&patch__dtlbmiss_exit_1, target, 0); 120 + patch_branch_site(&patch__dtlbmiss_exit_2, target, 0); 121 + patch_branch_site(&patch__dtlbmiss_exit_3, target, 0); 119 122 } 120 123 val = dtlb_miss_counter; 121 124 break; ··· 177 180 break; 178 181 case PERF_8xx_ID_ITLB_LOAD_MISS: 179 182 if (atomic_dec_return(&itlb_miss_ref) == 0) { 180 - patch_instruction(&itlb_miss_exit_1, insn); 183 + patch_instruction_site(&patch__itlbmiss_exit_1, insn); 181 184 #ifndef CONFIG_PIN_TLB_TEXT 182 - patch_instruction(&itlb_miss_exit_2, insn); 185 + patch_instruction_site(&patch__itlbmiss_exit_2, insn); 183 186 #endif 184 187 } 185 188 break; 186 189 case PERF_8xx_ID_DTLB_LOAD_MISS: 187 190 if (atomic_dec_return(&dtlb_miss_ref) == 0) { 188 - patch_instruction(&dtlb_miss_exit_1, insn); 189 - patch_instruction(&dtlb_miss_exit_2, insn); 190 - patch_instruction(&dtlb_miss_exit_3, insn); 191 + patch_instruction_site(&patch__dtlbmiss_exit_1, insn); 192 + patch_instruction_site(&patch__dtlbmiss_exit_2, insn); 193 + patch_instruction_site(&patch__dtlbmiss_exit_3, insn); 191 194 } 192 195 break; 193 196 }