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[ARM] 4498/1: ARMv7: Remove the L2 cache configuration via the aux ctrl register

The auxiliary control and the L2 auxiliary control registers are
Cortex-A8 specific. They need to be removed from the generic ARMv7
support code.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

authored by Catalin Marinas and committed by Russell King 7092fc38 69ebb222

-16
unified split
-6
arch/arm/mm/Kconfig
··· 612 612 Say Y here to use the predictable round-robin cache replacement 613 613 policy. Unless you specifically require this or are unsure, say N. 614 614 615 - config CPU_L2CACHE_DISABLE 616 - bool "Disable level 2 cache" 617 - depends on CPU_V7 618 - help 619 - Say Y here to disable the level 2 cache. If unsure, say N. 620 - 621 615 config CPU_BPREDICT_DISABLE 622 616 bool "Disable branch prediction" 623 617 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
-10
arch/arm/mm/proc-v7.S
··· 176 176 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 177 177 mov r10, #0x1f @ domains 0, 1 = manager 178 178 mcr p15, 0, r10, c3, c0, 0 @ load domain access register 179 - #ifndef CONFIG_CPU_L2CACHE_DISABLE 180 - @ L2 cache configuration in the L2 aux control register 181 - mrc p15, 1, r10, c9, c0, 2 182 - bic r10, r10, #(1 << 16) @ L2 outer cache 183 - mcr p15, 1, r10, c9, c0, 2 184 - @ L2 cache is enabled in the aux control register 185 - mrc p15, 0, r10, c1, c0, 1 186 - orr r10, r10, #2 187 - mcr p15, 0, r10, c1, c0, 1 188 - #endif 189 179 mrc p15, 0, r0, c1, c0, 0 @ read control register 190 180 ldr r10, cr1_clear @ get mask for bits to clear 191 181 bic r0, r0, r10 @ clear bits them