LoongArch: Adjust common macro definitions for 32BIT/64BIT

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Most common macros are defined in asm.h, asmmacro.h and stackframe.h.
Adjust these macros for both 32BIT and 64BIT.

Add SETUP_TWINS (Setup Trampoline Windows) and SETUP_MODES (Setup CRMD/
PRMD/EUEN) which will be used later.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

Huacai Chen 4 months ago 708ed32c 81f5d15c

+174 -55

3 changed files

expand all

arch

loongarch

include

asm

asm.h

asmmacro.h

stackframe.h

+57 -20

arch/loongarch/include/asm/asm.h

··· 72 72 #define INT_SUB sub.w 73 73 #define INT_L ld.w 74 74 #define INT_S st.w 75 - #define INT_SLL slli.w 75 + #define INT_SLLI slli.w 76 76 #define INT_SLLV sll.w 77 - #define INT_SRL srli.w 77 + #define INT_SRLI srli.w 78 78 #define INT_SRLV srl.w 79 - #define INT_SRA srai.w 79 + #define INT_SRAI srai.w 80 80 #define INT_SRAV sra.w 81 81 #endif 82 82 ··· 86 86 #define INT_SUB sub.d 87 87 #define INT_L ld.d 88 88 #define INT_S st.d 89 - #define INT_SLL slli.d 89 + #define INT_SLLI slli.d 90 90 #define INT_SLLV sll.d 91 - #define INT_SRL srli.d 91 + #define INT_SRLI srli.d 92 92 #define INT_SRLV srl.d 93 - #define INT_SRA srai.d 93 + #define INT_SRAI srai.d 94 94 #define INT_SRAV sra.d 95 95 #endif 96 96 ··· 100 100 #if (__SIZEOF_LONG__ == 4) 101 101 #define LONG_ADD add.w 102 102 #define LONG_ADDI addi.w 103 + #define LONG_ALSL alsl.w 104 + #define LONG_BSTRINS bstrins.w 105 + #define LONG_BSTRPICK bstrpick.w 103 106 #define LONG_SUB sub.w 104 107 #define LONG_L ld.w 108 + #define LONG_LI li.w 109 + #define LONG_LPTR ld.w 105 110 #define LONG_S st.w 106 - #define LONG_SLL slli.w 111 + #define LONG_SPTR st.w 112 + #define LONG_SLLI slli.w 107 113 #define LONG_SLLV sll.w 108 - #define LONG_SRL srli.w 114 + #define LONG_SRLI srli.w 109 115 #define LONG_SRLV srl.w 110 - #define LONG_SRA srai.w 116 + #define LONG_SRAI srai.w 111 117 #define LONG_SRAV sra.w 118 + #define LONG_ROTR rotr.w 119 + #define LONG_ROTRI rotri.w 112 120 113 121 #ifdef __ASSEMBLER__ 114 122 #define LONG .word ··· 129 121 #if (__SIZEOF_LONG__ == 8) 130 122 #define LONG_ADD add.d 131 123 #define LONG_ADDI addi.d 124 + #define LONG_ALSL alsl.d 125 + #define LONG_BSTRINS bstrins.d 126 + #define LONG_BSTRPICK bstrpick.d 132 127 #define LONG_SUB sub.d 133 128 #define LONG_L ld.d 129 + #define LONG_LI li.d 130 + #define LONG_LPTR ldptr.d 134 131 #define LONG_S st.d 135 - #define LONG_SLL slli.d 132 + #define LONG_SPTR stptr.d 133 + #define LONG_SLLI slli.d 136 134 #define LONG_SLLV sll.d 137 - #define LONG_SRL srli.d 135 + #define LONG_SRLI srli.d 138 136 #define LONG_SRLV srl.d 139 - #define LONG_SRA srai.d 137 + #define LONG_SRAI srai.d 140 138 #define LONG_SRAV sra.d 139 + #define LONG_ROTR rotr.d 140 + #define LONG_ROTRI rotri.d 141 141 142 142 #ifdef __ASSEMBLER__ 143 143 #define LONG .dword ··· 161 145 #if (__SIZEOF_POINTER__ == 4) 162 146 #define PTR_ADD add.w 163 147 #define PTR_ADDI addi.w 148 + #define PTR_ALSL alsl.w 149 + #define PTR_BSTRINS bstrins.w 150 + #define PTR_BSTRPICK bstrpick.w 164 151 #define PTR_SUB sub.w 165 152 #define PTR_L ld.w 166 - #define PTR_S st.w 167 153 #define PTR_LI li.w 168 - #define PTR_SLL slli.w 154 + #define PTR_LPTR ld.w 155 + #define PTR_S st.w 156 + #define PTR_SPTR st.w 157 + #define PTR_SLLI slli.w 169 158 #define PTR_SLLV sll.w 170 - #define PTR_SRL srli.w 159 + #define PTR_SRLI srli.w 171 160 #define PTR_SRLV srl.w 172 - #define PTR_SRA srai.w 161 + #define PTR_SRAI srai.w 173 162 #define PTR_SRAV sra.w 163 + #define PTR_ROTR rotr.w 164 + #define PTR_ROTRI rotri.w 174 165 175 166 #define PTR_SCALESHIFT 2 176 167 ··· 191 168 #if (__SIZEOF_POINTER__ == 8) 192 169 #define PTR_ADD add.d 193 170 #define PTR_ADDI addi.d 171 + #define PTR_ALSL alsl.d 172 + #define PTR_BSTRINS bstrins.d 173 + #define PTR_BSTRPICK bstrpick.d 194 174 #define PTR_SUB sub.d 195 175 #define PTR_L ld.d 196 - #define PTR_S st.d 197 176 #define PTR_LI li.d 198 - #define PTR_SLL slli.d 177 + #define PTR_LPTR ldptr.d 178 + #define PTR_S st.d 179 + #define PTR_SPTR stptr.d 180 + #define PTR_SLLI slli.d 199 181 #define PTR_SLLV sll.d 200 - #define PTR_SRL srli.d 182 + #define PTR_SRLI srli.d 201 183 #define PTR_SRLV srl.d 202 - #define PTR_SRA srai.d 184 + #define PTR_SRAI srai.d 203 185 #define PTR_SRAV sra.d 186 + #define PTR_ROTR rotr.d 187 + #define PTR_ROTRI rotri.d 204 188 205 189 #define PTR_SCALESHIFT 3 206 190 ··· 220 190 221 191 /* Annotate a function as being unsuitable for kprobes. */ 222 192 #ifdef CONFIG_KPROBES 193 + #ifdef CONFIG_32BIT 194 + #define _ASM_NOKPROBE(name) \ 195 + .pushsection "_kprobe_blacklist", "aw"; \ 196 + .long name; \ 197 + .popsection 198 + #else 223 199 #define _ASM_NOKPROBE(name) \ 224 200 .pushsection "_kprobe_blacklist", "aw"; \ 225 201 .quad name; \ 226 202 .popsection 203 + #endif 227 204 #else 228 205 #define _ASM_NOKPROBE(name) 229 206 #endif

+90 -28

arch/loongarch/include/asm/asmmacro.h

··· 5 5 #ifndef _ASM_ASMMACRO_H 6 6 #define _ASM_ASMMACRO_H 7 7 8 + #include <linux/sizes.h> 8 9 #include <asm/asm-offsets.h> 9 10 #include <asm/regdef.h> 10 11 #include <asm/fpregdef.h> 11 12 #include <asm/loongarch.h> 12 13 14 + #ifdef CONFIG_64BIT 15 + #define TASK_STRUCT_OFFSET 0 16 + #else 17 + #define TASK_STRUCT_OFFSET 2000 18 + #endif 19 + 13 20 .macro cpu_save_nonscratch thread 14 - stptr.d s0, \thread, THREAD_REG23 15 - stptr.d s1, \thread, THREAD_REG24 16 - stptr.d s2, \thread, THREAD_REG25 17 - stptr.d s3, \thread, THREAD_REG26 18 - stptr.d s4, \thread, THREAD_REG27 19 - stptr.d s5, \thread, THREAD_REG28 20 - stptr.d s6, \thread, THREAD_REG29 21 - stptr.d s7, \thread, THREAD_REG30 22 - stptr.d s8, \thread, THREAD_REG31 23 - stptr.d sp, \thread, THREAD_REG03 24 - stptr.d fp, \thread, THREAD_REG22 21 + LONG_SPTR s0, \thread, (THREAD_REG23 - TASK_STRUCT_OFFSET) 22 + LONG_SPTR s1, \thread, (THREAD_REG24 - TASK_STRUCT_OFFSET) 23 + LONG_SPTR s2, \thread, (THREAD_REG25 - TASK_STRUCT_OFFSET) 24 + LONG_SPTR s3, \thread, (THREAD_REG26 - TASK_STRUCT_OFFSET) 25 + LONG_SPTR s4, \thread, (THREAD_REG27 - TASK_STRUCT_OFFSET) 26 + LONG_SPTR s5, \thread, (THREAD_REG28 - TASK_STRUCT_OFFSET) 27 + LONG_SPTR s6, \thread, (THREAD_REG29 - TASK_STRUCT_OFFSET) 28 + LONG_SPTR s7, \thread, (THREAD_REG30 - TASK_STRUCT_OFFSET) 29 + LONG_SPTR s8, \thread, (THREAD_REG31 - TASK_STRUCT_OFFSET) 30 + LONG_SPTR ra, \thread, (THREAD_REG01 - TASK_STRUCT_OFFSET) 31 + LONG_SPTR sp, \thread, (THREAD_REG03 - TASK_STRUCT_OFFSET) 32 + LONG_SPTR fp, \thread, (THREAD_REG22 - TASK_STRUCT_OFFSET) 25 33 .endm 26 34 27 35 .macro cpu_restore_nonscratch thread 28 - ldptr.d s0, \thread, THREAD_REG23 29 - ldptr.d s1, \thread, THREAD_REG24 30 - ldptr.d s2, \thread, THREAD_REG25 31 - ldptr.d s3, \thread, THREAD_REG26 32 - ldptr.d s4, \thread, THREAD_REG27 33 - ldptr.d s5, \thread, THREAD_REG28 34 - ldptr.d s6, \thread, THREAD_REG29 35 - ldptr.d s7, \thread, THREAD_REG30 36 - ldptr.d s8, \thread, THREAD_REG31 37 - ldptr.d ra, \thread, THREAD_REG01 38 - ldptr.d sp, \thread, THREAD_REG03 39 - ldptr.d fp, \thread, THREAD_REG22 36 + LONG_LPTR s0, \thread, (THREAD_REG23 - TASK_STRUCT_OFFSET) 37 + LONG_LPTR s1, \thread, (THREAD_REG24 - TASK_STRUCT_OFFSET) 38 + LONG_LPTR s2, \thread, (THREAD_REG25 - TASK_STRUCT_OFFSET) 39 + LONG_LPTR s3, \thread, (THREAD_REG26 - TASK_STRUCT_OFFSET) 40 + LONG_LPTR s4, \thread, (THREAD_REG27 - TASK_STRUCT_OFFSET) 41 + LONG_LPTR s5, \thread, (THREAD_REG28 - TASK_STRUCT_OFFSET) 42 + LONG_LPTR s6, \thread, (THREAD_REG29 - TASK_STRUCT_OFFSET) 43 + LONG_LPTR s7, \thread, (THREAD_REG30 - TASK_STRUCT_OFFSET) 44 + LONG_LPTR s8, \thread, (THREAD_REG31 - TASK_STRUCT_OFFSET) 45 + LONG_LPTR ra, \thread, (THREAD_REG01 - TASK_STRUCT_OFFSET) 46 + LONG_LPTR sp, \thread, (THREAD_REG03 - TASK_STRUCT_OFFSET) 47 + LONG_LPTR fp, \thread, (THREAD_REG22 - TASK_STRUCT_OFFSET) 40 48 .endm 41 49 42 50 .macro fpu_save_csr thread tmp 43 51 movfcsr2gr \tmp, fcsr0 52 + #ifdef CONFIG_32BIT 53 + st.w \tmp, \thread, THREAD_FCSR 54 + #else 44 55 stptr.w \tmp, \thread, THREAD_FCSR 56 + #endif 45 57 #ifdef CONFIG_CPU_HAS_LBT 46 58 /* TM bit is always 0 if LBT not supported */ 47 59 andi \tmp, \tmp, FPU_CSR_TM ··· 68 56 .endm 69 57 70 58 .macro fpu_restore_csr thread tmp0 tmp1 59 + #ifdef CONFIG_32BIT 60 + ld.w \tmp0, \thread, THREAD_FCSR 61 + #else 71 62 ldptr.w \tmp0, \thread, THREAD_FCSR 63 + #endif 72 64 movgr2fcsr fcsr0, \tmp0 73 65 #ifdef CONFIG_CPU_HAS_LBT 74 66 /* TM bit is always 0 if LBT not supported */ ··· 104 88 #endif 105 89 .endm 106 90 91 + #ifdef CONFIG_32BIT 107 92 .macro fpu_save_cc thread tmp0 tmp1 108 93 movcf2gr \tmp0, $fcc0 109 - move \tmp1, \tmp0 94 + move \tmp1, \tmp0 95 + movcf2gr \tmp0, $fcc1 96 + bstrins.w \tmp1, \tmp0, 15, 8 97 + movcf2gr \tmp0, $fcc2 98 + bstrins.w \tmp1, \tmp0, 23, 16 99 + movcf2gr \tmp0, $fcc3 100 + bstrins.w \tmp1, \tmp0, 31, 24 101 + st.w \tmp1, \thread, THREAD_FCC 102 + movcf2gr \tmp0, $fcc4 103 + move \tmp1, \tmp0 104 + movcf2gr \tmp0, $fcc5 105 + bstrins.w \tmp1, \tmp0, 15, 8 106 + movcf2gr \tmp0, $fcc6 107 + bstrins.w \tmp1, \tmp0, 23, 16 108 + movcf2gr \tmp0, $fcc7 109 + bstrins.w \tmp1, \tmp0, 31, 24 110 + st.w \tmp1, \thread, (THREAD_FCC + 4) 111 + .endm 112 + 113 + .macro fpu_restore_cc thread tmp0 tmp1 114 + ld.w \tmp0, \thread, THREAD_FCC 115 + bstrpick.w \tmp1, \tmp0, 7, 0 116 + movgr2cf $fcc0, \tmp1 117 + bstrpick.w \tmp1, \tmp0, 15, 8 118 + movgr2cf $fcc1, \tmp1 119 + bstrpick.w \tmp1, \tmp0, 23, 16 120 + movgr2cf $fcc2, \tmp1 121 + bstrpick.w \tmp1, \tmp0, 31, 24 122 + movgr2cf $fcc3, \tmp1 123 + ld.w \tmp0, \thread, (THREAD_FCC + 4) 124 + bstrpick.w \tmp1, \tmp0, 7, 0 125 + movgr2cf $fcc4, \tmp1 126 + bstrpick.w \tmp1, \tmp0, 15, 8 127 + movgr2cf $fcc5, \tmp1 128 + bstrpick.w \tmp1, \tmp0, 23, 16 129 + movgr2cf $fcc6, \tmp1 130 + bstrpick.w \tmp1, \tmp0, 31, 24 131 + movgr2cf $fcc7, \tmp1 132 + .endm 133 + #else 134 + .macro fpu_save_cc thread tmp0 tmp1 135 + movcf2gr \tmp0, $fcc0 136 + move \tmp1, \tmp0 110 137 movcf2gr \tmp0, $fcc1 111 138 bstrins.d \tmp1, \tmp0, 15, 8 112 139 movcf2gr \tmp0, $fcc2 ··· 168 109 .endm 169 110 170 111 .macro fpu_restore_cc thread tmp0 tmp1 171 - ldptr.d \tmp0, \thread, THREAD_FCC 112 + ldptr.d \tmp0, \thread, THREAD_FCC 172 113 bstrpick.d \tmp1, \tmp0, 7, 0 173 114 movgr2cf $fcc0, \tmp1 174 115 bstrpick.d \tmp1, \tmp0, 15, 8 ··· 186 127 bstrpick.d \tmp1, \tmp0, 63, 56 187 128 movgr2cf $fcc7, \tmp1 188 129 .endm 130 + #endif 189 131 190 132 .macro fpu_save_double thread tmp 191 133 li.w \tmp, THREAD_FPR0 ··· 666 606 766: 667 607 lu12i.w \reg, 0 668 608 ori \reg, \reg, 0 609 + #ifdef CONFIG_64BIT 669 610 lu32i.d \reg, 0 670 611 lu52i.d \reg, \reg, 0 612 + #endif 671 613 .pushsection ".la_abs", "aw", %progbits 672 - .p2align 3 673 - .dword 766b 674 - .dword \sym 614 + .p2align PTRLOG 615 + PTR 766b 616 + PTR \sym 675 617 .popsection 676 618 #endif 677 619 .endm

+27 -7

arch/loongarch/include/asm/stackframe.h

··· 38 38 cfi_restore \reg \offset \docfi 39 39 .endm 40 40 41 + .macro SETUP_TWINS temp 42 + pcaddi t0, 0 43 + PTR_LI t1, ~TO_PHYS_MASK 44 + and t0, t0, t1 45 + ori t0, t0, (1 << 4 | 1) 46 + csrwr t0, LOONGARCH_CSR_DMWIN0 47 + PTR_LI t0, CSR_DMW1_INIT 48 + csrwr t0, LOONGARCH_CSR_DMWIN1 49 + .endm 50 + 51 + .macro SETUP_MODES temp 52 + /* Enable PG */ 53 + li.w \temp, 0xb0 # PLV=0, IE=0, PG=1 54 + csrwr \temp, LOONGARCH_CSR_CRMD 55 + li.w \temp, 0x04 # PLV=0, PIE=1, PWE=0 56 + csrwr \temp, LOONGARCH_CSR_PRMD 57 + li.w \temp, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 58 + csrwr \temp, LOONGARCH_CSR_EUEN 59 + .endm 60 + 41 61 .macro SETUP_DMWINS temp 42 - li.d \temp, CSR_DMW0_INIT # WUC, PLV0, 0x8000 xxxx xxxx xxxx 62 + PTR_LI \temp, CSR_DMW0_INIT # SUC, PLV0, LA32: 0x8xxx xxxx, LA64: 0x8000 xxxx xxxx xxxx 43 63 csrwr \temp, LOONGARCH_CSR_DMWIN0 44 - li.d \temp, CSR_DMW1_INIT # CAC, PLV0, 0x9000 xxxx xxxx xxxx 64 + PTR_LI \temp, CSR_DMW1_INIT # CAC, PLV0, LA32: 0xaxxx xxxx, LA64: 0x9000 xxxx xxxx xxxx 45 65 csrwr \temp, LOONGARCH_CSR_DMWIN1 46 - li.d \temp, CSR_DMW2_INIT # WUC, PLV0, 0xa000 xxxx xxxx xxxx 66 + PTR_LI \temp, CSR_DMW2_INIT # WUC, PLV0, LA32: unavailable, LA64: 0xa000 xxxx xxxx xxxx 47 67 csrwr \temp, LOONGARCH_CSR_DMWIN2 48 - li.d \temp, CSR_DMW3_INIT # 0x0, unused 68 + PTR_LI \temp, CSR_DMW3_INIT # 0x0, unused 49 69 csrwr \temp, LOONGARCH_CSR_DMWIN3 50 70 .endm 51 71 52 72 /* Jump to the runtime virtual address. */ 53 73 .macro JUMP_VIRT_ADDR temp1 temp2 54 - li.d \temp1, CACHE_BASE 74 + PTR_LI \temp1, CACHE_BASE 55 75 pcaddi \temp2, 0 56 - bstrins.d \temp1, \temp2, (DMW_PABITS - 1), 0 76 + PTR_BSTRINS \temp1, \temp2, (DMW_PABITS - 1), 0 57 77 jirl zero, \temp1, 0xc 58 78 .endm 59 79 ··· 191 171 andi t0, t0, 0x3 /* extract pplv bit */ 192 172 beqz t0, 9f 193 173 194 - li.d tp, ~_THREAD_MASK 174 + LONG_LI tp, ~_THREAD_MASK 195 175 and tp, tp, sp 196 176 cfi_st u0, PT_R21, \docfi 197 177 csrrd u0, PERCPU_BASE_KS