tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amd/pm: use macro to get pptable members

Use macro to get the pptable members for different pptable structures.

v2: abstract the table operations especially get the table members
to simplify cover the two different pptable structures.
v3: move pptable operations related structures and functions into ppt.c
v4: use macro to simplify the operation to get pptable members
v5: fix parameter reference error and add dump pptable support for
beige_goby

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Evan Quan <Evan.Quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Chengming Gui and committed by
Alex Deucher 7077b19a fbe8115c

+729 -66
+729 -66
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
··· 73 73 74 74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 75 75 76 + #define GET_PPTABLE_MEMBER(field, member) do {\ 77 + if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\ 78 + (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\ 79 + else\ 80 + (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\ 81 + } while(0) 82 + 83 + static int get_table_size(struct smu_context *smu) 84 + { 85 + if (smu->adev->asic_type == CHIP_BEIGE_GOBY) 86 + return sizeof(PPTable_beige_goby_t); 87 + else 88 + return sizeof(PPTable_t); 89 + } 90 + 76 91 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { 77 92 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 78 93 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), ··· 351 336 352 337 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) 353 338 { 354 - struct smu_table_context *table_context = &smu->smu_table; 355 - PPTable_t *smc_pptable = table_context->driver_pptable; 356 339 struct atom_smc_dpm_info_v4_9 *smc_dpm_table; 357 340 int index, ret; 341 + I2cControllerConfig_t *table_member; 358 342 359 343 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 360 344 smc_dpm_info); ··· 362 348 (uint8_t **)&smc_dpm_table); 363 349 if (ret) 364 350 return ret; 365 - 366 - memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers, 367 - sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); 351 + GET_PPTABLE_MEMBER(I2cControllers, &table_member); 352 + memcpy(table_member, smc_dpm_table->I2cControllers, 353 + sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); 368 354 369 355 return 0; 370 356 } ··· 374 360 struct smu_table_context *table_context = &smu->smu_table; 375 361 struct smu_11_0_7_powerplay_table *powerplay_table = 376 362 table_context->power_play_table; 363 + int table_size; 377 364 365 + table_size = get_table_size(smu); 378 366 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 379 - sizeof(PPTable_t)); 367 + table_size); 380 368 381 369 return 0; 382 370 } ··· 410 394 { 411 395 struct smu_table_context *smu_table = &smu->smu_table; 412 396 struct smu_table *tables = smu_table->tables; 397 + int table_size; 413 398 414 - SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 415 - PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 399 + table_size = get_table_size(smu); 400 + SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size, 401 + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 416 402 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 417 403 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 418 404 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), ··· 590 572 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) 591 573 { 592 574 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 593 - PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 594 575 struct smu_11_0_dpm_table *dpm_table; 595 576 struct amdgpu_device *adev = smu->adev; 596 577 int ret = 0; 578 + DpmDescriptor_t *table_member; 597 579 598 580 /* socclk dpm table setup */ 599 581 dpm_table = &dpm_context->dpm_tables.soc_table; 582 + GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 600 583 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 601 584 ret = smu_v11_0_set_single_dpm_table(smu, 602 585 SMU_SOCCLK, ··· 605 586 if (ret) 606 587 return ret; 607 588 dpm_table->is_fine_grained = 608 - !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 589 + !table_member[PPCLK_SOCCLK].SnapToDiscrete; 609 590 } else { 610 591 dpm_table->count = 1; 611 592 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; ··· 623 604 if (ret) 624 605 return ret; 625 606 dpm_table->is_fine_grained = 626 - !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 607 + !table_member[PPCLK_GFXCLK].SnapToDiscrete; 627 608 } else { 628 609 dpm_table->count = 1; 629 610 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; ··· 641 622 if (ret) 642 623 return ret; 643 624 dpm_table->is_fine_grained = 644 - !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 625 + !table_member[PPCLK_UCLK].SnapToDiscrete; 645 626 } else { 646 627 dpm_table->count = 1; 647 628 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; ··· 659 640 if (ret) 660 641 return ret; 661 642 dpm_table->is_fine_grained = 662 - !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete; 643 + !table_member[PPCLK_FCLK].SnapToDiscrete; 663 644 } else { 664 645 dpm_table->count = 1; 665 646 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; ··· 677 658 if (ret) 678 659 return ret; 679 660 dpm_table->is_fine_grained = 680 - !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete; 661 + !table_member[PPCLK_VCLK_0].SnapToDiscrete; 681 662 } else { 682 663 dpm_table->count = 1; 683 664 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; ··· 696 677 if (ret) 697 678 return ret; 698 679 dpm_table->is_fine_grained = 699 - !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete; 680 + !table_member[PPCLK_VCLK_1].SnapToDiscrete; 700 681 } else { 701 682 dpm_table->count = 1; 702 683 dpm_table->dpm_levels[0].value = ··· 716 697 if (ret) 717 698 return ret; 718 699 dpm_table->is_fine_grained = 719 - !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete; 700 + !table_member[PPCLK_DCLK_0].SnapToDiscrete; 720 701 } else { 721 702 dpm_table->count = 1; 722 703 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; ··· 735 716 if (ret) 736 717 return ret; 737 718 dpm_table->is_fine_grained = 738 - !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete; 719 + !table_member[PPCLK_DCLK_1].SnapToDiscrete; 739 720 } else { 740 721 dpm_table->count = 1; 741 722 dpm_table->dpm_levels[0].value = ··· 755 736 if (ret) 756 737 return ret; 757 738 dpm_table->is_fine_grained = 758 - !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; 739 + !table_member[PPCLK_DCEFCLK].SnapToDiscrete; 759 740 } else { 760 741 dpm_table->count = 1; 761 742 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; ··· 773 754 if (ret) 774 755 return ret; 775 756 dpm_table->is_fine_grained = 776 - !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; 757 + !table_member[PPCLK_PIXCLK].SnapToDiscrete; 777 758 } else { 778 759 dpm_table->count = 1; 779 760 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; ··· 791 772 if (ret) 792 773 return ret; 793 774 dpm_table->is_fine_grained = 794 - !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; 775 + !table_member[PPCLK_DISPCLK].SnapToDiscrete; 795 776 } else { 796 777 dpm_table->count = 1; 797 778 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; ··· 809 790 if (ret) 810 791 return ret; 811 792 dpm_table->is_fine_grained = 812 - !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; 793 + !table_member[PPCLK_PHYCLK].SnapToDiscrete; 813 794 } else { 814 795 dpm_table->count = 1; 815 796 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; ··· 930 911 931 912 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 932 913 { 933 - PPTable_t *pptable = smu->smu_table.driver_pptable; 934 914 DpmDescriptor_t *dpm_desc = NULL; 915 + DpmDescriptor_t *table_member; 935 916 uint32_t clk_index = 0; 936 917 918 + GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 937 919 clk_index = smu_cmn_to_asic_specific_index(smu, 938 920 CMN2ASIC_MAPPING_CLK, 939 921 clk_type); 940 - dpm_desc = &pptable->DpmDescriptor[clk_index]; 922 + dpm_desc = &table_member[clk_index]; 941 923 942 924 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 943 925 return dpm_desc->SnapToDiscrete == 0; ··· 967 947 struct smu_table_context *table_context = &smu->smu_table; 968 948 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 969 949 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 970 - PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 950 + uint16_t *table_member; 951 + 971 952 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; 972 953 OverDriveTable_t *od_table = 973 954 (OverDriveTable_t *)table_context->overdrive_table; ··· 1037 1016 case SMU_PCIE: 1038 1017 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1039 1018 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1019 + GET_PPTABLE_MEMBER(LclkFreq, &table_member); 1040 1020 for (i = 0; i < NUM_LINK_LEVELS; i++) 1041 1021 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, 1042 1022 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : ··· 1050 1028 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1051 1029 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1052 1030 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1053 - pptable->LclkFreq[i], 1031 + table_member[i], 1054 1032 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1055 1033 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1056 1034 "*" : ""); ··· 1297 1275 1298 1276 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) 1299 1277 { 1300 - PPTable_t *pptable = smu->smu_table.driver_pptable; 1278 + uint16_t *table_member; 1301 1279 1302 - smu->fan_max_rpm = pptable->FanMaximumRpm; 1280 + GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member); 1281 + smu->fan_max_rpm = *table_member; 1303 1282 1304 1283 return 0; 1305 1284 } ··· 1591 1568 void *data, uint32_t *size) 1592 1569 { 1593 1570 int ret = 0; 1594 - struct smu_table_context *table_context = &smu->smu_table; 1595 - PPTable_t *pptable = table_context->driver_pptable; 1571 + uint16_t *temp; 1596 1572 1597 1573 if(!data || !size) 1598 1574 return -EINVAL; ··· 1599 1577 mutex_lock(&smu->sensor_lock); 1600 1578 switch (sensor) { 1601 1579 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1602 - *(uint32_t *)data = pptable->FanMaximumRpm; 1580 + GET_PPTABLE_MEMBER(FanMaximumRpm, &temp); 1581 + *(uint16_t *)data = *temp; 1603 1582 *size = 4; 1604 1583 break; 1605 1584 case AMDGPU_PP_SENSOR_MEM_LOAD: ··· 1668 1645 uint16_t *dpm_levels = NULL; 1669 1646 uint16_t i = 0; 1670 1647 struct smu_table_context *table_context = &smu->smu_table; 1671 - PPTable_t *driver_ppt = NULL; 1648 + DpmDescriptor_t *table_member1; 1649 + uint16_t *table_member2; 1672 1650 1673 1651 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 1674 1652 return -EINVAL; 1675 1653 1676 - driver_ppt = table_context->driver_pptable; 1677 - num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; 1678 - dpm_levels = driver_ppt->FreqTableUclk; 1654 + GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1); 1655 + num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels; 1656 + GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2); 1657 + dpm_levels = table_member2; 1679 1658 1680 1659 if (num_discrete_levels == 0 || dpm_levels == NULL) 1681 1660 return -EINVAL; ··· 1699 1674 struct smu_table_context *table_context = &smu->smu_table; 1700 1675 struct smu_11_0_7_powerplay_table *powerplay_table = 1701 1676 table_context->power_play_table; 1702 - PPTable_t *pptable = smu->smu_table.driver_pptable; 1677 + uint16_t *table_member; 1678 + uint16_t temp_edge, temp_hotspot, temp_mem; 1703 1679 1704 1680 if (!range) 1705 1681 return -EINVAL; 1706 1682 1707 1683 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 1708 1684 1709 - range->max = pptable->TemperatureLimit[TEMP_EDGE] * 1685 + GET_PPTABLE_MEMBER(TemperatureLimit, &table_member); 1686 + temp_edge = table_member[TEMP_EDGE]; 1687 + temp_hotspot = table_member[TEMP_HOTSPOT]; 1688 + temp_mem = table_member[TEMP_MEM]; 1689 + 1690 + range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1691 + range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) * 1710 1692 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1711 - range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * 1693 + range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1694 + range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) * 1712 1695 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1713 - range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] * 1696 + range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1697 + range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)* 1714 1698 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1715 - range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * 1716 - SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1717 - range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] * 1718 - SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1719 - range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* 1720 - SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1699 + 1721 1700 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1722 1701 1723 1702 return 0; ··· 1755 1726 { 1756 1727 struct smu_11_0_7_powerplay_table *powerplay_table = 1757 1728 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; 1758 - PPTable_t *pptable = smu->smu_table.driver_pptable; 1759 1729 uint32_t power_limit, od_percent; 1730 + uint16_t *table_member; 1731 + 1732 + GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member); 1760 1733 1761 1734 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 1762 - /* the last hope to figure out the ppt limit */ 1763 - if (!pptable) { 1764 - dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 1765 - return -EINVAL; 1766 - } 1767 1735 power_limit = 1768 - pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 1736 + table_member[PPT_THROTTLER_PPT0]; 1769 1737 } 1770 1738 smu->current_power_limit = smu->default_power_limit = power_limit; 1771 1739 ··· 1784 1758 uint32_t pcie_width_cap) 1785 1759 { 1786 1760 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1787 - PPTable_t *pptable = smu->smu_table.driver_pptable; 1761 + 1788 1762 uint32_t smu_pcie_arg; 1763 + uint8_t *table_member1, *table_member2; 1789 1764 int ret, i; 1765 + 1766 + GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); 1767 + GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); 1790 1768 1791 1769 /* lclk dpm table setup */ 1792 1770 for (i = 0; i < MAX_PCIE_CONF; i++) { 1793 - dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; 1794 - dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; 1771 + dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i]; 1772 + dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i]; 1795 1773 } 1796 1774 1797 1775 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1798 1776 smu_pcie_arg = (i << 16) | 1799 - ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? 1800 - (pptable->PcieGenSpeed[i] << 8) : 1801 - (pcie_gen_cap << 8)) | 1802 - ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? 1803 - pptable->PcieLaneCount[i] : 1804 - pcie_width_cap); 1777 + ((table_member1[i] <= pcie_gen_cap) ? 1778 + (table_member1[i] << 8) : 1779 + (pcie_gen_cap << 8)) | 1780 + ((table_member2[i] <= pcie_width_cap) ? 1781 + table_member2[i] : 1782 + pcie_width_cap); 1805 1783 1806 1784 ret = smu_cmn_send_smc_msg_with_param(smu, 1807 - SMU_MSG_OverridePcieParameters, 1808 - smu_pcie_arg, 1809 - NULL); 1810 - 1785 + SMU_MSG_OverridePcieParameters, 1786 + smu_pcie_arg, 1787 + NULL); 1811 1788 if (ret) 1812 1789 return ret; 1813 1790 1814 - if (pptable->PcieGenSpeed[i] > pcie_gen_cap) 1791 + if (table_member1[i] > pcie_gen_cap) 1815 1792 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 1816 - if (pptable->PcieLaneCount[i] > pcie_width_cap) 1793 + if (table_member2[i] > pcie_width_cap) 1817 1794 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 1818 1795 } 1819 1796 ··· 2115 2086 return val != 0x0; 2116 2087 } 2117 2088 2089 + static void beige_goby_dump_pptable(struct smu_context *smu) 2090 + { 2091 + struct smu_table_context *table_context = &smu->smu_table; 2092 + PPTable_beige_goby_t *pptable = table_context->driver_pptable; 2093 + int i; 2094 + 2095 + dev_info(smu->adev->dev, "Dumped PPTable:\n"); 2096 + 2097 + dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 2098 + dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 2099 + dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 2100 + 2101 + for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 2102 + dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 2103 + dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 2104 + dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 2105 + dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 2106 + } 2107 + 2108 + for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 2109 + dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 2110 + dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 2111 + } 2112 + 2113 + for (i = 0; i < TEMP_COUNT; i++) { 2114 + dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 2115 + } 2116 + 2117 + dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 2118 + dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 2119 + dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 2120 + dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 2121 + dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 2122 + 2123 + dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 2124 + for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 2125 + dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 2126 + dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 2127 + } 2128 + dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 2129 + 2130 + dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 2131 + 2132 + dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 2133 + dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 2134 + dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 2135 + dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 2136 + 2137 + dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 2138 + 2139 + dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 2140 + 2141 + dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 2142 + dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 2143 + dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 2144 + dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 2145 + 2146 + dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 2147 + dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 2148 + 2149 + dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 2150 + dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 2151 + dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 2152 + dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 2153 + dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 2154 + dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 2155 + dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 2156 + dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 2157 + 2158 + dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 2159 + " .VoltageMode = 0x%02x\n" 2160 + " .SnapToDiscrete = 0x%02x\n" 2161 + " .NumDiscreteLevels = 0x%02x\n" 2162 + " .padding = 0x%02x\n" 2163 + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2164 + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2165 + " .SsFmin = 0x%04x\n" 2166 + " .Padding_16 = 0x%04x\n", 2167 + pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 2168 + pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 2169 + pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 2170 + pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 2171 + pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 2172 + pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 2173 + pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 2174 + pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 2175 + pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 2176 + pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 2177 + pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 2178 + 2179 + dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 2180 + " .VoltageMode = 0x%02x\n" 2181 + " .SnapToDiscrete = 0x%02x\n" 2182 + " .NumDiscreteLevels = 0x%02x\n" 2183 + " .padding = 0x%02x\n" 2184 + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2185 + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2186 + " .SsFmin = 0x%04x\n" 2187 + " .Padding_16 = 0x%04x\n", 2188 + pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 2189 + pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 2190 + pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 2191 + pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 2192 + pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 2193 + pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 2194 + pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 2195 + pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 2196 + pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 2197 + pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 2198 + pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 2199 + 2200 + dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 2201 + " .VoltageMode = 0x%02x\n" 2202 + " .SnapToDiscrete = 0x%02x\n" 2203 + " .NumDiscreteLevels = 0x%02x\n" 2204 + " .padding = 0x%02x\n" 2205 + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2206 + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2207 + " .SsFmin = 0x%04x\n" 2208 + " .Padding_16 = 0x%04x\n", 2209 + pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 2210 + pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 2211 + pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 2212 + pptable->DpmDescriptor[PPCLK_UCLK].Padding, 2213 + pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 2214 + pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 2215 + pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 2216 + pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 2217 + pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 2218 + pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 2219 + pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 2220 + 2221 + dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 2222 + " .VoltageMode = 0x%02x\n" 2223 + " .SnapToDiscrete = 0x%02x\n" 2224 + " .NumDiscreteLevels = 0x%02x\n" 2225 + " .padding = 0x%02x\n" 2226 + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2227 + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2228 + " .SsFmin = 0x%04x\n" 2229 + " .Padding_16 = 0x%04x\n", 2230 + pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 2231 + pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 2232 + pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 2233 + pptable->DpmDescriptor[PPCLK_FCLK].Padding, 2234 + pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 2235 + pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 2236 + pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 2237 + pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 2238 + pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 2239 + pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 2240 + pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 2241 + 2242 + dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 2243 + " .VoltageMode = 0x%02x\n" 2244 + " .SnapToDiscrete = 0x%02x\n" 2245 + " .NumDiscreteLevels = 0x%02x\n" 2246 + " .padding = 0x%02x\n" 2247 + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2248 + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2249 + " .SsFmin = 0x%04x\n" 2250 + " .Padding_16 = 0x%04x\n", 2251 + pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 2252 + pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 2253 + pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 2254 + pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 2255 + pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 2256 + pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 2257 + pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 2258 + pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 2259 + pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 2260 + pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 2261 + pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 2262 + 2263 + dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 2264 + " .VoltageMode = 0x%02x\n" 2265 + " .SnapToDiscrete = 0x%02x\n" 2266 + " .NumDiscreteLevels = 0x%02x\n" 2267 + " .padding = 0x%02x\n" 2268 + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2269 + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2270 + " .SsFmin = 0x%04x\n" 2271 + " .Padding_16 = 0x%04x\n", 2272 + pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 2273 + pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 2274 + pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 2275 + pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 2276 + pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 2277 + pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 2278 + pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 2279 + pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 2280 + pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 2281 + pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 2282 + pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 2283 + 2284 + dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 2285 + " .VoltageMode = 0x%02x\n" 2286 + " .SnapToDiscrete = 0x%02x\n" 2287 + " .NumDiscreteLevels = 0x%02x\n" 2288 + " .padding = 0x%02x\n" 2289 + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2290 + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2291 + " .SsFmin = 0x%04x\n" 2292 + " .Padding_16 = 0x%04x\n", 2293 + pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 2294 + pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 2295 + pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 2296 + pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 2297 + pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 2298 + pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 2299 + pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 2300 + pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 2301 + pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 2302 + pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 2303 + pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 2304 + 2305 + dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 2306 + " .VoltageMode = 0x%02x\n" 2307 + " .SnapToDiscrete = 0x%02x\n" 2308 + " .NumDiscreteLevels = 0x%02x\n" 2309 + " .padding = 0x%02x\n" 2310 + " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2311 + " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2312 + " .SsFmin = 0x%04x\n" 2313 + " .Padding_16 = 0x%04x\n", 2314 + pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 2315 + pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 2316 + pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 2317 + pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 2318 + pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 2319 + pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 2320 + pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 2321 + pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 2322 + pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 2323 + pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 2324 + pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 2325 + 2326 + dev_info(smu->adev->dev, "FreqTableGfx\n"); 2327 + for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 2328 + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 2329 + 2330 + dev_info(smu->adev->dev, "FreqTableVclk\n"); 2331 + for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 2332 + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 2333 + 2334 + dev_info(smu->adev->dev, "FreqTableDclk\n"); 2335 + for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 2336 + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 2337 + 2338 + dev_info(smu->adev->dev, "FreqTableSocclk\n"); 2339 + for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 2340 + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 2341 + 2342 + dev_info(smu->adev->dev, "FreqTableUclk\n"); 2343 + for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2344 + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 2345 + 2346 + dev_info(smu->adev->dev, "FreqTableFclk\n"); 2347 + for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 2348 + dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 2349 + 2350 + dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 2351 + dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 2352 + dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 2353 + dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 2354 + dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 2355 + dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 2356 + dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 2357 + dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 2358 + dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 2359 + 2360 + dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 2361 + for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2362 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 2363 + 2364 + dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 2365 + dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 2366 + 2367 + dev_info(smu->adev->dev, "Mp0clkFreq\n"); 2368 + for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2369 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 2370 + 2371 + dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 2372 + for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2373 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 2374 + 2375 + dev_info(smu->adev->dev, "MemVddciVoltage\n"); 2376 + for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2377 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 2378 + 2379 + dev_info(smu->adev->dev, "MemMvddVoltage\n"); 2380 + for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2381 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 2382 + 2383 + dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 2384 + dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 2385 + dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 2386 + dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 2387 + dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 2388 + 2389 + dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 2390 + 2391 + dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 2392 + dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 2393 + dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 2394 + dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 2395 + dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 2396 + dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 2397 + dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 2398 + dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 2399 + dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 2400 + dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 2401 + dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 2402 + 2403 + dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 2404 + dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 2405 + dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 2406 + dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 2407 + dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 2408 + dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 2409 + 2410 + dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 2411 + dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 2412 + dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 2413 + dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 2414 + dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 2415 + 2416 + dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 2417 + for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 2418 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 2419 + 2420 + dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 2421 + dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 2422 + dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 2423 + dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 2424 + 2425 + dev_info(smu->adev->dev, "UclkDpmPstates\n"); 2426 + for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2427 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 2428 + 2429 + dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 2430 + dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2431 + pptable->UclkDpmSrcFreqRange.Fmin); 2432 + dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2433 + pptable->UclkDpmSrcFreqRange.Fmax); 2434 + dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 2435 + dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2436 + pptable->UclkDpmTargFreqRange.Fmin); 2437 + dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2438 + pptable->UclkDpmTargFreqRange.Fmax); 2439 + dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 2440 + dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 2441 + 2442 + dev_info(smu->adev->dev, "PcieGenSpeed\n"); 2443 + for (i = 0; i < NUM_LINK_LEVELS; i++) 2444 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 2445 + 2446 + dev_info(smu->adev->dev, "PcieLaneCount\n"); 2447 + for (i = 0; i < NUM_LINK_LEVELS; i++) 2448 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 2449 + 2450 + dev_info(smu->adev->dev, "LclkFreq\n"); 2451 + for (i = 0; i < NUM_LINK_LEVELS; i++) 2452 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 2453 + 2454 + dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 2455 + dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 2456 + 2457 + dev_info(smu->adev->dev, "FanGain\n"); 2458 + for (i = 0; i < TEMP_COUNT; i++) 2459 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 2460 + 2461 + dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 2462 + dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 2463 + dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 2464 + dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 2465 + dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 2466 + dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 2467 + dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 2468 + dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 2469 + dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 2470 + dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 2471 + dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 2472 + dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 2473 + 2474 + dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 2475 + dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 2476 + dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 2477 + dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 2478 + 2479 + dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 2480 + dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 2481 + dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 2482 + dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 2483 + 2484 + dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2485 + pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 2486 + pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 2487 + pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 2488 + dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2489 + pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 2490 + pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 2491 + pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 2492 + dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 2493 + pptable->dBtcGbGfxPll.a, 2494 + pptable->dBtcGbGfxPll.b, 2495 + pptable->dBtcGbGfxPll.c); 2496 + dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 2497 + pptable->dBtcGbGfxDfll.a, 2498 + pptable->dBtcGbGfxDfll.b, 2499 + pptable->dBtcGbGfxDfll.c); 2500 + dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 2501 + pptable->dBtcGbSoc.a, 2502 + pptable->dBtcGbSoc.b, 2503 + pptable->dBtcGbSoc.c); 2504 + dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 2505 + pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 2506 + pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 2507 + dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 2508 + pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 2509 + pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 2510 + 2511 + dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 2512 + for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 2513 + dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 2514 + i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 2515 + dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 2516 + i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 2517 + } 2518 + 2519 + dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2520 + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 2521 + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 2522 + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 2523 + dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2524 + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 2525 + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 2526 + pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 2527 + 2528 + dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 2529 + dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 2530 + 2531 + dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 2532 + dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 2533 + dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 2534 + dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 2535 + 2536 + dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 2537 + dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 2538 + dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 2539 + dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 2540 + 2541 + dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 2542 + dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 2543 + 2544 + dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 2545 + for (i = 0; i < NUM_XGMI_LEVELS; i++) 2546 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 2547 + dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 2548 + dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 2549 + 2550 + dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 2551 + dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 2552 + pptable->ReservedEquation0.a, 2553 + pptable->ReservedEquation0.b, 2554 + pptable->ReservedEquation0.c); 2555 + dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 2556 + pptable->ReservedEquation1.a, 2557 + pptable->ReservedEquation1.b, 2558 + pptable->ReservedEquation1.c); 2559 + dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 2560 + pptable->ReservedEquation2.a, 2561 + pptable->ReservedEquation2.b, 2562 + pptable->ReservedEquation2.c); 2563 + dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 2564 + pptable->ReservedEquation3.a, 2565 + pptable->ReservedEquation3.b, 2566 + pptable->ReservedEquation3.c); 2567 + 2568 + dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 2569 + dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 2570 + dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 2571 + dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 2572 + dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 2573 + dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 2574 + dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 2575 + dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 2576 + 2577 + dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 2578 + dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 2579 + dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 2580 + dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 2581 + dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 2582 + dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 2583 + 2584 + for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 2585 + dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 2586 + dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 2587 + pptable->I2cControllers[i].Enabled); 2588 + dev_info(smu->adev->dev, " .Speed = 0x%x\n", 2589 + pptable->I2cControllers[i].Speed); 2590 + dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 2591 + pptable->I2cControllers[i].SlaveAddress); 2592 + dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 2593 + pptable->I2cControllers[i].ControllerPort); 2594 + dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 2595 + pptable->I2cControllers[i].ControllerName); 2596 + dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 2597 + pptable->I2cControllers[i].ThermalThrotter); 2598 + dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 2599 + pptable->I2cControllers[i].I2cProtocol); 2600 + dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 2601 + pptable->I2cControllers[i].PaddingConfig); 2602 + } 2603 + 2604 + dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 2605 + dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 2606 + dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 2607 + dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 2608 + 2609 + dev_info(smu->adev->dev, "Board Parameters:\n"); 2610 + dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 2611 + dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 2612 + dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 2613 + dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 2614 + dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 2615 + dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 2616 + dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 2617 + dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 2618 + 2619 + dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 2620 + dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 2621 + dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 2622 + 2623 + dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 2624 + dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 2625 + dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 2626 + 2627 + dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 2628 + dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 2629 + dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 2630 + 2631 + dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 2632 + dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 2633 + dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 2634 + 2635 + dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 2636 + 2637 + dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 2638 + dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 2639 + dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 2640 + dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 2641 + dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 2642 + dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 2643 + dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 2644 + dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 2645 + dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 2646 + dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 2647 + dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 2648 + dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 2649 + dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 2650 + dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 2651 + dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 2652 + dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 2653 + 2654 + dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 2655 + dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 2656 + dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 2657 + 2658 + dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 2659 + dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 2660 + dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 2661 + 2662 + dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 2663 + dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 2664 + 2665 + dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 2666 + dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 2667 + dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 2668 + 2669 + dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 2670 + dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 2671 + dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 2672 + dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 2673 + dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 2674 + 2675 + dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 2676 + dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 2677 + 2678 + dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 2679 + for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2680 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 2681 + dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 2682 + for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2683 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 2684 + dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 2685 + for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2686 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 2687 + dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 2688 + for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2689 + dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 2690 + 2691 + dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 2692 + dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 2693 + dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 2694 + dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 2695 + 2696 + dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 2697 + dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 2698 + dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 2699 + dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 2700 + dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 2701 + dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 2702 + dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 2703 + dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 2704 + dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 2705 + dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 2706 + dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 2707 + 2708 + dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 2709 + dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 2710 + dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 2711 + dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 2712 + dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 2713 + dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 2714 + dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 2715 + dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 2716 + } 2717 + 2118 2718 static void sienna_cichlid_dump_pptable(struct smu_context *smu) 2119 2719 { 2120 2720 struct smu_table_context *table_context = &smu->smu_table; 2121 2721 PPTable_t *pptable = table_context->driver_pptable; 2122 2722 int i; 2723 + 2724 + if (smu->adev->asic_type == CHIP_BEIGE_GOBY) { 2725 + beige_goby_dump_pptable(smu); 2726 + return; 2727 + } 2123 2728 2124 2729 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 2125 2730