Merge tag 'v4.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

+1 -1

arch/arm/boot/dts/rk3288-veyron.dtsi

··· 421 421 status = "okay"; 422 422 423 423 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; 424 - assigned-clock-parents = <&cru SCLK_OTGPHY0>; 424 + assigned-clock-parents = <&usbphy0>; 425 425 dr_mode = "host"; 426 426 }; 427 427

+7 -26

drivers/clk/rockchip/clk-rk3036.c

··· 177 177 GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED, 178 178 RK2928_CLKGATE_CON(0), 6, GFLAGS), 179 179 180 + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 181 + 180 182 /* 181 183 * Clock-Architecture Diagram 2 182 184 */ ··· 189 187 RK2928_CLKGATE_CON(0), 8, GFLAGS), 190 188 COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED, 191 189 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 190 + FACTOR(0, "ddrphy", "ddrphy2x", 0, 1, 2), 192 191 193 192 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, 194 193 RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, ··· 266 263 COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0, 267 264 RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, 268 265 RK2928_CLKGATE_CON(3), 11, GFLAGS), 266 + FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4, 267 + RK2928_CLKGATE_CON(3), 12, GFLAGS), 269 268 270 269 COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0, 271 270 RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS, ··· 356 351 COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0, 357 352 RK2928_CLKSEL_CON(21), 4, 5, DFLAGS, 358 353 RK2928_CLKGATE_CON(2), 6, GFLAGS), 354 + FACTOR(0, "sclk_macref_out", "hclk_peri_src", 0, 1, 2), 359 355 360 356 MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0, 361 357 RK2928_CLKSEL_CON(31), 0, 1, MFLAGS), ··· 382 376 GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS), 383 377 GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), 384 378 385 - GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS), 379 + GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS), 386 380 GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), 387 381 388 - /* hclk_video gates */ 389 - GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS), 390 382 391 383 /* xin24m gates */ 392 384 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS), ··· 448 444 449 445 rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 450 446 451 - /* xin12m is created by an cru-internal divider */ 452 - clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); 453 - if (IS_ERR(clk)) 454 - pr_warn("%s: could not register clock xin12m: %ld\n", 455 - __func__, PTR_ERR(clk)); 456 - 457 447 clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1); 458 448 if (IS_ERR(clk)) 459 449 pr_warn("%s: could not register clock usb480m: %ld\n", 460 - __func__, PTR_ERR(clk)); 461 - 462 - clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy2x", 0, 1, 2); 463 - if (IS_ERR(clk)) 464 - pr_warn("%s: could not register clock ddrphy: %ld\n", 465 - __func__, PTR_ERR(clk)); 466 - 467 - clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre", 468 - "aclk_vcodec", 0, 1, 4); 469 - if (IS_ERR(clk)) 470 - pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", 471 - __func__, PTR_ERR(clk)); 472 - 473 - clk = clk_register_fixed_factor(NULL, "sclk_macref_out", 474 - "hclk_peri_src", 0, 1, 2); 475 - if (IS_ERR(clk)) 476 - pr_warn("%s: could not register clock sclk_macref_out: %ld\n", 477 450 __func__, PTR_ERR(clk)); 478 451 479 452 rockchip_clk_register_plls(rk3036_pll_clks,

+9 -18

drivers/clk/rockchip/clk-rk3188.c

··· 339 339 INVERTER(0, "pclk_cif0", "pclkin_cif0", 340 340 RK2928_CLKSEL_CON(30), 8, IFLAGS), 341 341 342 + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 343 + 342 344 /* 343 345 * the 480m are generated inside the usb block from these clocks, 344 346 * but they are also a source for the hsicphy clock. 345 347 */ 346 - GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED, 348 + GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED, 347 349 RK2928_CLKGATE_CON(1), 5, GFLAGS), 348 - GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED, 350 + GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED, 349 351 RK2928_CLKGATE_CON(1), 6, GFLAGS), 350 352 351 353 COMPOSITE(0, "mac_src", mux_mac_p, 0, ··· 607 605 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, 608 606 RK2928_CLKGATE_CON(3), 2, GFLAGS), 609 607 610 - COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, 608 + COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, 611 609 RK2928_CLKSEL_CON(34), 0, 16, DFLAGS, 612 610 RK2928_CLKGATE_CON(2), 15, GFLAGS), 613 611 ··· 664 662 { /* sentinel */ }, 665 663 }; 666 664 667 - PNAME(mux_hsicphy_p) = { "sclk_otgphy0", "sclk_otgphy1", 665 + PNAME(mux_hsicphy_p) = { "sclk_otgphy0_480m", "sclk_otgphy1_480m", 668 666 "gpll", "cpll" }; 669 667 670 668 static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata = 671 - MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, 669 + MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, 672 670 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); 673 671 674 672 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { ··· 724 722 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, 725 723 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, 726 724 RK2928_CLKGATE_CON(0), 9, GFLAGS), 727 - COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0, 725 + COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT, 728 726 RK2928_CLKSEL_CON(7), 0, 729 727 RK2928_CLKGATE_CON(0), 10, GFLAGS, 730 728 &rk3188_i2s0_fracmux), ··· 750 748 "hclk_peri", 751 749 "pclk_cpu", 752 750 "pclk_peri", 751 + "hclk_cpubus" 753 752 }; 754 753 755 754 static void __init rk3188_common_clk_init(struct device_node *np) 756 755 { 757 756 void __iomem *reg_base; 758 - struct clk *clk; 759 757 760 758 reg_base = of_iomap(np, 0); 761 759 if (!reg_base) { ··· 764 762 } 765 763 766 764 rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 767 - 768 - /* xin12m is created by an cru-internal divider */ 769 - clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); 770 - if (IS_ERR(clk)) 771 - pr_warn("%s: could not register clock xin12m: %ld\n", 772 - __func__, PTR_ERR(clk)); 773 - 774 - clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1); 775 - if (IS_ERR(clk)) 776 - pr_warn("%s: could not register clock usb480m: %ld\n", 777 - __func__, PTR_ERR(clk)); 778 765 779 766 rockchip_clk_register_branches(common_clk_branches, 780 767 ARRAY_SIZE(common_clk_branches));

+8 -30

drivers/clk/rockchip/clk-rk3228.c

··· 187 187 RK2928_CLKGATE_CON(7), 1, GFLAGS), 188 188 GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED, 189 189 RK2928_CLKGATE_CON(8), 5, GFLAGS), 190 - GATE(0, "ddrphy", "ddrphy_pre", CLK_IGNORE_UNUSED, 190 + FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, 191 191 RK2928_CLKGATE_CON(7), 0, GFLAGS), 192 192 193 193 /* PD_CORE */ ··· 240 240 COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, 241 241 RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS, 242 242 RK2928_CLKGATE_CON(3), 11, GFLAGS), 243 - GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0, 243 + FACTOR_GATE(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4, 244 244 RK2928_CLKGATE_CON(4), 4, GFLAGS), 245 245 246 246 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, 247 247 RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, 248 248 RK2928_CLKGATE_CON(3), 2, GFLAGS), 249 - GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0, 249 + FACTOR_GATE(0, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4, 250 250 RK2928_CLKGATE_CON(4), 5, GFLAGS), 251 251 252 252 COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, ··· 370 370 RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), 371 371 MUX(0, "dclk_vop", mux_dclk_vop_p, 0, 372 372 RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), 373 + 374 + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 373 375 374 376 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, 375 377 RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS, ··· 607 605 608 606 /* PD_MMC */ 609 607 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1), 610 - MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1), 608 + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0), 611 609 612 610 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1), 613 - MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1), 611 + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0), 614 612 615 613 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1), 616 - MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1), 614 + MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0), 617 615 }; 618 616 619 617 static const char *const rk3228_critical_clocks[] __initconst = { ··· 626 624 static void __init rk3228_clk_init(struct device_node *np) 627 625 { 628 626 void __iomem *reg_base; 629 - struct clk *clk; 630 627 631 628 reg_base = of_iomap(np, 0); 632 629 if (!reg_base) { ··· 634 633 } 635 634 636 635 rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 637 - 638 - /* xin12m is created by an cru-internal divider */ 639 - clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); 640 - if (IS_ERR(clk)) 641 - pr_warn("%s: could not register clock xin12m: %ld\n", 642 - __func__, PTR_ERR(clk)); 643 - 644 - clk = clk_register_fixed_factor(NULL, "ddrphy_pre", "ddrphy4x", 0, 1, 4); 645 - if (IS_ERR(clk)) 646 - pr_warn("%s: could not register clock ddrphy_pre: %ld\n", 647 - __func__, PTR_ERR(clk)); 648 - 649 - clk = clk_register_fixed_factor(NULL, "hclk_vpu_pre", 650 - "hclk_vpu_src", 0, 1, 4); 651 - if (IS_ERR(clk)) 652 - pr_warn("%s: could not register clock hclk_vpu_pre: %ld\n", 653 - __func__, PTR_ERR(clk)); 654 - 655 - clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre", 656 - "hclk_rkvdec_src", 0, 1, 4); 657 - if (IS_ERR(clk)) 658 - pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n", 659 - __func__, PTR_ERR(clk)); 660 636 661 637 rockchip_clk_register_plls(rk3228_pll_clks, 662 638 ARRAY_SIZE(rk3228_pll_clks),

+10 -28

drivers/clk/rockchip/clk-rk3288.c

··· 195 195 PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" }; 196 196 PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" }; 197 197 198 - PNAME(mux_usbphy480m_p) = { "sclk_otgphy1", "sclk_otgphy2", 199 - "sclk_otgphy0" }; 198 + PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m", 199 + "sclk_otgphy0_480m" }; 200 200 PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" }; 201 201 PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" }; 202 202 ··· 333 333 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED, 334 334 RK3288_CLKGATE_CON(0), 7, GFLAGS), 335 335 336 + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 337 + 336 338 COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0, 337 339 RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS, 338 340 RK3288_CLKGATE_CON(4), 1, GFLAGS), ··· 401 399 */ 402 400 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, 403 401 RK3288_CLKGATE_CON(9), 0, GFLAGS), 404 - /* 405 - * We introduce a virtul node of hclk_vodec_pre_v to split one clock 406 - * struct with a gate and a fix divider into two node in software. 407 - */ 408 - GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0, 402 + 403 + FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0, 1, 4, 409 404 RK3288_CLKGATE_CON(3), 10, GFLAGS), 405 + 410 406 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, 411 407 RK3288_CLKGATE_CON(9), 1, GFLAGS), 412 408 ··· 537 537 RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, 538 538 RK3288_CLKGATE_CON(4), 10, GFLAGS), 539 539 540 - GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED, 540 + GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED, 541 541 RK3288_CLKGATE_CON(13), 4, GFLAGS), 542 - GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED, 542 + GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED, 543 543 RK3288_CLKGATE_CON(13), 5, GFLAGS), 544 - GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", CLK_IGNORE_UNUSED, 544 + GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED, 545 545 RK3288_CLKGATE_CON(13), 6, GFLAGS), 546 546 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED, 547 547 RK3288_CLKGATE_CON(13), 7, GFLAGS), ··· 887 887 } 888 888 889 889 rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS); 890 - 891 - /* xin12m is created by an cru-internal divider */ 892 - clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); 893 - if (IS_ERR(clk)) 894 - pr_warn("%s: could not register clock xin12m: %ld\n", 895 - __func__, PTR_ERR(clk)); 896 - 897 - 898 - clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1); 899 - if (IS_ERR(clk)) 900 - pr_warn("%s: could not register clock usb480m: %ld\n", 901 - __func__, PTR_ERR(clk)); 902 - 903 - clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre", 904 - "hclk_vcodec_pre_v", 0, 1, 4); 905 - if (IS_ERR(clk)) 906 - pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", 907 - __func__, PTR_ERR(clk)); 908 890 909 891 /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */ 910 892 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);

+33 -49

drivers/clk/rockchip/clk-rk3368.c

··· 121 121 "dummy", "xin12m" }; 122 122 PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", 123 123 "ext_i2s", "xin12m" }; 124 - PNAME(mux_edp_24m_p) = { "dummy", "xin24m" }; 124 + PNAME(mux_edp_24m_p) = { "xin24m", "dummy" }; 125 125 PNAME(mux_vip_out_p) = { "vip_src", "xin24m" }; 126 126 PNAME(mux_usbphy480m_p) = { "usbotg_out", "xin24m" }; 127 127 PNAME(mux_hsic_usbphy480m_p) = { "usbotg_out", "dummy" }; ··· 165 165 .core_reg = RK3368_CLKSEL_CON(0), 166 166 .div_core_shift = 0, 167 167 .div_core_mask = 0x1f, 168 - .mux_core_shift = 15, 168 + .mux_core_shift = 7, 169 169 }; 170 170 171 171 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = { ··· 218 218 } 219 219 220 220 static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = { 221 - RK3368_CPUCLKB_RATE(1512000000, 2, 6, 6), 222 - RK3368_CPUCLKB_RATE(1488000000, 2, 5, 5), 223 - RK3368_CPUCLKB_RATE(1416000000, 2, 5, 5), 224 - RK3368_CPUCLKB_RATE(1200000000, 2, 4, 4), 225 - RK3368_CPUCLKB_RATE(1008000000, 2, 4, 4), 226 - RK3368_CPUCLKB_RATE( 816000000, 2, 3, 3), 227 - RK3368_CPUCLKB_RATE( 696000000, 2, 3, 3), 228 - RK3368_CPUCLKB_RATE( 600000000, 2, 2, 2), 229 - RK3368_CPUCLKB_RATE( 408000000, 2, 2, 2), 230 - RK3368_CPUCLKB_RATE( 312000000, 2, 2, 2), 221 + RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5), 222 + RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4), 223 + RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4), 224 + RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3), 225 + RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3), 226 + RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2), 227 + RK3368_CPUCLKB_RATE( 696000000, 1, 2, 2), 228 + RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1), 229 + RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1), 230 + RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1), 231 231 }; 232 232 233 233 static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = { 234 - RK3368_CPUCLKL_RATE(1512000000, 2, 7, 7), 235 - RK3368_CPUCLKL_RATE(1488000000, 2, 6, 6), 236 - RK3368_CPUCLKL_RATE(1416000000, 2, 6, 6), 237 - RK3368_CPUCLKL_RATE(1200000000, 2, 5, 5), 238 - RK3368_CPUCLKL_RATE(1008000000, 2, 5, 5), 239 - RK3368_CPUCLKL_RATE( 816000000, 2, 4, 4), 240 - RK3368_CPUCLKL_RATE( 696000000, 2, 3, 3), 241 - RK3368_CPUCLKL_RATE( 600000000, 2, 3, 3), 242 - RK3368_CPUCLKL_RATE( 408000000, 2, 2, 2), 243 - RK3368_CPUCLKL_RATE( 312000000, 2, 2, 2), 234 + RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6), 235 + RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5), 236 + RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5), 237 + RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4), 238 + RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4), 239 + RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3), 240 + RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2), 241 + RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2), 242 + RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1), 243 + RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1), 244 244 }; 245 245 246 246 static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { 247 247 /* 248 248 * Clock-Architecture Diagram 2 249 249 */ 250 + 251 + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 250 252 251 253 MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT, 252 254 RK3368_CLKSEL_CON(13), 8, 1, MFLAGS), ··· 301 299 COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED, 302 300 RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t), 303 301 304 - GATE(0, "sclk_ddr", "ddrphy_div4", CLK_IGNORE_UNUSED, 302 + FACTOR_GATE(0, "sclk_ddr", "ddrphy_src", CLK_IGNORE_UNUSED, 1, 4, 305 303 RK3368_CLKGATE_CON(6), 14, GFLAGS), 306 304 GATE(0, "sclk_ddr4x", "ddrphy_src", CLK_IGNORE_UNUSED, 307 305 RK3368_CLKGATE_CON(6), 15, GFLAGS), ··· 355 353 COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT, 356 354 RK3368_CLKSEL_CON(32), 0, 357 355 RK3368_CLKGATE_CON(6), 5, GFLAGS), 358 - COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0, 356 + COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, 359 357 RK3368_CLKSEL_CON(31), 8, 2, MFLAGS, 360 358 RK3368_CLKGATE_CON(6), 6, GFLAGS), 361 359 COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0, ··· 364 362 COMPOSITE_FRAC(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT, 365 363 RK3368_CLKSEL_CON(54), 0, 366 364 RK3368_CLKGATE_CON(5), 14, GFLAGS), 367 - COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p, 0, 365 + COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p, CLK_SET_RATE_PARENT, 368 366 RK3368_CLKSEL_CON(53), 8, 2, MFLAGS, 369 367 RK3368_CLKGATE_CON(5), 15, GFLAGS), 370 368 ··· 386 384 * Clock-Architecture Diagram 3 387 385 */ 388 386 389 - COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb_p, 0, 387 + COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0, 390 388 RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS, 391 389 RK3368_CLKGATE_CON(4), 6, GFLAGS), 392 - COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb_p, 0, 390 + COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0, 393 391 RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS, 394 392 RK3368_CLKGATE_CON(4), 7, GFLAGS), 395 393 396 394 /* 397 - * We introduce a virtual node of hclk_vodec_pre_v to split one clock 398 - * struct with a gate and a fix divider into two node in software. 395 + * We use aclk_vdpu by default ---GRF_SOC_CON0[7] setting in system, 396 + * so we ignore the mux and make clocks nodes as following, 399 397 */ 400 - GATE(0, "hclk_video_pre_v", "aclk_vdpu", 0, 398 + FACTOR_GATE(0, "hclk_video_pre", "aclk_vdpu", 0, 1, 4, 401 399 RK3368_CLKGATE_CON(4), 8, GFLAGS), 402 400 403 401 COMPOSITE(0, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_npll_usb_p, 0, ··· 444 442 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, 445 443 RK3368_CLKGATE_CON(4), 13, GFLAGS), 446 444 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0, 447 - RK3368_CLKGATE_CON(5), 12, GFLAGS), 445 + RK3368_CLKGATE_CON(4), 12, GFLAGS), 448 446 449 447 COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0, 450 448 RK3368_CLKSEL_CON(21), 15, 1, MFLAGS, ··· 843 841 } 844 842 845 843 rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 846 - 847 - /* xin12m is created by a cru-internal divider */ 848 - clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); 849 - if (IS_ERR(clk)) 850 - pr_warn("%s: could not register clock xin12m: %ld\n", 851 - __func__, PTR_ERR(clk)); 852 - 853 - /* ddrphy_div4 is created by a cru-internal divider */ 854 - clk = clk_register_fixed_factor(NULL, "ddrphy_div4", "ddrphy_src", 0, 1, 4); 855 - if (IS_ERR(clk)) 856 - pr_warn("%s: could not register clock xin12m: %ld\n", 857 - __func__, PTR_ERR(clk)); 858 - 859 - clk = clk_register_fixed_factor(NULL, "hclk_video_pre", 860 - "hclk_video_pre_v", 0, 1, 4); 861 - if (IS_ERR(clk)) 862 - pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", 863 - __func__, PTR_ERR(clk)); 864 844 865 845 /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */ 866 846 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);

+62 -2

drivers/clk/rockchip/clk.c

··· 70 70 if (gate_offset >= 0) { 71 71 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 72 72 if (!gate) 73 - return ERR_PTR(-ENOMEM); 73 + goto err_gate; 74 74 75 75 gate->flags = gate_flags; 76 76 gate->reg = base + gate_offset; ··· 82 82 if (div_width > 0) { 83 83 div = kzalloc(sizeof(*div), GFP_KERNEL); 84 84 if (!div) 85 - return ERR_PTR(-ENOMEM); 85 + goto err_div; 86 86 87 87 div->flags = div_flags; 88 88 div->reg = base + muxdiv_offset; ··· 102 102 flags); 103 103 104 104 return clk; 105 + err_div: 106 + kfree(gate); 107 + err_gate: 108 + kfree(mux); 109 + return ERR_PTR(-ENOMEM); 105 110 } 106 111 107 112 struct rockchip_clk_frac { ··· 267 262 return clk; 268 263 } 269 264 265 + static struct clk *rockchip_clk_register_factor_branch(const char *name, 266 + const char *const *parent_names, u8 num_parents, 267 + void __iomem *base, unsigned int mult, unsigned int div, 268 + int gate_offset, u8 gate_shift, u8 gate_flags, 269 + unsigned long flags, spinlock_t *lock) 270 + { 271 + struct clk *clk; 272 + struct clk_gate *gate = NULL; 273 + struct clk_fixed_factor *fix = NULL; 274 + 275 + /* without gate, register a simple factor clock */ 276 + if (gate_offset == 0) { 277 + return clk_register_fixed_factor(NULL, name, 278 + parent_names[0], flags, mult, 279 + div); 280 + } 281 + 282 + gate = kzalloc(sizeof(*gate), GFP_KERNEL); 283 + if (!gate) 284 + return ERR_PTR(-ENOMEM); 285 + 286 + gate->flags = gate_flags; 287 + gate->reg = base + gate_offset; 288 + gate->bit_idx = gate_shift; 289 + gate->lock = lock; 290 + 291 + fix = kzalloc(sizeof(*fix), GFP_KERNEL); 292 + if (!fix) { 293 + kfree(gate); 294 + return ERR_PTR(-ENOMEM); 295 + } 296 + 297 + fix->mult = mult; 298 + fix->div = div; 299 + 300 + clk = clk_register_composite(NULL, name, parent_names, num_parents, 301 + NULL, NULL, 302 + &fix->hw, &clk_fixed_factor_ops, 303 + &gate->hw, &clk_gate_ops, flags); 304 + if (IS_ERR(clk)) { 305 + kfree(fix); 306 + kfree(gate); 307 + } 308 + 309 + return clk; 310 + } 311 + 270 312 static DEFINE_SPINLOCK(clk_lock); 271 313 static struct clk **clk_table; 272 314 static void __iomem *reg_base; ··· 448 396 list->num_parents, 449 397 reg_base + list->muxdiv_offset, 450 398 list->div_shift, list->div_flags, &clk_lock); 399 + break; 400 + case branch_factor: 401 + clk = rockchip_clk_register_factor_branch( 402 + list->name, list->parent_names, 403 + list->num_parents, reg_base, 404 + list->div_shift, list->div_width, 405 + list->gate_offset, list->gate_shift, 406 + list->gate_flags, flags, &clk_lock); 451 407 break; 452 408 } 453 409

+28

drivers/clk/rockchip/clk.h

··· 254 254 branch_gate, 255 255 branch_mmc, 256 256 branch_inverter, 257 + branch_factor, 257 258 }; 258 259 259 260 struct rockchip_clk_branch { ··· 507 506 .muxdiv_offset = io, \ 508 507 .div_shift = is, \ 509 508 .div_flags = if, \ 509 + } 510 + 511 + #define FACTOR(_id, cname, pname, f, fm, fd) \ 512 + { \ 513 + .id = _id, \ 514 + .branch_type = branch_factor, \ 515 + .name = cname, \ 516 + .parent_names = (const char *[]){ pname }, \ 517 + .num_parents = 1, \ 518 + .flags = f, \ 519 + .div_shift = fm, \ 520 + .div_width = fd, \ 521 + } 522 + 523 + #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \ 524 + { \ 525 + .id = _id, \ 526 + .branch_type = branch_factor, \ 527 + .name = cname, \ 528 + .parent_names = (const char *[]){ pname }, \ 529 + .num_parents = 1, \ 530 + .flags = f, \ 531 + .div_shift = fm, \ 532 + .div_width = fd, \ 533 + .gate_offset = go, \ 534 + .gate_shift = gb, \ 535 + .gate_flags = gf, \ 510 536 } 511 537 512 538 void rockchip_clk_init(struct device_node *np, void __iomem *base,

+1

include/dt-bindings/clock/rk3188-cru-common.h

··· 55 55 #define SCLK_TIMER6 90 56 56 #define SCLK_JTAG 91 57 57 #define SCLK_SMC 92 58 + #define SCLK_TSADC 93 58 59 59 60 #define DCLK_LCDC0 190 60 61 #define DCLK_LCDC1 191