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MIPS: bmips: Add support PCIe controller device nodes
For Broadcom STB PCIe HW. The 7425 and 7435 are MIPs-based SOCs. Not much
difference between the two for the DT properties except that they have
slightly different PCIe interrupt assignments.
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
authored by
Jim Quinlan
and committed by
Thomas Bogendoerfer
6fffb01e
145790e5
+78
+30
arch/mips/boot/dts/brcm/bcm7425.dtsi
+30
arch/mips/boot/dts/brcm/bcm7425.dtsi
···
584
584
};
585
585
};
586
586
};
587
+
588
+
pcie_0: pcie@8b20000 {
589
+
status = "disabled";
590
+
compatible = "brcm,bcm7425-pcie";
591
+
592
+
ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0x0 0x08000000
593
+
0x02000000 0x0 0xd8000000 0xd8000000 0x0 0x08000000
594
+
0x02000000 0x0 0xe0000000 0xe0000000 0x0 0x08000000
595
+
0x02000000 0x0 0xe8000000 0xe8000000 0x0 0x08000000>;
596
+
597
+
reg = <0x10410000 0x19310>;
598
+
aspm-no-l0s;
599
+
device_type = "pci";
600
+
msi-controller;
601
+
msi-parent = <&pcie_0>;
602
+
#address-cells = <0x3>;
603
+
#size-cells = <0x2>;
604
+
bus-range = <0x0 0xff>;
605
+
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
606
+
linux,pci-domain = <0x0>;
607
+
608
+
interrupt-parent = <&periph_intc>;
609
+
interrupts = <37>, <37>;
610
+
interrupt-names = "pcie", "msi";
611
+
#interrupt-cells = <0x1>;
612
+
interrupt-map = <0 0 0 1 &periph_intc 0x21
613
+
0 0 0 1 &periph_intc 0x22
614
+
0 0 0 1 &periph_intc 0x23
615
+
0 0 0 1 &periph_intc 0x24>;
616
+
};
587
617
};
+30
arch/mips/boot/dts/brcm/bcm7435.dtsi
+30
arch/mips/boot/dts/brcm/bcm7435.dtsi
···
599
599
};
600
600
};
601
601
};
602
+
603
+
pcie_0: pcie@8b20000 {
604
+
status = "disabled";
605
+
compatible = "brcm,bcm7435-pcie";
606
+
607
+
ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0x0 0x08000000
608
+
0x02000000 0x0 0xd8000000 0xd8000000 0x0 0x08000000
609
+
0x02000000 0x0 0xe0000000 0xe0000000 0x0 0x08000000
610
+
0x02000000 0x0 0xe8000000 0xe8000000 0x0 0x08000000>;
611
+
612
+
reg = <0x10410000 0x19310>;
613
+
aspm-no-l0s;
614
+
device_type = "pci";
615
+
msi-controller;
616
+
msi-parent = <&pcie_0>;
617
+
#address-cells = <0x3>;
618
+
#size-cells = <0x2>;
619
+
bus-range = <0x0 0xff>;
620
+
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
621
+
linux,pci-domain = <0x0>;
622
+
623
+
interrupt-parent = <&periph_intc>;
624
+
interrupts = <39>, <39>;
625
+
interrupt-names = "pcie", "msi";
626
+
#interrupt-cells = <0x1>;
627
+
interrupt-map = <0 0 0 1 &periph_intc 0x23
628
+
0 0 0 1 &periph_intc 0x24
629
+
0 0 0 1 &periph_intc 0x25
630
+
0 0 0 1 &periph_intc 0x26>;
631
+
};
602
632
};
+9
arch/mips/boot/dts/brcm/bcm97425svmb.dts
+9
arch/mips/boot/dts/brcm/bcm97425svmb.dts
···
152
152
&waketimer {
153
153
status = "okay";
154
154
};
155
+
156
+
&pcie_0 {
157
+
status = "okay";
158
+
/* 1GB Memc0, 1GB Memc1 */
159
+
brcm,scb-sizes = <0 0x40000000 0 0x40000000>;
160
+
dma-ranges = <0x43000000 0x00000000 0x00000000 0x00000000 0x0 0x10000000
161
+
0x43000000 0x00000000 0x10000000 0x20000000 0x0 0x30000000
162
+
0x43000000 0x00000000 0x40000000 0x90000000 0x0 0x40000000>;
163
+
};
+9
arch/mips/boot/dts/brcm/bcm97435svmb.dts
+9
arch/mips/boot/dts/brcm/bcm97435svmb.dts
···
128
128
&waketimer {
129
129
status = "okay";
130
130
};
131
+
132
+
&pcie_0 {
133
+
status = "okay";
134
+
/* 1GB Memc0, 1GB Memc1 */
135
+
brcm,scb-sizes = <0 0x40000000 0 0x40000000>;
136
+
dma-ranges = <0x43000000 0x00000000 0x00000000 0x00000000 0x0 0x10000000
137
+
0x43000000 0x00000000 0x10000000 0x20000000 0x0 0x30000000
138
+
0x43000000 0x00000000 0x40000000 0x90000000 0x0 0x40000000>;
139
+
};