tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: Add r8a7744 CPG Core Clock Definitions
Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's
Manual.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Biju Das
and committed by
Geert Uytterhoeven
6ff9cb53
bbd71915
+39
+39
include/dt-bindings/clock/r8a7744-cpg-mssr.h
+39
include/dt-bindings/clock/r8a7744-cpg-mssr.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0
2
+
*
3
+
* Copyright (C) 2018 Renesas Electronics Corp.
4
+
*/
5
+
#ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
6
+
#define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
7
+
8
+
#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
+
10
+
/* r8a7744 CPG Core Clocks */
11
+
#define R8A7744_CLK_Z 0
12
+
#define R8A7744_CLK_ZG 1
13
+
#define R8A7744_CLK_ZTR 2
14
+
#define R8A7744_CLK_ZTRD2 3
15
+
#define R8A7744_CLK_ZT 4
16
+
#define R8A7744_CLK_ZX 5
17
+
#define R8A7744_CLK_ZS 6
18
+
#define R8A7744_CLK_HP 7
19
+
#define R8A7744_CLK_B 9
20
+
#define R8A7744_CLK_LB 10
21
+
#define R8A7744_CLK_P 11
22
+
#define R8A7744_CLK_CL 12
23
+
#define R8A7744_CLK_M2 13
24
+
#define R8A7744_CLK_ZB3 15
25
+
#define R8A7744_CLK_ZB3D2 16
26
+
#define R8A7744_CLK_DDR 17
27
+
#define R8A7744_CLK_SDH 18
28
+
#define R8A7744_CLK_SD0 19
29
+
#define R8A7744_CLK_SD2 20
30
+
#define R8A7744_CLK_SD3 21
31
+
#define R8A7744_CLK_MMC0 22
32
+
#define R8A7744_CLK_MP 23
33
+
#define R8A7744_CLK_QSPI 26
34
+
#define R8A7744_CLK_CP 27
35
+
#define R8A7744_CLK_RCAN 28
36
+
#define R8A7744_CLK_R 29
37
+
#define R8A7744_CLK_OSC 30
38
+
39
+
#endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */