···18441844brcmf_add_keyext(struct wiphy *wiphy, struct net_device *ndev,18451845 u8 key_idx, const u8 *mac_addr, struct key_params *params)18461846{18471847+ struct brcmf_if *ifp = netdev_priv(ndev);18471848 struct brcmf_wsec_key key;18481849 s32 err = 0;18501850+ u8 keybuf[8];1849185118501852 memset(&key, 0, sizeof(key));18511853 key.index = (u32) key_idx;···18711869 brcmf_dbg(CONN, "Setting the key index %d\n", key.index);18721870 memcpy(key.data, params->key, key.len);1873187118741874- if (params->cipher == WLAN_CIPHER_SUITE_TKIP) {18751875- u8 keybuf[8];18721872+ if ((ifp->vif->mode != WL_MODE_AP) &&18731873+ (params->cipher == WLAN_CIPHER_SUITE_TKIP)) {18741874+ brcmf_dbg(CONN, "Swapping RX/TX MIC key\n");18761875 memcpy(keybuf, &key.data[24], sizeof(keybuf));18771876 memcpy(&key.data[24], &key.data[16], sizeof(keybuf));18781877 memcpy(&key.data[16], keybuf, sizeof(keybuf));···19691966 break;19701967 case WLAN_CIPHER_SUITE_TKIP:19711968 if (ifp->vif->mode != WL_MODE_AP) {19721972- brcmf_dbg(CONN, "Swapping key\n");19691969+ brcmf_dbg(CONN, "Swapping RX/TX MIC key\n");19731970 memcpy(keybuf, &key.data[24], sizeof(keybuf));19741971 memcpy(&key.data[24], &key.data[16], sizeof(keybuf));19751972 memcpy(&key.data[16], keybuf, sizeof(keybuf));···20742071 err = -EAGAIN;20752072 goto done;20762073 }20772077- switch (wsec & ~SES_OW_ENABLED) {20782078- case WEP_ENABLED:20742074+ if (wsec & WEP_ENABLED) {20792075 sec = &profile->sec;20802076 if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP40) {20812077 params.cipher = WLAN_CIPHER_SUITE_WEP40;···20832081 params.cipher = WLAN_CIPHER_SUITE_WEP104;20842082 brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP104\n");20852083 }20862086- break;20872087- case TKIP_ENABLED:20842084+ } else if (wsec & TKIP_ENABLED) {20882085 params.cipher = WLAN_CIPHER_SUITE_TKIP;20892086 brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_TKIP\n");20902090- break;20912091- case AES_ENABLED:20872087+ } else if (wsec & AES_ENABLED) {20922088 params.cipher = WLAN_CIPHER_SUITE_AES_CMAC;20932089 brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_AES_CMAC\n");20942094- break;20952095- default:20902090+ } else {20962091 brcmf_err("Invalid algo (0x%x)\n", wsec);20972092 err = -EINVAL;20982093 goto done;···37733774static int brcmf_cfg80211_stop_ap(struct wiphy *wiphy, struct net_device *ndev)37743775{37753776 struct brcmf_if *ifp = netdev_priv(ndev);37763776- s32 err = -EPERM;37773777+ s32 err;37773778 struct brcmf_fil_bss_enable_le bss_enable;37793779+ struct brcmf_join_params join_params;3778378037793781 brcmf_dbg(TRACE, "Enter\n");37803782···37833783 /* Due to most likely deauths outstanding we sleep */37843784 /* first to make sure they get processed by fw. */37853785 msleep(400);37863786- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_AP, 0);37873787- if (err < 0) {37883788- brcmf_err("setting AP mode failed %d\n", err);37893789- goto exit;37903790- }37863786+37873787+ memset(&join_params, 0, sizeof(join_params));37883788+ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_SSID,37893789+ &join_params, sizeof(join_params));37903790+ if (err < 0)37913791+ brcmf_err("SET SSID error (%d)\n", err);37913792 err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_UP, 0);37923792- if (err < 0) {37933793+ if (err < 0)37933794 brcmf_err("BRCMF_C_UP error %d\n", err);37943794- goto exit;37953795- }37953795+ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_AP, 0);37963796+ if (err < 0)37973797+ brcmf_err("setting AP mode failed %d\n", err);37983798+ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_INFRA, 0);37993799+ if (err < 0)38003800+ brcmf_err("setting INFRA mode failed %d\n", err);37963801 } else {37973802 bss_enable.bsscfg_idx = cpu_to_le32(ifp->bssidx);37983803 bss_enable.enable = cpu_to_le32(0);···38103805 set_bit(BRCMF_VIF_STATUS_AP_CREATING, &ifp->vif->sme_state);38113806 clear_bit(BRCMF_VIF_STATUS_AP_CREATED, &ifp->vif->sme_state);3812380738133813-exit:38143808 return err;38153809}38163810
+8-10
drivers/net/wireless/iwlwifi/dvm/rxon.c
···1419141914201420 mutex_lock(&priv->mutex);1421142114221422+ if (changes & BSS_CHANGED_IDLE && bss_conf->idle) {14231423+ /*14241424+ * If we go idle, then clearly no "passive-no-rx"14251425+ * workaround is needed any more, this is a reset.14261426+ */14271427+ iwlagn_lift_passive_no_rx(priv);14281428+ }14291429+14221430 if (unlikely(!iwl_is_ready(priv))) {14231431 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");14241432 mutex_unlock(&priv->mutex);···14581450 priv->timestamp = bss_conf->sync_tsf;14591451 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;14601452 } else {14611461- /*14621462- * If we disassociate while there are pending14631463- * frames, just wake up the queues and let the14641464- * frames "escape" ... This shouldn't really14651465- * be happening to start with, but we should14661466- * not get stuck in this case either since it14671467- * can happen if userspace gets confused.14681468- */14691469- iwlagn_lift_passive_no_rx(priv);14701470-14711453 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;1472145414731455 if (ctx->ctxid == IWL_RXON_CTX_BSS)
+1-1
drivers/net/wireless/iwlwifi/dvm/tx.c
···11931193 memset(&info->status, 0, sizeof(info->status));1194119411951195 if (status == TX_STATUS_FAIL_PASSIVE_NO_RX &&11961196- iwl_is_associated_ctx(ctx) && ctx->vif &&11961196+ ctx->vif &&11971197 ctx->vif->type == NL80211_IFTYPE_STATION) {11981198 /* block and stop all queues */11991199 priv->passive_no_rx = true;
+2-1
drivers/net/wireless/mwifiex/cfg80211.c
···19041904 }19051905 }1906190619071907- for (i = 0; i < request->n_channels; i++) {19071907+ for (i = 0; i < min_t(u32, request->n_channels,19081908+ MWIFIEX_USER_SCAN_CHAN_MAX); i++) {19081909 chan = request->channels[i];19091910 priv->user_scan_cfg->chan_list[i].chan_number = chan->hw_value;19101911 priv->user_scan_cfg->chan_list[i].radio_type = chan->band;
+9-2
drivers/net/wireless/mwifiex/scan.c
···13931393 queue_work(adapter->workqueue, &adapter->main_work);1394139413951395 /* Perform internal scan synchronously */13961396- if (!priv->scan_request)13961396+ if (!priv->scan_request) {13971397+ dev_dbg(adapter->dev, "wait internal scan\n");13971398 mwifiex_wait_queue_complete(adapter, cmd_node);13991399+ }13981400 } else {13991401 spin_unlock_irqrestore(&adapter->scan_pending_q_lock,14001402 flags);···17951793 /* Need to indicate IOCTL complete */17961794 if (adapter->curr_cmd->wait_q_enabled) {17971795 adapter->cmd_wait_q.status = 0;17981798- mwifiex_complete_cmd(adapter, adapter->curr_cmd);17961796+ if (!priv->scan_request) {17971797+ dev_dbg(adapter->dev,17981798+ "complete internal scan\n");17991799+ mwifiex_complete_cmd(adapter,18001800+ adapter->curr_cmd);18011801+ }17991802 }18001803 if (priv->report_scan_result)18011804 priv->report_scan_result = false;
···11+/*22+ Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>33+ <http://rt2x00.serialmonkey.com>44+55+ This program is free software; you can redistribute it and/or modify66+ it under the terms of the GNU General Public License as published by77+ the Free Software Foundation; either version 2 of the License, or88+ (at your option) any later version.99+1010+ This program is distributed in the hope that it will be useful,1111+ but WITHOUT ANY WARRANTY; without even the implied warranty of1212+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the1313+ GNU General Public License for more details.1414+1515+ You should have received a copy of the GNU General Public License1616+ along with this program; if not, write to the1717+ Free Software Foundation, Inc.,1818+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.1919+ */2020+2121+/*2222+ Module: rt2x00mmio2323+ Abstract: rt2x00 generic mmio device routines.2424+ */2525+2626+#include <linux/dma-mapping.h>2727+#include <linux/kernel.h>2828+#include <linux/module.h>2929+#include <linux/slab.h>3030+3131+#include "rt2x00.h"3232+#include "rt2x00mmio.h"3333+3434+/*3535+ * Register access.3636+ */3737+int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,3838+ const unsigned int offset,3939+ const struct rt2x00_field32 field,4040+ u32 *reg)4141+{4242+ unsigned int i;4343+4444+ if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))4545+ return 0;4646+4747+ for (i = 0; i < REGISTER_BUSY_COUNT; i++) {4848+ rt2x00pci_register_read(rt2x00dev, offset, reg);4949+ if (!rt2x00_get_field32(*reg, field))5050+ return 1;5151+ udelay(REGISTER_BUSY_DELAY);5252+ }5353+5454+ printk_once(KERN_ERR "%s() Indirect register access failed: "5555+ "offset=0x%.08x, value=0x%.08x\n", __func__, offset, *reg);5656+ *reg = ~0;5757+5858+ return 0;5959+}6060+EXPORT_SYMBOL_GPL(rt2x00pci_regbusy_read);6161+6262+bool rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)6363+{6464+ struct data_queue *queue = rt2x00dev->rx;6565+ struct queue_entry *entry;6666+ struct queue_entry_priv_pci *entry_priv;6767+ struct skb_frame_desc *skbdesc;6868+ int max_rx = 16;6969+7070+ while (--max_rx) {7171+ entry = rt2x00queue_get_entry(queue, Q_INDEX);7272+ entry_priv = entry->priv_data;7373+7474+ if (rt2x00dev->ops->lib->get_entry_state(entry))7575+ break;7676+7777+ /*7878+ * Fill in desc fields of the skb descriptor7979+ */8080+ skbdesc = get_skb_frame_desc(entry->skb);8181+ skbdesc->desc = entry_priv->desc;8282+ skbdesc->desc_len = entry->queue->desc_size;8383+8484+ /*8585+ * DMA is already done, notify rt2x00lib that8686+ * it finished successfully.8787+ */8888+ rt2x00lib_dmastart(entry);8989+ rt2x00lib_dmadone(entry);9090+9191+ /*9292+ * Send the frame to rt2x00lib for further processing.9393+ */9494+ rt2x00lib_rxdone(entry, GFP_ATOMIC);9595+ }9696+9797+ return !max_rx;9898+}9999+EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);100100+101101+void rt2x00pci_flush_queue(struct data_queue *queue, bool drop)102102+{103103+ unsigned int i;104104+105105+ for (i = 0; !rt2x00queue_empty(queue) && i < 10; i++)106106+ msleep(10);107107+}108108+EXPORT_SYMBOL_GPL(rt2x00pci_flush_queue);109109+110110+/*111111+ * Device initialization handlers.112112+ */113113+static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,114114+ struct data_queue *queue)115115+{116116+ struct queue_entry_priv_pci *entry_priv;117117+ void *addr;118118+ dma_addr_t dma;119119+ unsigned int i;120120+121121+ /*122122+ * Allocate DMA memory for descriptor and buffer.123123+ */124124+ addr = dma_alloc_coherent(rt2x00dev->dev,125125+ queue->limit * queue->desc_size,126126+ &dma, GFP_KERNEL);127127+ if (!addr)128128+ return -ENOMEM;129129+130130+ memset(addr, 0, queue->limit * queue->desc_size);131131+132132+ /*133133+ * Initialize all queue entries to contain valid addresses.134134+ */135135+ for (i = 0; i < queue->limit; i++) {136136+ entry_priv = queue->entries[i].priv_data;137137+ entry_priv->desc = addr + i * queue->desc_size;138138+ entry_priv->desc_dma = dma + i * queue->desc_size;139139+ }140140+141141+ return 0;142142+}143143+144144+static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,145145+ struct data_queue *queue)146146+{147147+ struct queue_entry_priv_pci *entry_priv =148148+ queue->entries[0].priv_data;149149+150150+ if (entry_priv->desc)151151+ dma_free_coherent(rt2x00dev->dev,152152+ queue->limit * queue->desc_size,153153+ entry_priv->desc, entry_priv->desc_dma);154154+ entry_priv->desc = NULL;155155+}156156+157157+int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)158158+{159159+ struct data_queue *queue;160160+ int status;161161+162162+ /*163163+ * Allocate DMA164164+ */165165+ queue_for_each(rt2x00dev, queue) {166166+ status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);167167+ if (status)168168+ goto exit;169169+ }170170+171171+ /*172172+ * Register interrupt handler.173173+ */174174+ status = request_irq(rt2x00dev->irq,175175+ rt2x00dev->ops->lib->irq_handler,176176+ IRQF_SHARED, rt2x00dev->name, rt2x00dev);177177+ if (status) {178178+ ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",179179+ rt2x00dev->irq, status);180180+ goto exit;181181+ }182182+183183+ return 0;184184+185185+exit:186186+ queue_for_each(rt2x00dev, queue)187187+ rt2x00pci_free_queue_dma(rt2x00dev, queue);188188+189189+ return status;190190+}191191+EXPORT_SYMBOL_GPL(rt2x00pci_initialize);192192+193193+void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)194194+{195195+ struct data_queue *queue;196196+197197+ /*198198+ * Free irq line.199199+ */200200+ free_irq(rt2x00dev->irq, rt2x00dev);201201+202202+ /*203203+ * Free DMA204204+ */205205+ queue_for_each(rt2x00dev, queue)206206+ rt2x00pci_free_queue_dma(rt2x00dev, queue);207207+}208208+EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);209209+210210+/*211211+ * rt2x00mmio module information.212212+ */213213+MODULE_AUTHOR(DRV_PROJECT);214214+MODULE_VERSION(DRV_VERSION);215215+MODULE_DESCRIPTION("rt2x00 mmio library");216216+MODULE_LICENSE("GPL");
+119
drivers/net/wireless/rt2x00/rt2x00mmio.h
···11+/*22+ Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>33+ <http://rt2x00.serialmonkey.com>44+55+ This program is free software; you can redistribute it and/or modify66+ it under the terms of the GNU General Public License as published by77+ the Free Software Foundation; either version 2 of the License, or88+ (at your option) any later version.99+1010+ This program is distributed in the hope that it will be useful,1111+ but WITHOUT ANY WARRANTY; without even the implied warranty of1212+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the1313+ GNU General Public License for more details.1414+1515+ You should have received a copy of the GNU General Public License1616+ along with this program; if not, write to the1717+ Free Software Foundation, Inc.,1818+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.1919+ */2020+2121+/*2222+ Module: rt2x00mmio2323+ Abstract: Data structures for the rt2x00mmio module.2424+ */2525+2626+#ifndef RT2X00MMIO_H2727+#define RT2X00MMIO_H2828+2929+#include <linux/io.h>3030+3131+/*3232+ * Register access.3333+ */3434+static inline void rt2x00pci_register_read(struct rt2x00_dev *rt2x00dev,3535+ const unsigned int offset,3636+ u32 *value)3737+{3838+ *value = readl(rt2x00dev->csr.base + offset);3939+}4040+4141+static inline void rt2x00pci_register_multiread(struct rt2x00_dev *rt2x00dev,4242+ const unsigned int offset,4343+ void *value, const u32 length)4444+{4545+ memcpy_fromio(value, rt2x00dev->csr.base + offset, length);4646+}4747+4848+static inline void rt2x00pci_register_write(struct rt2x00_dev *rt2x00dev,4949+ const unsigned int offset,5050+ u32 value)5151+{5252+ writel(value, rt2x00dev->csr.base + offset);5353+}5454+5555+static inline void rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev,5656+ const unsigned int offset,5757+ const void *value,5858+ const u32 length)5959+{6060+ __iowrite32_copy(rt2x00dev->csr.base + offset, value, length >> 2);6161+}6262+6363+/**6464+ * rt2x00pci_regbusy_read - Read from register with busy check6565+ * @rt2x00dev: Device pointer, see &struct rt2x00_dev.6666+ * @offset: Register offset6767+ * @field: Field to check if register is busy6868+ * @reg: Pointer to where register contents should be stored6969+ *7070+ * This function will read the given register, and checks if the7171+ * register is busy. If it is, it will sleep for a couple of7272+ * microseconds before reading the register again. If the register7373+ * is not read after a certain timeout, this function will return7474+ * FALSE.7575+ */7676+int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,7777+ const unsigned int offset,7878+ const struct rt2x00_field32 field,7979+ u32 *reg);8080+8181+/**8282+ * struct queue_entry_priv_pci: Per entry PCI specific information8383+ *8484+ * @desc: Pointer to device descriptor8585+ * @desc_dma: DMA pointer to &desc.8686+ * @data: Pointer to device's entry memory.8787+ * @data_dma: DMA pointer to &data.8888+ */8989+struct queue_entry_priv_pci {9090+ __le32 *desc;9191+ dma_addr_t desc_dma;9292+};9393+9494+/**9595+ * rt2x00pci_rxdone - Handle RX done events9696+ * @rt2x00dev: Device pointer, see &struct rt2x00_dev.9797+ *9898+ * Returns true if there are still rx frames pending and false if all9999+ * pending rx frames were processed.100100+ */101101+bool rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev);102102+103103+/**104104+ * rt2x00pci_flush_queue - Flush data queue105105+ * @queue: Data queue to stop106106+ * @drop: True to drop all pending frames.107107+ *108108+ * This will wait for a maximum of 100ms, waiting for the queues109109+ * to become empty.110110+ */111111+void rt2x00pci_flush_queue(struct data_queue *queue, bool drop);112112+113113+/*114114+ * Device initialization handlers.115115+ */116116+int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev);117117+void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev);118118+119119+#endif /* RT2X00MMIO_H */
-176
drivers/net/wireless/rt2x00/rt2x00pci.c
···3333#include "rt2x00pci.h"34343535/*3636- * Register access.3737- */3838-int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,3939- const unsigned int offset,4040- const struct rt2x00_field32 field,4141- u32 *reg)4242-{4343- unsigned int i;4444-4545- if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))4646- return 0;4747-4848- for (i = 0; i < REGISTER_BUSY_COUNT; i++) {4949- rt2x00pci_register_read(rt2x00dev, offset, reg);5050- if (!rt2x00_get_field32(*reg, field))5151- return 1;5252- udelay(REGISTER_BUSY_DELAY);5353- }5454-5555- printk_once(KERN_ERR "%s() Indirect register access failed: "5656- "offset=0x%.08x, value=0x%.08x\n", __func__, offset, *reg);5757- *reg = ~0;5858-5959- return 0;6060-}6161-EXPORT_SYMBOL_GPL(rt2x00pci_regbusy_read);6262-6363-bool rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)6464-{6565- struct data_queue *queue = rt2x00dev->rx;6666- struct queue_entry *entry;6767- struct queue_entry_priv_pci *entry_priv;6868- struct skb_frame_desc *skbdesc;6969- int max_rx = 16;7070-7171- while (--max_rx) {7272- entry = rt2x00queue_get_entry(queue, Q_INDEX);7373- entry_priv = entry->priv_data;7474-7575- if (rt2x00dev->ops->lib->get_entry_state(entry))7676- break;7777-7878- /*7979- * Fill in desc fields of the skb descriptor8080- */8181- skbdesc = get_skb_frame_desc(entry->skb);8282- skbdesc->desc = entry_priv->desc;8383- skbdesc->desc_len = entry->queue->desc_size;8484-8585- /*8686- * DMA is already done, notify rt2x00lib that8787- * it finished successfully.8888- */8989- rt2x00lib_dmastart(entry);9090- rt2x00lib_dmadone(entry);9191-9292- /*9393- * Send the frame to rt2x00lib for further processing.9494- */9595- rt2x00lib_rxdone(entry, GFP_ATOMIC);9696- }9797-9898- return !max_rx;9999-}100100-EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);101101-102102-void rt2x00pci_flush_queue(struct data_queue *queue, bool drop)103103-{104104- unsigned int i;105105-106106- for (i = 0; !rt2x00queue_empty(queue) && i < 10; i++)107107- msleep(10);108108-}109109-EXPORT_SYMBOL_GPL(rt2x00pci_flush_queue);110110-111111-/*112112- * Device initialization handlers.113113- */114114-static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,115115- struct data_queue *queue)116116-{117117- struct queue_entry_priv_pci *entry_priv;118118- void *addr;119119- dma_addr_t dma;120120- unsigned int i;121121-122122- /*123123- * Allocate DMA memory for descriptor and buffer.124124- */125125- addr = dma_alloc_coherent(rt2x00dev->dev,126126- queue->limit * queue->desc_size,127127- &dma, GFP_KERNEL);128128- if (!addr)129129- return -ENOMEM;130130-131131- memset(addr, 0, queue->limit * queue->desc_size);132132-133133- /*134134- * Initialize all queue entries to contain valid addresses.135135- */136136- for (i = 0; i < queue->limit; i++) {137137- entry_priv = queue->entries[i].priv_data;138138- entry_priv->desc = addr + i * queue->desc_size;139139- entry_priv->desc_dma = dma + i * queue->desc_size;140140- }141141-142142- return 0;143143-}144144-145145-static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,146146- struct data_queue *queue)147147-{148148- struct queue_entry_priv_pci *entry_priv =149149- queue->entries[0].priv_data;150150-151151- if (entry_priv->desc)152152- dma_free_coherent(rt2x00dev->dev,153153- queue->limit * queue->desc_size,154154- entry_priv->desc, entry_priv->desc_dma);155155- entry_priv->desc = NULL;156156-}157157-158158-int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)159159-{160160- struct data_queue *queue;161161- int status;162162-163163- /*164164- * Allocate DMA165165- */166166- queue_for_each(rt2x00dev, queue) {167167- status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);168168- if (status)169169- goto exit;170170- }171171-172172- /*173173- * Register interrupt handler.174174- */175175- status = request_irq(rt2x00dev->irq,176176- rt2x00dev->ops->lib->irq_handler,177177- IRQF_SHARED, rt2x00dev->name, rt2x00dev);178178- if (status) {179179- ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",180180- rt2x00dev->irq, status);181181- goto exit;182182- }183183-184184- return 0;185185-186186-exit:187187- queue_for_each(rt2x00dev, queue)188188- rt2x00pci_free_queue_dma(rt2x00dev, queue);189189-190190- return status;191191-}192192-EXPORT_SYMBOL_GPL(rt2x00pci_initialize);193193-194194-void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)195195-{196196- struct data_queue *queue;197197-198198- /*199199- * Free irq line.200200- */201201- free_irq(rt2x00dev->irq, rt2x00dev);202202-203203- /*204204- * Free DMA205205- */206206- queue_for_each(rt2x00dev, queue)207207- rt2x00pci_free_queue_dma(rt2x00dev, queue);208208-}209209-EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);210210-211211-/*21236 * PCI driver handlers.21337 */21438static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
-88
drivers/net/wireless/rt2x00/rt2x00pci.h
···3636#define PCI_DEVICE_DATA(__ops) .driver_data = (kernel_ulong_t)(__ops)37373838/*3939- * Register access.4040- */4141-static inline void rt2x00pci_register_read(struct rt2x00_dev *rt2x00dev,4242- const unsigned int offset,4343- u32 *value)4444-{4545- *value = readl(rt2x00dev->csr.base + offset);4646-}4747-4848-static inline void rt2x00pci_register_multiread(struct rt2x00_dev *rt2x00dev,4949- const unsigned int offset,5050- void *value, const u32 length)5151-{5252- memcpy_fromio(value, rt2x00dev->csr.base + offset, length);5353-}5454-5555-static inline void rt2x00pci_register_write(struct rt2x00_dev *rt2x00dev,5656- const unsigned int offset,5757- u32 value)5858-{5959- writel(value, rt2x00dev->csr.base + offset);6060-}6161-6262-static inline void rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev,6363- const unsigned int offset,6464- const void *value,6565- const u32 length)6666-{6767- __iowrite32_copy(rt2x00dev->csr.base + offset, value, length >> 2);6868-}6969-7070-/**7171- * rt2x00pci_regbusy_read - Read from register with busy check7272- * @rt2x00dev: Device pointer, see &struct rt2x00_dev.7373- * @offset: Register offset7474- * @field: Field to check if register is busy7575- * @reg: Pointer to where register contents should be stored7676- *7777- * This function will read the given register, and checks if the7878- * register is busy. If it is, it will sleep for a couple of7979- * microseconds before reading the register again. If the register8080- * is not read after a certain timeout, this function will return8181- * FALSE.8282- */8383-int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,8484- const unsigned int offset,8585- const struct rt2x00_field32 field,8686- u32 *reg);8787-8888-/**8989- * struct queue_entry_priv_pci: Per entry PCI specific information9090- *9191- * @desc: Pointer to device descriptor9292- * @desc_dma: DMA pointer to &desc.9393- * @data: Pointer to device's entry memory.9494- * @data_dma: DMA pointer to &data.9595- */9696-struct queue_entry_priv_pci {9797- __le32 *desc;9898- dma_addr_t desc_dma;9999-};100100-101101-/**102102- * rt2x00pci_rxdone - Handle RX done events103103- * @rt2x00dev: Device pointer, see &struct rt2x00_dev.104104- *105105- * Returns true if there are still rx frames pending and false if all106106- * pending rx frames were processed.107107- */108108-bool rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev);109109-110110-/**111111- * rt2x00pci_flush_queue - Flush data queue112112- * @queue: Data queue to stop113113- * @drop: True to drop all pending frames.114114- *115115- * This will wait for a maximum of 100ms, waiting for the queues116116- * to become empty.117117- */118118-void rt2x00pci_flush_queue(struct data_queue *queue, bool drop);119119-120120-/*121121- * Device initialization handlers.122122- */123123-int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev);124124-void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev);125125-126126-/*12739 * PCI driver handlers.12840 */12941int rt2x00pci_probe(struct pci_dev *pci_dev, const struct rt2x00_ops *ops);
···26412641 list_del(&dep->list);26422642 mutex_unlock(&local->mtx);2643264326442644- ieee80211_roc_notify_destroy(dep);26442644+ ieee80211_roc_notify_destroy(dep, true);26452645 return 0;26462646 }26472647···26812681 ieee80211_start_next_roc(local);26822682 mutex_unlock(&local->mtx);2683268326842684- ieee80211_roc_notify_destroy(found);26842684+ ieee80211_roc_notify_destroy(found, true);26852685 } else {26862686 /* work may be pending so use it all the time */26872687 found->abort = true;···2691269126922692 /* work will clean up etc */26932693 flush_delayed_work(&found->work);26942694+ WARN_ON(!found->to_be_freed);26952695+ kfree(found);26942696 }2695269726962698 return 0;
+14-3
net/mac80211/chan.c
···6363 enum ieee80211_chanctx_mode mode)6464{6565 struct ieee80211_chanctx *ctx;6666+ u32 changed;6667 int err;67686869 lockdep_assert_held(&local->chanctx_mtx);···7776 ctx->conf.rx_chains_dynamic = 1;7877 ctx->mode = mode;79787979+ /* acquire mutex to prevent idle from changing */8080+ mutex_lock(&local->mtx);8181+ /* turn idle off *before* setting channel -- some drivers need that */8282+ changed = ieee80211_idle_off(local);8383+ if (changed)8484+ ieee80211_hw_config(local, changed);8585+8086 if (!local->use_chanctx) {8187 local->_oper_channel_type =8288 cfg80211_get_chandef_type(chandef);···9385 err = drv_add_chanctx(local, ctx);9486 if (err) {9587 kfree(ctx);9696- return ERR_PTR(err);8888+ ctx = ERR_PTR(err);8989+9090+ ieee80211_recalc_idle(local);9191+ goto out;9792 }9893 }99949595+ /* and keep the mutex held until the new chanctx is on the list */10096 list_add_rcu(&ctx->list, &local->chanctx_list);10197102102- mutex_lock(&local->mtx);103103- ieee80211_recalc_idle(local);9898+ out:10499 mutex_unlock(&local->mtx);105100106101 return ctx;