tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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[MIPS] TX49x7: Fix timer register #define's Fix the #define's for TX4927/37 timer reg's to match the datasheets (those Signed-off-by: Konstantin Baydarov <kbaidarov@mvista.com> Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Sergei Shtylylov and committed by
Ralf Baechle 6fe2a568 4feb8f8f

+10 -11
+10 -11
include/asm-mips/tx4927/tx4927.h
··· 2 2 * Author: MontaVista Software, Inc. 3 3 * source@mvista.com 4 4 * 5 - * Copyright 2001-2002 MontaVista Software Inc. 5 + * Copyright 2001-2006 MontaVista Software Inc. 6 6 * 7 7 * This program is free software; you can redistribute it and/or modify it 8 8 * under the terms of the GNU General Public License as published by the ··· 30 30 #include <asm/tx4927/tx4927_mips.h> 31 31 32 32 /* 33 - This register naming came from the intergrate cpu/controoler name TX4927 33 + This register naming came from the integrated CPU/controller name TX4927 34 34 followed by the device name from table 4.2.2 on page 4-3 and then followed 35 35 by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul 36 - used is "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". 36 + used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". 37 37 */ 38 38 39 39 #define TX4927_SIO_0_BASE ··· 251 251 252 252 /* TX4927 Timer 0 (32-bit registers) */ 253 253 #define TX4927_TMR0_BASE 0xf000 254 - #define TX4927_TMR0_TMTCR0 0xf004 255 - #define TX4927_TMR0_TMTISR0 0xf008 254 + #define TX4927_TMR0_TMTCR0 0xf000 255 + #define TX4927_TMR0_TMTISR0 0xf004 256 256 #define TX4927_TMR0_TMCPRA0 0xf008 257 257 #define TX4927_TMR0_TMCPRB0 0xf00c 258 258 #define TX4927_TMR0_TMITMR0 0xf010 ··· 264 264 265 265 /* TX4927 Timer 1 (32-bit registers) */ 266 266 #define TX4927_TMR1_BASE 0xf100 267 - #define TX4927_TMR1_TMTCR1 0xf104 268 - #define TX4927_TMR1_TMTISR1 0xf108 267 + #define TX4927_TMR1_TMTCR1 0xf100 268 + #define TX4927_TMR1_TMTISR1 0xf104 269 269 #define TX4927_TMR1_TMCPRA1 0xf108 270 270 #define TX4927_TMR1_TMCPRB1 0xf10c 271 271 #define TX4927_TMR1_TMITMR1 0xf110 ··· 277 277 278 278 /* TX4927 Timer 2 (32-bit registers) */ 279 279 #define TX4927_TMR2_BASE 0xf200 280 - #define TX4927_TMR2_TMTCR2 0xf104 281 - #define TX4927_TMR2_TMTISR2 0xf208 280 + #define TX4927_TMR2_TMTCR2 0xf200 281 + #define TX4927_TMR2_TMTISR2 0xf204 282 282 #define TX4927_TMR2_TMCPRA2 0xf208 283 - #define TX4927_TMR2_TMCPRB2 0xf20c 284 283 #define TX4927_TMR2_TMITMR2 0xf210 285 284 #define TX4927_TMR2_TMCCDR2 0xf220 286 - #define TX4927_TMR2_TMPGMR2 0xf230 285 + #define TX4927_TMR2_TMWTMR2 0xf240 287 286 #define TX4927_TMR2_TMTRR2 0xf2f0 288 287 #define TX4927_TMR2_LIMIT 0xf2ff 289 288