tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

x86, UV: Clean up UV headers for MMR definitions

Update UV mmr definitions header file. Eliminate definitions no
longer needed. Move 2 definitions from tlb_uv.c into the header
file where they belong.

Signed-off-by: Jack Steiner <steiner@sgi.com>
LKML-Reference: <20100310204458.GA28835@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

authored by Jack Steiner and committed by Ingo Molnar 6f4edd69 522dba71

+85 -453
unified split
+79 -449
arch/x86/include/asm/uv/uv_mmrs.h
··· 1 - 2 1 /* 3 2 * This file is subject to the terms and conditions of the GNU General Public 4 3 * License. See the file "COPYING" in the main directory of this archive ··· 14 15 #define UV_MMR_ENABLE (1UL << 63) 15 16 16 17 /* ========================================================================= */ 18 + /* UVH_BAU_DATA_BROADCAST */ 19 + /* ========================================================================= */ 20 + #define UVH_BAU_DATA_BROADCAST 0x61688UL 21 + #define UVH_BAU_DATA_BROADCAST_32 0x0440 22 + 23 + #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 24 + #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 25 + 26 + union uvh_bau_data_broadcast_u { 27 + unsigned long v; 28 + struct uvh_bau_data_broadcast_s { 29 + unsigned long enable : 1; /* RW */ 30 + unsigned long rsvd_1_63: 63; /* */ 31 + } s; 32 + }; 33 + 34 + /* ========================================================================= */ 17 35 /* UVH_BAU_DATA_CONFIG */ 18 36 /* ========================================================================= */ 19 - #define UVH_LB_BAU_MISC_CONTROL 0x320170UL 20 - #define UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT 15 21 - #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT 16 22 - #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 0x000000000bUL 23 - /* 1011 timebase 7 (168millisec) * 3 ticks -> 500ms */ 24 37 #define UVH_BAU_DATA_CONFIG 0x61680UL 25 38 #define UVH_BAU_DATA_CONFIG_32 0x0438 26 39 ··· 615 604 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70 616 605 617 606 /* ========================================================================= */ 607 + /* UVH_LB_BAU_MISC_CONTROL */ 608 + /* ========================================================================= */ 609 + #define UVH_LB_BAU_MISC_CONTROL 0x320170UL 610 + #define UVH_LB_BAU_MISC_CONTROL_32 0x00a10 611 + 612 + #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 613 + #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 614 + #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 615 + #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 616 + #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 617 + #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 618 + #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 619 + #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 620 + #define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_SHFT 11 621 + #define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 622 + #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 623 + #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 624 + #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 625 + #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 626 + #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 627 + #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 628 + #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 629 + #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 630 + #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 631 + #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 632 + #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 633 + #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 634 + #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 635 + #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 636 + #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 637 + #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 638 + #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 639 + #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 640 + #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 641 + #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 642 + #define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 643 + #define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 644 + 645 + union uvh_lb_bau_misc_control_u { 646 + unsigned long v; 647 + struct uvh_lb_bau_misc_control_s { 648 + unsigned long rejection_delay : 8; /* RW */ 649 + unsigned long apic_mode : 1; /* RW */ 650 + unsigned long force_broadcast : 1; /* RW */ 651 + unsigned long force_lock_nop : 1; /* RW */ 652 + unsigned long csi_agent_presence_vector : 3; /* RW */ 653 + unsigned long descriptor_fetch_mode : 1; /* RW */ 654 + unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 655 + unsigned long intd_soft_ack_timeout_period : 4; /* RW */ 656 + unsigned long enable_dual_mapping_mode : 1; /* RW */ 657 + unsigned long vga_io_port_decode_enable : 1; /* RW */ 658 + unsigned long vga_io_port_16_bit_decode : 1; /* RW */ 659 + unsigned long suppress_dest_registration : 1; /* RW */ 660 + unsigned long programmed_initial_priority : 3; /* RW */ 661 + unsigned long use_incoming_priority : 1; /* RW */ 662 + unsigned long enable_programmed_initial_priority : 1; /* RW */ 663 + unsigned long rsvd_29_47 : 19; /* */ 664 + unsigned long fun : 16; /* RW */ 665 + } s; 666 + }; 667 + 668 + /* ========================================================================= */ 618 669 /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 619 670 /* ========================================================================= */ 620 671 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL ··· 750 677 unsigned long rsvd_43_48 : 6; /* */ 751 678 unsigned long node_id : 14; /* RW */ 752 679 unsigned long rsvd_63 : 1; /* */ 753 - } s; 754 - }; 755 - 756 - /* ========================================================================= */ 757 - /* UVH_LB_MCAST_AOERR0_RPT_ENABLE */ 758 - /* ========================================================================= */ 759 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE 0x50b20UL 760 - 761 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_SHFT 0 762 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_MASK 0x0000000000000001UL 763 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_SHFT 1 764 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_MASK 0x0000000000000002UL 765 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_SHFT 2 766 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_MASK 0x0000000000000004UL 767 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_SHFT 3 768 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_MASK 0x0000000000000008UL 769 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_SHFT 4 770 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_MASK 0x0000000000000010UL 771 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_SHFT 5 772 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_MASK 0x0000000000000020UL 773 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_SHFT 6 774 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_MASK 0x0000000000000040UL 775 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_SHFT 7 776 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_MASK 0x0000000000000080UL 777 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_SHFT 8 778 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_MASK 0x0000000000000100UL 779 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_SHFT 9 780 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_MASK 0x0000000000000200UL 781 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_SHFT 10 782 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_MASK 0x0000000000000400UL 783 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_SHFT 11 784 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_MASK 0x0000000000000800UL 785 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_SHFT 12 786 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_MASK 0x0000000000001000UL 787 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_SHFT 13 788 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_MASK 0x0000000000002000UL 789 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_SHFT 14 790 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_MASK 0x0000000000004000UL 791 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_SHFT 15 792 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_MASK 0x0000000000008000UL 793 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_SHFT 16 794 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_MASK 0x0000000000010000UL 795 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_SHFT 17 796 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_MASK 0x0000000000020000UL 797 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_SHFT 18 798 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_MASK 0x0000000000040000UL 799 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_SHFT 19 800 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_MASK 0x0000000000080000UL 801 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_SHFT 20 802 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_MASK 0x0000000000100000UL 803 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_SHFT 21 804 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_MASK 0x0000000000200000UL 805 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_SHFT 22 806 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_MASK 0x0000000000400000UL 807 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_SHFT 23 808 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_MASK 0x0000000000800000UL 809 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 24 810 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000001000000UL 811 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 25 812 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000002000000UL 813 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 26 814 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000004000000UL 815 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 27 816 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000008000000UL 817 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 28 818 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000010000000UL 819 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 29 820 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000020000000UL 821 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 30 822 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000040000000UL 823 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 31 824 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000080000000UL 825 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 32 826 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000100000000UL 827 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 33 828 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000200000000UL 829 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 34 830 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000400000000UL 831 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 35 832 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000800000000UL 833 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 36 834 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000001000000000UL 835 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 37 836 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000002000000000UL 837 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 38 838 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000004000000000UL 839 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 39 840 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000008000000000UL 841 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 40 842 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000010000000000UL 843 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 41 844 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000020000000000UL 845 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 42 846 - #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000040000000000UL 847 - 848 - union uvh_lb_mcast_aoerr0_rpt_enable_u { 849 - unsigned long v; 850 - struct uvh_lb_mcast_aoerr0_rpt_enable_s { 851 - unsigned long mcast_obese_msg : 1; /* RW */ 852 - unsigned long mcast_data_sb_err : 1; /* RW */ 853 - unsigned long mcast_nack_buff_parity : 1; /* RW */ 854 - unsigned long mcast_timeout : 1; /* RW */ 855 - unsigned long mcast_inactive_reply : 1; /* RW */ 856 - unsigned long mcast_upgrade_error : 1; /* RW */ 857 - unsigned long mcast_reg_count_underflow : 1; /* RW */ 858 - unsigned long mcast_rep_obese_msg : 1; /* RW */ 859 - unsigned long ucache_req_runt_msg : 1; /* RW */ 860 - unsigned long ucache_req_obese_msg : 1; /* RW */ 861 - unsigned long ucache_req_data_sb_err : 1; /* RW */ 862 - unsigned long ucache_rep_runt_msg : 1; /* RW */ 863 - unsigned long ucache_rep_obese_msg : 1; /* RW */ 864 - unsigned long ucache_rep_data_sb_err : 1; /* RW */ 865 - unsigned long ucache_rep_command_err : 1; /* RW */ 866 - unsigned long ucache_pend_timeout : 1; /* RW */ 867 - unsigned long macc_req_runt_msg : 1; /* RW */ 868 - unsigned long macc_req_obese_msg : 1; /* RW */ 869 - unsigned long macc_req_data_sb_err : 1; /* RW */ 870 - unsigned long macc_rep_runt_msg : 1; /* RW */ 871 - unsigned long macc_rep_obese_msg : 1; /* RW */ 872 - unsigned long macc_rep_data_sb_err : 1; /* RW */ 873 - unsigned long macc_amo_timeout : 1; /* RW */ 874 - unsigned long macc_put_timeout : 1; /* RW */ 875 - unsigned long macc_spurious_event : 1; /* RW */ 876 - unsigned long ioh_destination_table_parity : 1; /* RW */ 877 - unsigned long get_had_error_reply : 1; /* RW */ 878 - unsigned long get_timeout : 1; /* RW */ 879 - unsigned long lock_manager_had_error_reply : 1; /* RW */ 880 - unsigned long put_had_error_reply : 1; /* RW */ 881 - unsigned long put_timeout : 1; /* RW */ 882 - unsigned long sb_activation_overrun : 1; /* RW */ 883 - unsigned long completed_gb_activation_had_error_reply : 1; /* RW */ 884 - unsigned long completed_gb_activation_timeout : 1; /* RW */ 885 - unsigned long descriptor_buffer_0_parity : 1; /* RW */ 886 - unsigned long descriptor_buffer_1_parity : 1; /* RW */ 887 - unsigned long socket_destination_table_parity : 1; /* RW */ 888 - unsigned long bau_reply_payload_corruption : 1; /* RW */ 889 - unsigned long io_port_destination_table_parity : 1; /* RW */ 890 - unsigned long intd_soft_ack_timeout : 1; /* RW */ 891 - unsigned long int_rep_obese_msg : 1; /* RW */ 892 - unsigned long int_rep_command_err : 1; /* RW */ 893 - unsigned long int_timeout : 1; /* RW */ 894 - unsigned long rsvd_43_63 : 21; /* */ 895 - } s; 896 - }; 897 - 898 - /* ========================================================================= */ 899 - /* UVH_LOCAL_INT0_CONFIG */ 900 - /* ========================================================================= */ 901 - #define UVH_LOCAL_INT0_CONFIG 0x61000UL 902 - 903 - #define UVH_LOCAL_INT0_CONFIG_VECTOR_SHFT 0 904 - #define UVH_LOCAL_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 905 - #define UVH_LOCAL_INT0_CONFIG_DM_SHFT 8 906 - #define UVH_LOCAL_INT0_CONFIG_DM_MASK 0x0000000000000700UL 907 - #define UVH_LOCAL_INT0_CONFIG_DESTMODE_SHFT 11 908 - #define UVH_LOCAL_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 909 - #define UVH_LOCAL_INT0_CONFIG_STATUS_SHFT 12 910 - #define UVH_LOCAL_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 911 - #define UVH_LOCAL_INT0_CONFIG_P_SHFT 13 912 - #define UVH_LOCAL_INT0_CONFIG_P_MASK 0x0000000000002000UL 913 - #define UVH_LOCAL_INT0_CONFIG_T_SHFT 15 914 - #define UVH_LOCAL_INT0_CONFIG_T_MASK 0x0000000000008000UL 915 - #define UVH_LOCAL_INT0_CONFIG_M_SHFT 16 916 - #define UVH_LOCAL_INT0_CONFIG_M_MASK 0x0000000000010000UL 917 - #define UVH_LOCAL_INT0_CONFIG_APIC_ID_SHFT 32 918 - #define UVH_LOCAL_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 919 - 920 - union uvh_local_int0_config_u { 921 - unsigned long v; 922 - struct uvh_local_int0_config_s { 923 - unsigned long vector_ : 8; /* RW */ 924 - unsigned long dm : 3; /* RW */ 925 - unsigned long destmode : 1; /* RW */ 926 - unsigned long status : 1; /* RO */ 927 - unsigned long p : 1; /* RO */ 928 - unsigned long rsvd_14 : 1; /* */ 929 - unsigned long t : 1; /* RO */ 930 - unsigned long m : 1; /* RW */ 931 - unsigned long rsvd_17_31: 15; /* */ 932 - unsigned long apic_id : 32; /* RW */ 933 - } s; 934 - }; 935 - 936 - /* ========================================================================= */ 937 - /* UVH_LOCAL_INT0_ENABLE */ 938 - /* ========================================================================= */ 939 - #define UVH_LOCAL_INT0_ENABLE 0x65000UL 940 - 941 - #define UVH_LOCAL_INT0_ENABLE_LB_HCERR_SHFT 0 942 - #define UVH_LOCAL_INT0_ENABLE_LB_HCERR_MASK 0x0000000000000001UL 943 - #define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_SHFT 1 944 - #define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_MASK 0x0000000000000002UL 945 - #define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_SHFT 2 946 - #define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_MASK 0x0000000000000004UL 947 - #define UVH_LOCAL_INT0_ENABLE_LH_HCERR_SHFT 3 948 - #define UVH_LOCAL_INT0_ENABLE_LH_HCERR_MASK 0x0000000000000008UL 949 - #define UVH_LOCAL_INT0_ENABLE_RH_HCERR_SHFT 4 950 - #define UVH_LOCAL_INT0_ENABLE_RH_HCERR_MASK 0x0000000000000010UL 951 - #define UVH_LOCAL_INT0_ENABLE_XN_HCERR_SHFT 5 952 - #define UVH_LOCAL_INT0_ENABLE_XN_HCERR_MASK 0x0000000000000020UL 953 - #define UVH_LOCAL_INT0_ENABLE_SI_HCERR_SHFT 6 954 - #define UVH_LOCAL_INT0_ENABLE_SI_HCERR_MASK 0x0000000000000040UL 955 - #define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_SHFT 7 956 - #define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_MASK 0x0000000000000080UL 957 - #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_SHFT 8 958 - #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_MASK 0x0000000000000100UL 959 - #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_SHFT 9 960 - #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_MASK 0x0000000000000200UL 961 - #define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_SHFT 10 962 - #define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_MASK 0x0000000000000400UL 963 - #define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_SHFT 11 964 - #define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_MASK 0x0000000000000800UL 965 - #define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_SHFT 12 966 - #define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_MASK 0x0000000000001000UL 967 - #define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_SHFT 13 968 - #define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_MASK 0x0000000000002000UL 969 - #define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_SHFT 14 970 - #define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_MASK 0x0000000000004000UL 971 - #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_SHFT 15 972 - #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_MASK 0x0000000000008000UL 973 - #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_SHFT 16 974 - #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_MASK 0x0000000000010000UL 975 - #define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_SHFT 17 976 - #define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_MASK 0x0000000000020000UL 977 - #define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_SHFT 18 978 - #define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_MASK 0x0000000000040000UL 979 - #define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_SHFT 19 980 - #define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_MASK 0x0000000000080000UL 981 - #define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_SHFT 20 982 - #define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_MASK 0x0000000000100000UL 983 - #define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_SHFT 21 984 - #define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_MASK 0x0000000000200000UL 985 - #define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 22 986 - #define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL 987 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_SHFT 23 988 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_MASK 0x0000000000800000UL 989 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_SHFT 24 990 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_MASK 0x0000000001000000UL 991 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_SHFT 25 992 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_MASK 0x0000000002000000UL 993 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_SHFT 26 994 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_MASK 0x0000000004000000UL 995 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_SHFT 27 996 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_MASK 0x0000000008000000UL 997 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_SHFT 28 998 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_MASK 0x0000000010000000UL 999 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_SHFT 29 1000 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_MASK 0x0000000020000000UL 1001 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_SHFT 30 1002 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_MASK 0x0000000040000000UL 1003 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_SHFT 31 1004 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_MASK 0x0000000080000000UL 1005 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_SHFT 32 1006 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_MASK 0x0000000100000000UL 1007 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_SHFT 33 1008 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_MASK 0x0000000200000000UL 1009 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_SHFT 34 1010 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_MASK 0x0000000400000000UL 1011 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_SHFT 35 1012 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_MASK 0x0000000800000000UL 1013 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_SHFT 36 1014 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_MASK 0x0000001000000000UL 1015 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_SHFT 37 1016 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_MASK 0x0000002000000000UL 1017 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_SHFT 38 1018 - #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_MASK 0x0000004000000000UL 1019 - #define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 39 1020 - #define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000008000000000UL 1021 - #define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 40 1022 - #define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000010000000000UL 1023 - #define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_SHFT 41 1024 - #define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_MASK 0x0000020000000000UL 1025 - #define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_SHFT 42 1026 - #define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_MASK 0x0000040000000000UL 1027 - #define UVH_LOCAL_INT0_ENABLE_LTC_INT_SHFT 43 1028 - #define UVH_LOCAL_INT0_ENABLE_LTC_INT_MASK 0x0000080000000000UL 1029 - #define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_SHFT 44 1030 - #define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL 1031 - 1032 - union uvh_local_int0_enable_u { 1033 - unsigned long v; 1034 - struct uvh_local_int0_enable_s { 1035 - unsigned long lb_hcerr : 1; /* RW */ 1036 - unsigned long gr0_hcerr : 1; /* RW */ 1037 - unsigned long gr1_hcerr : 1; /* RW */ 1038 - unsigned long lh_hcerr : 1; /* RW */ 1039 - unsigned long rh_hcerr : 1; /* RW */ 1040 - unsigned long xn_hcerr : 1; /* RW */ 1041 - unsigned long si_hcerr : 1; /* RW */ 1042 - unsigned long lb_aoerr0 : 1; /* RW */ 1043 - unsigned long gr0_aoerr0 : 1; /* RW */ 1044 - unsigned long gr1_aoerr0 : 1; /* RW */ 1045 - unsigned long lh_aoerr0 : 1; /* RW */ 1046 - unsigned long rh_aoerr0 : 1; /* RW */ 1047 - unsigned long xn_aoerr0 : 1; /* RW */ 1048 - unsigned long si_aoerr0 : 1; /* RW */ 1049 - unsigned long lb_aoerr1 : 1; /* RW */ 1050 - unsigned long gr0_aoerr1 : 1; /* RW */ 1051 - unsigned long gr1_aoerr1 : 1; /* RW */ 1052 - unsigned long lh_aoerr1 : 1; /* RW */ 1053 - unsigned long rh_aoerr1 : 1; /* RW */ 1054 - unsigned long xn_aoerr1 : 1; /* RW */ 1055 - unsigned long si_aoerr1 : 1; /* RW */ 1056 - unsigned long rh_vpi_int : 1; /* RW */ 1057 - unsigned long system_shutdown_int : 1; /* RW */ 1058 - unsigned long lb_irq_int_0 : 1; /* RW */ 1059 - unsigned long lb_irq_int_1 : 1; /* RW */ 1060 - unsigned long lb_irq_int_2 : 1; /* RW */ 1061 - unsigned long lb_irq_int_3 : 1; /* RW */ 1062 - unsigned long lb_irq_int_4 : 1; /* RW */ 1063 - unsigned long lb_irq_int_5 : 1; /* RW */ 1064 - unsigned long lb_irq_int_6 : 1; /* RW */ 1065 - unsigned long lb_irq_int_7 : 1; /* RW */ 1066 - unsigned long lb_irq_int_8 : 1; /* RW */ 1067 - unsigned long lb_irq_int_9 : 1; /* RW */ 1068 - unsigned long lb_irq_int_10 : 1; /* RW */ 1069 - unsigned long lb_irq_int_11 : 1; /* RW */ 1070 - unsigned long lb_irq_int_12 : 1; /* RW */ 1071 - unsigned long lb_irq_int_13 : 1; /* RW */ 1072 - unsigned long lb_irq_int_14 : 1; /* RW */ 1073 - unsigned long lb_irq_int_15 : 1; /* RW */ 1074 - unsigned long l1_nmi_int : 1; /* RW */ 1075 - unsigned long stop_clock : 1; /* RW */ 1076 - unsigned long asic_to_l1 : 1; /* RW */ 1077 - unsigned long l1_to_asic : 1; /* RW */ 1078 - unsigned long ltc_int : 1; /* RW */ 1079 - unsigned long la_seq_trigger : 1; /* RW */ 1080 - unsigned long rsvd_45_63 : 19; /* */ 1081 680 } s; 1082 681 }; 1083 682 ··· 853 1108 unsigned long rsvd_0_23 : 24; /* */ 854 1109 unsigned long dest_base : 22; /* RW */ 855 1110 unsigned long rsvd_46_63: 18; /* */ 856 - } s; 857 - }; 858 - 859 - /* ========================================================================= */ 860 - /* UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR */ 861 - /* ========================================================================= */ 862 - #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR 0x1600020UL 863 - 864 - #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT 26 865 - #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 866 - #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 867 - #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 868 - 869 - union uvh_rh_gam_cfg_overlay_config_mmr_u { 870 - unsigned long v; 871 - struct uvh_rh_gam_cfg_overlay_config_mmr_s { 872 - unsigned long rsvd_0_25: 26; /* */ 873 - unsigned long base : 20; /* RW */ 874 - unsigned long rsvd_46_62: 17; /* */ 875 - unsigned long enable : 1; /* RW */ 876 1111 } s; 877 1112 }; 878 1113 ··· 984 1259 unsigned long m : 1; /* RW */ 985 1260 unsigned long rsvd_17_31: 15; /* */ 986 1261 unsigned long apic_id : 32; /* RW */ 987 - } s; 988 - }; 989 - 990 - /* ========================================================================= */ 991 - /* UVH_RTC2_INT_CONFIG */ 992 - /* ========================================================================= */ 993 - #define UVH_RTC2_INT_CONFIG 0x61600UL 994 - 995 - #define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0 996 - #define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL 997 - #define UVH_RTC2_INT_CONFIG_DM_SHFT 8 998 - #define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL 999 - #define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11 1000 - #define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL 1001 - #define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12 1002 - #define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL 1003 - #define UVH_RTC2_INT_CONFIG_P_SHFT 13 1004 - #define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL 1005 - #define UVH_RTC2_INT_CONFIG_T_SHFT 15 1006 - #define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL 1007 - #define UVH_RTC2_INT_CONFIG_M_SHFT 16 1008 - #define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL 1009 - #define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32 1010 - #define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1011 - 1012 - union uvh_rtc2_int_config_u { 1013 - unsigned long v; 1014 - struct uvh_rtc2_int_config_s { 1015 - unsigned long vector_ : 8; /* RW */ 1016 - unsigned long dm : 3; /* RW */ 1017 - unsigned long destmode : 1; /* RW */ 1018 - unsigned long status : 1; /* RO */ 1019 - unsigned long p : 1; /* RO */ 1020 - unsigned long rsvd_14 : 1; /* */ 1021 - unsigned long t : 1; /* RO */ 1022 - unsigned long m : 1; /* RW */ 1023 - unsigned long rsvd_17_31: 15; /* */ 1024 - unsigned long apic_id : 32; /* RW */ 1025 - } s; 1026 - }; 1027 - 1028 - /* ========================================================================= */ 1029 - /* UVH_RTC3_INT_CONFIG */ 1030 - /* ========================================================================= */ 1031 - #define UVH_RTC3_INT_CONFIG 0x61640UL 1032 - 1033 - #define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0 1034 - #define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL 1035 - #define UVH_RTC3_INT_CONFIG_DM_SHFT 8 1036 - #define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL 1037 - #define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11 1038 - #define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL 1039 - #define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12 1040 - #define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL 1041 - #define UVH_RTC3_INT_CONFIG_P_SHFT 13 1042 - #define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL 1043 - #define UVH_RTC3_INT_CONFIG_T_SHFT 15 1044 - #define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL 1045 - #define UVH_RTC3_INT_CONFIG_M_SHFT 16 1046 - #define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL 1047 - #define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32 1048 - #define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1049 - 1050 - union uvh_rtc3_int_config_u { 1051 - unsigned long v; 1052 - struct uvh_rtc3_int_config_s { 1053 - unsigned long vector_ : 8; /* RW */ 1054 - unsigned long dm : 3; /* RW */ 1055 - unsigned long destmode : 1; /* RW */ 1056 - unsigned long status : 1; /* RO */ 1057 - unsigned long p : 1; /* RO */ 1058 - unsigned long rsvd_14 : 1; /* */ 1059 - unsigned long t : 1; /* RO */ 1060 - unsigned long m : 1; /* RW */ 1061 - unsigned long rsvd_17_31: 15; /* */ 1062 - unsigned long apic_id : 32; /* RW */ 1063 - } s; 1064 - }; 1065 - 1066 - /* ========================================================================= */ 1067 - /* UVH_RTC_INC_RATIO */ 1068 - /* ========================================================================= */ 1069 - #define UVH_RTC_INC_RATIO 0x350000UL 1070 - 1071 - #define UVH_RTC_INC_RATIO_FRACTION_SHFT 0 1072 - #define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL 1073 - #define UVH_RTC_INC_RATIO_RATIO_SHFT 20 1074 - #define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL 1075 - 1076 - union uvh_rtc_inc_ratio_u { 1077 - unsigned long v; 1078 - struct uvh_rtc_inc_ratio_s { 1079 - unsigned long fraction : 20; /* RW */ 1080 - unsigned long ratio : 3; /* RW */ 1081 - unsigned long rsvd_23_63: 41; /* */ 1082 1262 } s; 1083 1263 }; 1084 1264
+6 -4
arch/x86/kernel/tlb_uv.c
··· 20 20 #include <asm/tsc.h> 21 21 #include <asm/irq_vectors.h> 22 22 23 + #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 0x000000000bUL 24 + 23 25 static struct bau_control **uv_bau_table_bases __read_mostly; 24 26 static int uv_bau_retry_limit __read_mostly; 25 27 ··· 480 478 * To program the period, the SOFT_ACK_MODE must be off. 481 479 */ 482 480 mmr_image &= ~((unsigned long)1 << 483 - UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT); 481 + UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT); 484 482 uv_write_global_mmr64 485 483 (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); 486 484 /* 487 485 * Set the 4-bit period. 488 486 */ 489 487 mmr_image &= ~((unsigned long)0xf << 490 - UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT); 488 + UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT); 491 489 mmr_image |= (UV_INTD_SOFT_ACK_TIMEOUT_PERIOD << 492 - UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT); 490 + UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT); 493 491 uv_write_global_mmr64 494 492 (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); 495 493 /* ··· 498 496 * indicated in bits 2:0 (7 causes all of them to timeout). 499 497 */ 500 498 mmr_image |= ((unsigned long)1 << 501 - UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT); 499 + UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT); 502 500 uv_write_global_mmr64 503 501 (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); 504 502 }