tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux into arm/drivers
Reset controller changes for v5.1
This adds the include/linux/reset directory to MAINTAINERS for reset
specific headers and adds headers for sunxi and socfpga in there to
get rid of a few extern function declarations.
There is a new reset driver for the Broadcom STB reset controller and
the i.MX7 system reset controller driver is extended to support i.MX8MQ
as well. Finally, there is a new header with reset id constants for
the Meson G12A SoC, which has a reset controller identical to Meson AXG
and thus can reuse its driver and DT bindings.
* tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux:
dt-bindings: reset: meson: add g12a bindings
reset: imx7: Add support for i.MX8MQ IP block variant
reset: imx7: Add plubming to support multiple IP variants
reset: Add Broadcom STB SW_INIT reset controller driver
dt-bindings: reset: Add document for Broadcom STB reset controller
reset: socfpga: declare socfpga_reset_init in a header file
reset: sunxi: declare sun6i_reset_init in a header file
MAINTAINERS: use include/linux/reset for reset controller related headers
dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+550
-22
+27
Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt
+27
Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt
···
1
+
Broadcom STB SW_INIT-style reset controller
2
+
===========================================
3
+
4
+
Broadcom STB SoCs have a SW_INIT-style reset controller with separate
5
+
SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit
6
+
reset lines.
7
+
8
+
Please also refer to reset.txt in this directory for common reset
9
+
controller binding usage.
10
+
11
+
Required properties:
12
+
- compatible: should be brcm,brcmstb-reset
13
+
- reg: register base and length
14
+
- #reset-cells: must be set to 1
15
+
16
+
Example:
17
+
18
+
reset: reset-controller@8404318 {
19
+
compatible = "brcm,brcmstb-reset";
20
+
reg = <0x8404318 0x30>;
21
+
#reset-cells = <1>;
22
+
};
23
+
24
+
ðernet_switch {
25
+
resets = <&reset>;
26
+
reset-names = "switch";
27
+
};
+5
-2
Documentation/devicetree/bindings/reset/fsl,imx7-src.txt
+5
-2
Documentation/devicetree/bindings/reset/fsl,imx7-src.txt
···
5
5
controller binding usage.
6
6
7
7
Required properties:
8
-
- compatible: Should be "fsl,imx7d-src", "syscon"
8
+
- compatible:
9
+
- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"
10
+
- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
9
11
- reg: should be register base and length as documented in the
10
12
datasheet
11
13
- interrupts: Should contain SRC interrupt
···
46
44
47
45
48
46
For list of all valid reset indicies see
49
-
<dt-bindings/reset/imx7-reset.h>
47
+
<dt-bindings/reset/imx7-reset.h> for i.MX7 and
48
+
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ
+1
MAINTAINERS
+1
MAINTAINERS
+1
-2
arch/arm/mach-socfpga/socfpga.c
+1
-2
arch/arm/mach-socfpga/socfpga.c
···
19
19
#include <linux/of_irq.h>
20
20
#include <linux/of_platform.h>
21
21
#include <linux/reboot.h>
22
+
#include <linux/reset/socfpga.h>
22
23
23
24
#include <asm/hardware/cache-l2x0.h>
24
25
#include <asm/mach/arch.h>
···
32
31
void __iomem *rst_manager_base_addr;
33
32
void __iomem *sdr_ctl_base_addr;
34
33
unsigned long socfpga_cpu1start_addr;
35
-
36
-
extern void __init socfpga_reset_init(void);
37
34
38
35
static void __init socfpga_sysmgr_init(void)
39
36
{
+1
-1
arch/arm/mach-sunxi/sunxi.c
+1
-1
arch/arm/mach-sunxi/sunxi.c
···
14
14
#include <linux/clocksource.h>
15
15
#include <linux/init.h>
16
16
#include <linux/platform_device.h>
17
+
#include <linux/reset/sunxi.h>
17
18
18
19
#include <asm/mach/arch.h>
19
20
#include <asm/secure_cntvoff.h>
···
38
37
NULL,
39
38
};
40
39
41
-
extern void __init sun6i_reset_init(void);
42
40
static void __init sun6i_timer_init(void)
43
41
{
44
42
of_clk_init(NULL);
+10
-2
drivers/reset/Kconfig
+10
-2
drivers/reset/Kconfig
···
40
40
help
41
41
This enables the reset controller driver for Marvell Berlin SoCs.
42
42
43
+
config RESET_BRCMSTB
44
+
tristate "Broadcom STB reset controller"
45
+
depends on ARCH_BRCMSTB || COMPILE_TEST
46
+
default ARCH_BRCMSTB
47
+
help
48
+
This enables the reset controller driver for Broadcom STB SoCs using
49
+
a SUN_TOP_CTRL_SW_INIT style controller.
50
+
43
51
config RESET_HSDK
44
52
bool "Synopsys HSDK Reset Driver"
45
53
depends on HAS_IOMEM
···
56
48
This enables the reset controller driver for HSDK board.
57
49
58
50
config RESET_IMX7
59
-
bool "i.MX7 Reset Driver" if COMPILE_TEST
51
+
bool "i.MX7/8 Reset Driver" if COMPILE_TEST
60
52
depends on HAS_IOMEM
61
-
default SOC_IMX7D
53
+
default SOC_IMX7D || (ARM64 && ARCH_MXC)
62
54
select MFD_SYSCON
63
55
help
64
56
This enables the reset controller driver for i.MX7 SoCs.
+1
drivers/reset/Makefile
+1
drivers/reset/Makefile
···
7
7
obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8
8
obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
9
9
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
10
+
obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
10
11
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
11
12
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
12
13
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
+132
drivers/reset/reset-brcmstb.c
+132
drivers/reset/reset-brcmstb.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Broadcom STB generic reset controller for SW_INIT style reset controller
4
+
*
5
+
* Author: Florian Fainelli <f.fainelli@gmail.com>
6
+
* Copyright (C) 2018 Broadcom
7
+
*/
8
+
#include <linux/delay.h>
9
+
#include <linux/device.h>
10
+
#include <linux/io.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/platform_device.h>
14
+
#include <linux/reset-controller.h>
15
+
#include <linux/types.h>
16
+
17
+
struct brcmstb_reset {
18
+
void __iomem *base;
19
+
struct reset_controller_dev rcdev;
20
+
};
21
+
22
+
#define SW_INIT_SET 0x00
23
+
#define SW_INIT_CLEAR 0x04
24
+
#define SW_INIT_STATUS 0x08
25
+
26
+
#define SW_INIT_BIT(id) BIT((id) & 0x1f)
27
+
#define SW_INIT_BANK(id) ((id) >> 5)
28
+
29
+
/* A full bank contains extra registers that we are not utilizing but still
30
+
* qualify as a single bank.
31
+
*/
32
+
#define SW_INIT_BANK_SIZE 0x18
33
+
34
+
static inline
35
+
struct brcmstb_reset *to_brcmstb(struct reset_controller_dev *rcdev)
36
+
{
37
+
return container_of(rcdev, struct brcmstb_reset, rcdev);
38
+
}
39
+
40
+
static int brcmstb_reset_assert(struct reset_controller_dev *rcdev,
41
+
unsigned long id)
42
+
{
43
+
unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
44
+
struct brcmstb_reset *priv = to_brcmstb(rcdev);
45
+
46
+
writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET);
47
+
48
+
return 0;
49
+
}
50
+
51
+
static int brcmstb_reset_deassert(struct reset_controller_dev *rcdev,
52
+
unsigned long id)
53
+
{
54
+
unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
55
+
struct brcmstb_reset *priv = to_brcmstb(rcdev);
56
+
57
+
writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR);
58
+
/* Maximum reset delay after de-asserting a line and seeing block
59
+
* operation is typically 14us for the worst case, build some slack
60
+
* here.
61
+
*/
62
+
usleep_range(100, 200);
63
+
64
+
return 0;
65
+
}
66
+
67
+
static int brcmstb_reset_status(struct reset_controller_dev *rcdev,
68
+
unsigned long id)
69
+
{
70
+
unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
71
+
struct brcmstb_reset *priv = to_brcmstb(rcdev);
72
+
73
+
return readl_relaxed(priv->base + off + SW_INIT_STATUS) &
74
+
SW_INIT_BIT(id);
75
+
}
76
+
77
+
static const struct reset_control_ops brcmstb_reset_ops = {
78
+
.assert = brcmstb_reset_assert,
79
+
.deassert = brcmstb_reset_deassert,
80
+
.status = brcmstb_reset_status,
81
+
};
82
+
83
+
static int brcmstb_reset_probe(struct platform_device *pdev)
84
+
{
85
+
struct device *kdev = &pdev->dev;
86
+
struct brcmstb_reset *priv;
87
+
struct resource *res;
88
+
89
+
priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
90
+
if (!priv)
91
+
return -ENOMEM;
92
+
93
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
94
+
if (!IS_ALIGNED(res->start, SW_INIT_BANK_SIZE) ||
95
+
!IS_ALIGNED(resource_size(res), SW_INIT_BANK_SIZE)) {
96
+
dev_err(kdev, "incorrect register range\n");
97
+
return -EINVAL;
98
+
}
99
+
100
+
priv->base = devm_ioremap_resource(kdev, res);
101
+
if (IS_ERR(priv->base))
102
+
return PTR_ERR(priv->base);
103
+
104
+
dev_set_drvdata(kdev, priv);
105
+
106
+
priv->rcdev.owner = THIS_MODULE;
107
+
priv->rcdev.nr_resets = DIV_ROUND_DOWN_ULL(resource_size(res),
108
+
SW_INIT_BANK_SIZE) * 32;
109
+
priv->rcdev.ops = &brcmstb_reset_ops;
110
+
priv->rcdev.of_node = kdev->of_node;
111
+
/* Use defaults: 1 cell and simple xlate function */
112
+
113
+
return devm_reset_controller_register(kdev, &priv->rcdev);
114
+
}
115
+
116
+
static const struct of_device_id brcmstb_reset_of_match[] = {
117
+
{ .compatible = "brcm,brcmstb-reset" },
118
+
{ /* sentinel */ }
119
+
};
120
+
121
+
static struct platform_driver brcmstb_reset_driver = {
122
+
.probe = brcmstb_reset_probe,
123
+
.driver = {
124
+
.name = "brcmstb-reset",
125
+
.of_match_table = brcmstb_reset_of_match,
126
+
},
127
+
};
128
+
module_platform_driver(brcmstb_reset_driver);
129
+
130
+
MODULE_AUTHOR("Broadcom");
131
+
MODULE_DESCRIPTION("Broadcom STB reset controller");
132
+
MODULE_LICENSE("GPL");
+158
-14
drivers/reset/reset-imx7.c
+158
-14
drivers/reset/reset-imx7.c
···
17
17
18
18
#include <linux/mfd/syscon.h>
19
19
#include <linux/mod_devicetable.h>
20
+
#include <linux/of_device.h>
20
21
#include <linux/platform_device.h>
21
22
#include <linux/reset-controller.h>
22
23
#include <linux/regmap.h>
23
24
#include <dt-bindings/reset/imx7-reset.h>
25
+
#include <dt-bindings/reset/imx8mq-reset.h>
26
+
27
+
struct imx7_src_signal {
28
+
unsigned int offset, bit;
29
+
};
30
+
31
+
struct imx7_src_variant {
32
+
const struct imx7_src_signal *signals;
33
+
unsigned int signals_num;
34
+
struct reset_control_ops ops;
35
+
};
24
36
25
37
struct imx7_src {
26
38
struct reset_controller_dev rcdev;
27
39
struct regmap *regmap;
40
+
const struct imx7_src_signal *signals;
28
41
};
29
42
30
43
enum imx7_src_registers {
···
52
39
SRC_DDRC_RCR = 0x1000,
53
40
};
54
41
55
-
struct imx7_src_signal {
56
-
unsigned int offset, bit;
57
-
};
42
+
static int imx7_reset_update(struct imx7_src *imx7src,
43
+
unsigned long id, unsigned int value)
44
+
{
45
+
const struct imx7_src_signal *signal = &imx7src->signals[id];
46
+
47
+
return regmap_update_bits(imx7src->regmap,
48
+
signal->offset, signal->bit, value);
49
+
}
58
50
59
51
static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
60
52
[IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
···
99
81
unsigned long id, bool assert)
100
82
{
101
83
struct imx7_src *imx7src = to_imx7_src(rcdev);
102
-
const struct imx7_src_signal *signal = &imx7_src_signals[id];
103
-
unsigned int value = assert ? signal->bit : 0;
84
+
const unsigned int bit = imx7src->signals[id].bit;
85
+
unsigned int value = assert ? bit : 0;
104
86
105
87
switch (id) {
106
88
case IMX7_RESET_PCIEPHY:
···
113
95
break;
114
96
115
97
case IMX7_RESET_PCIE_CTRL_APPS_EN:
116
-
value = (assert) ? 0 : signal->bit;
98
+
value = assert ? 0 : bit;
117
99
break;
118
100
}
119
101
120
-
return regmap_update_bits(imx7src->regmap,
121
-
signal->offset, signal->bit, value);
102
+
return imx7_reset_update(imx7src, id, value);
122
103
}
123
104
124
105
static int imx7_reset_assert(struct reset_controller_dev *rcdev,
···
132
115
return imx7_reset_set(rcdev, id, false);
133
116
}
134
117
135
-
static const struct reset_control_ops imx7_reset_ops = {
136
-
.assert = imx7_reset_assert,
137
-
.deassert = imx7_reset_deassert,
118
+
static const struct imx7_src_variant variant_imx7 = {
119
+
.signals = imx7_src_signals,
120
+
.signals_num = ARRAY_SIZE(imx7_src_signals),
121
+
.ops = {
122
+
.assert = imx7_reset_assert,
123
+
.deassert = imx7_reset_deassert,
124
+
},
125
+
};
126
+
127
+
enum imx8mq_src_registers {
128
+
SRC_A53RCR0 = 0x0004,
129
+
SRC_HDMI_RCR = 0x0030,
130
+
SRC_DISP_RCR = 0x0034,
131
+
SRC_GPU_RCR = 0x0040,
132
+
SRC_VPU_RCR = 0x0044,
133
+
SRC_PCIE2_RCR = 0x0048,
134
+
SRC_MIPIPHY1_RCR = 0x004c,
135
+
SRC_MIPIPHY2_RCR = 0x0050,
136
+
SRC_DDRC2_RCR = 0x1004,
137
+
};
138
+
139
+
static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
140
+
[IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
141
+
[IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
142
+
[IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
143
+
[IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
144
+
[IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
145
+
[IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
146
+
[IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
147
+
[IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
148
+
[IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
149
+
[IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
150
+
[IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
151
+
[IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
152
+
[IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
153
+
[IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
154
+
[IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
155
+
[IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
156
+
[IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
157
+
[IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
158
+
[IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
159
+
[IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
160
+
[IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
161
+
[IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
162
+
[IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
163
+
[IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
164
+
[IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
165
+
[IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
166
+
[IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
167
+
BIT(2) | BIT(1) },
168
+
[IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
169
+
[IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
170
+
[IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
171
+
[IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
172
+
[IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) },
173
+
[IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
174
+
[IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
175
+
[IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR,
176
+
BIT(2) | BIT(1) },
177
+
[IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) },
178
+
[IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) },
179
+
[IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) },
180
+
[IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
181
+
[IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) },
182
+
[IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) },
183
+
[IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
184
+
[IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) },
185
+
[IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) },
186
+
[IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) },
187
+
[IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) },
188
+
[IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) },
189
+
[IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) },
190
+
[IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) },
191
+
[IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
192
+
};
193
+
194
+
static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
195
+
unsigned long id, bool assert)
196
+
{
197
+
struct imx7_src *imx7src = to_imx7_src(rcdev);
198
+
const unsigned int bit = imx7src->signals[id].bit;
199
+
unsigned int value = assert ? bit : 0;
200
+
201
+
switch (id) {
202
+
case IMX8MQ_RESET_PCIEPHY:
203
+
case IMX8MQ_RESET_PCIEPHY2: /* fallthrough */
204
+
/*
205
+
* wait for more than 10us to release phy g_rst and
206
+
* btnrst
207
+
*/
208
+
if (!assert)
209
+
udelay(10);
210
+
break;
211
+
212
+
case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
213
+
case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
214
+
case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N: /* fallthrough */
215
+
case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */
216
+
case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */
217
+
case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
218
+
case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
219
+
value = assert ? 0 : bit;
220
+
break;
221
+
}
222
+
223
+
return imx7_reset_update(imx7src, id, value);
224
+
}
225
+
226
+
static int imx8mq_reset_assert(struct reset_controller_dev *rcdev,
227
+
unsigned long id)
228
+
{
229
+
return imx8mq_reset_set(rcdev, id, true);
230
+
}
231
+
232
+
static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev,
233
+
unsigned long id)
234
+
{
235
+
return imx8mq_reset_set(rcdev, id, false);
236
+
}
237
+
238
+
static const struct imx7_src_variant variant_imx8mq = {
239
+
.signals = imx8mq_src_signals,
240
+
.signals_num = ARRAY_SIZE(imx8mq_src_signals),
241
+
.ops = {
242
+
.assert = imx8mq_reset_assert,
243
+
.deassert = imx8mq_reset_deassert,
244
+
},
138
245
};
139
246
140
247
static int imx7_reset_probe(struct platform_device *pdev)
···
266
125
struct imx7_src *imx7src;
267
126
struct device *dev = &pdev->dev;
268
127
struct regmap_config config = { .name = "src" };
128
+
const struct imx7_src_variant *variant = of_device_get_match_data(dev);
269
129
270
130
imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL);
271
131
if (!imx7src)
272
132
return -ENOMEM;
273
133
134
+
imx7src->signals = variant->signals;
274
135
imx7src->regmap = syscon_node_to_regmap(dev->of_node);
275
136
if (IS_ERR(imx7src->regmap)) {
276
137
dev_err(dev, "Unable to get imx7-src regmap");
···
281
138
regmap_attach_dev(dev, imx7src->regmap, &config);
282
139
283
140
imx7src->rcdev.owner = THIS_MODULE;
284
-
imx7src->rcdev.nr_resets = IMX7_RESET_NUM;
285
-
imx7src->rcdev.ops = &imx7_reset_ops;
141
+
imx7src->rcdev.nr_resets = variant->signals_num;
142
+
imx7src->rcdev.ops = &variant->ops;
286
143
imx7src->rcdev.of_node = dev->of_node;
287
144
288
145
return devm_reset_controller_register(dev, &imx7src->rcdev);
289
146
}
290
147
291
148
static const struct of_device_id imx7_reset_dt_ids[] = {
292
-
{ .compatible = "fsl,imx7d-src", },
149
+
{ .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
150
+
{ .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
293
151
{ /* sentinel */ },
294
152
};
295
153
+1
-1
drivers/reset/reset-socfpga.c
+1
-1
drivers/reset/reset-socfpga.c
···
11
11
#include <linux/of_address.h>
12
12
#include <linux/platform_device.h>
13
13
#include <linux/reset-controller.h>
14
+
#include <linux/reset/socfpga.h>
14
15
#include <linux/slab.h>
15
16
#include <linux/spinlock.h>
16
17
#include <linux/types.h>
···
19
18
#include "reset-simple.h"
20
19
21
20
#define SOCFPGA_NR_BANKS 8
22
-
void __init socfpga_reset_init(void);
23
21
24
22
static int a10_reset_init(struct device_node *np)
25
23
{
+1
drivers/reset/reset-sunxi.c
+1
drivers/reset/reset-sunxi.c
+134
include/dt-bindings/reset/amlogic,meson-g12a-reset.h
+134
include/dt-bindings/reset/amlogic,meson-g12a-reset.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
2
+
/*
3
+
* Copyright (c) 2019 BayLibre, SAS.
4
+
* Author: Jerome Brunet <jbrunet@baylibre.com>
5
+
*
6
+
*/
7
+
8
+
#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
9
+
#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
10
+
11
+
/* RESET0 */
12
+
#define RESET_HIU 0
13
+
/* 1 */
14
+
#define RESET_DOS 2
15
+
/* 3-4 */
16
+
#define RESET_VIU 5
17
+
#define RESET_AFIFO 6
18
+
#define RESET_VID_PLL_DIV 7
19
+
/* 8-9 */
20
+
#define RESET_VENC 10
21
+
#define RESET_ASSIST 11
22
+
#define RESET_PCIE_CTRL_A 12
23
+
#define RESET_VCBUS 13
24
+
#define RESET_PCIE_PHY 14
25
+
#define RESET_PCIE_APB 15
26
+
#define RESET_GIC 16
27
+
#define RESET_CAPB3_DECODE 17
28
+
/* 18 */
29
+
#define RESET_HDMITX_CAPB3 19
30
+
#define RESET_DVALIN_CAPB3 20
31
+
#define RESET_DOS_CAPB3 21
32
+
/* 22 */
33
+
#define RESET_CBUS_CAPB3 23
34
+
#define RESET_AHB_CNTL 24
35
+
#define RESET_AHB_DATA 25
36
+
#define RESET_VCBUS_CLK81 26
37
+
/* 27-31 */
38
+
/* RESET1 */
39
+
/* 32 */
40
+
#define RESET_DEMUX 33
41
+
#define RESET_USB 34
42
+
#define RESET_DDR 35
43
+
/* 36 */
44
+
#define RESET_BT656 37
45
+
#define RESET_AHB_SRAM 38
46
+
/* 39 */
47
+
#define RESET_PARSER 40
48
+
/* 41 */
49
+
#define RESET_ISA 42
50
+
#define RESET_ETHERNET 43
51
+
#define RESET_SD_EMMC_A 44
52
+
#define RESET_SD_EMMC_B 45
53
+
#define RESET_SD_EMMC_C 46
54
+
/* 47-60 */
55
+
#define RESET_AUDIO_CODEC 61
56
+
/* 62-63 */
57
+
/* RESET2 */
58
+
/* 64 */
59
+
#define RESET_AUDIO 65
60
+
#define RESET_HDMITX_PHY 66
61
+
/* 67 */
62
+
#define RESET_MIPI_DSI_HOST 68
63
+
#define RESET_ALOCKER 69
64
+
#define RESET_GE2D 70
65
+
#define RESET_PARSER_REG 71
66
+
#define RESET_PARSER_FETCH 72
67
+
#define RESET_CTL 73
68
+
#define RESET_PARSER_TOP 74
69
+
/* 75-77 */
70
+
#define RESET_DVALIN 78
71
+
#define RESET_HDMITX 79
72
+
/* 80-95 */
73
+
/* RESET3 */
74
+
/* 96-95 */
75
+
#define RESET_DEMUX_TOP 105
76
+
#define RESET_DEMUX_DES_PL 106
77
+
#define RESET_DEMUX_S2P_0 107
78
+
#define RESET_DEMUX_S2P_1 108
79
+
#define RESET_DEMUX_0 109
80
+
#define RESET_DEMUX_1 110
81
+
#define RESET_DEMUX_2 111
82
+
/* 112-127 */
83
+
/* RESET4 */
84
+
/* 128-129 */
85
+
#define RESET_MIPI_DSI_PHY 130
86
+
/* 131-132 */
87
+
#define RESET_RDMA 133
88
+
#define RESET_VENCI 134
89
+
#define RESET_VENCP 135
90
+
/* 136 */
91
+
#define RESET_VDAC 137
92
+
/* 138-139 */
93
+
#define RESET_VDI6 140
94
+
#define RESET_VENCL 141
95
+
#define RESET_I2C_M1 142
96
+
#define RESET_I2C_M2 143
97
+
/* 144-159 */
98
+
/* RESET5 */
99
+
/* 160-191 */
100
+
/* RESET6 */
101
+
#define RESET_GEN 192
102
+
#define RESET_SPICC0 193
103
+
#define RESET_SC 194
104
+
#define RESET_SANA_3 195
105
+
#define RESET_I2C_M0 196
106
+
#define RESET_TS_PLL 197
107
+
#define RESET_SPICC1 198
108
+
#define RESET_STREAM 199
109
+
#define RESET_TS_CPU 200
110
+
#define RESET_UART0 201
111
+
#define RESET_UART1_2 202
112
+
#define RESET_ASYNC0 203
113
+
#define RESET_ASYNC1 204
114
+
#define RESET_SPIFC0 205
115
+
#define RESET_I2C_M3 206
116
+
/* 207-223 */
117
+
/* RESET7 */
118
+
#define RESET_USB_DDR_0 224
119
+
#define RESET_USB_DDR_1 225
120
+
#define RESET_USB_DDR_2 226
121
+
#define RESET_USB_DDR_3 227
122
+
#define RESET_TS_GPU 228
123
+
#define RESET_DEVICE_MMC_ARB 229
124
+
#define RESET_DVALIN_DMC_PIPL 230
125
+
#define RESET_VID_LOCK 231
126
+
#define RESET_NIC_DMC_PIPL 232
127
+
#define RESET_DMC_VPU_PIPL 233
128
+
#define RESET_GE2D_DMC_PIPL 234
129
+
#define RESET_HCODEC_DMC_PIPL 235
130
+
#define RESET_WAVE420_DMC_PIPL 236
131
+
#define RESET_HEVCF_DMC_PIPL 237
132
+
/* 238-255 */
133
+
134
+
#endif
+64
include/dt-bindings/reset/imx8mq-reset.h
+64
include/dt-bindings/reset/imx8mq-reset.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2018 Zodiac Inflight Innovations
4
+
*
5
+
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
6
+
*/
7
+
8
+
#ifndef DT_BINDING_RESET_IMX8MQ_H
9
+
#define DT_BINDING_RESET_IMX8MQ_H
10
+
11
+
#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0
12
+
#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1
13
+
#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2
14
+
#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3
15
+
#define IMX8MQ_RESET_A53_CORE_RESET0 4
16
+
#define IMX8MQ_RESET_A53_CORE_RESET1 5
17
+
#define IMX8MQ_RESET_A53_CORE_RESET2 6
18
+
#define IMX8MQ_RESET_A53_CORE_RESET3 7
19
+
#define IMX8MQ_RESET_A53_DBG_RESET0 8
20
+
#define IMX8MQ_RESET_A53_DBG_RESET1 9
21
+
#define IMX8MQ_RESET_A53_DBG_RESET2 10
22
+
#define IMX8MQ_RESET_A53_DBG_RESET3 11
23
+
#define IMX8MQ_RESET_A53_ETM_RESET0 12
24
+
#define IMX8MQ_RESET_A53_ETM_RESET1 13
25
+
#define IMX8MQ_RESET_A53_ETM_RESET2 14
26
+
#define IMX8MQ_RESET_A53_ETM_RESET3 15
27
+
#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16
28
+
#define IMX8MQ_RESET_A53_L2RESET 17
29
+
#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
30
+
#define IMX8MQ_RESET_OTG1_PHY_RESET 19
31
+
#define IMX8MQ_RESET_OTG2_PHY_RESET 20
32
+
#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
33
+
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
34
+
#define IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N 23
35
+
#define IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N 24
36
+
#define IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N 25
37
+
#define IMX8MQ_RESET_PCIEPHY 26
38
+
#define IMX8MQ_RESET_PCIEPHY_PERST 27
39
+
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
40
+
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
41
+
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30
42
+
#define IMX8MQ_RESET_DISP_RESET 31
43
+
#define IMX8MQ_RESET_GPU_RESET 32
44
+
#define IMX8MQ_RESET_VPU_RESET 33
45
+
#define IMX8MQ_RESET_PCIEPHY2 34
46
+
#define IMX8MQ_RESET_PCIEPHY2_PERST 35
47
+
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36
48
+
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37
49
+
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38
50
+
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39
51
+
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40
52
+
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41
53
+
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42
54
+
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43
55
+
#define IMX8MQ_RESET_DDRC1_PRST 44
56
+
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
57
+
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
58
+
#define IMX8MQ_RESET_DDRC2_PRST 47
59
+
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48
60
+
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49
61
+
62
+
#define IMX8MQ_RESET_NUM 50
63
+
64
+
#endif
+7
include/linux/reset/socfpga.h
+7
include/linux/reset/socfpga.h