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kernel
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linux
clk: qcom: Remove double-space after assignment operator
This is an oddly common hiccup across clk/qcom.. Remove it in hopes to
reduce spread through copy-paste.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250802-topic-clk_qc_doublespace-v1-1-2cae59ba7d59@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Konrad Dybcio
and committed by
Bjorn Andersson
6ef38b0c
5bf83c54
+43
-43
+1
-1
drivers/clk/qcom/a7-pll.c
+1
-1
drivers/clk/qcom/a7-pll.c
+13
-13
drivers/clk/qcom/clk-alpha-pll.c
+13
-13
drivers/clk/qcom/clk-alpha-pll.c
···
66
66
#define GET_PLL_TYPE(pll) (((pll)->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS)
67
67
68
68
const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
69
-
[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
69
+
[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
70
70
[PLL_OFF_L_VAL] = 0x04,
71
71
[PLL_OFF_ALPHA_VAL] = 0x08,
72
72
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
···
77
77
[PLL_OFF_TEST_CTL_U] = 0x20,
78
78
[PLL_OFF_STATUS] = 0x24,
79
79
},
80
-
[CLK_ALPHA_PLL_TYPE_HUAYRA] = {
80
+
[CLK_ALPHA_PLL_TYPE_HUAYRA] = {
81
81
[PLL_OFF_L_VAL] = 0x04,
82
82
[PLL_OFF_ALPHA_VAL] = 0x08,
83
83
[PLL_OFF_USER_CTL] = 0x10,
···
87
87
[PLL_OFF_TEST_CTL_U] = 0x20,
88
88
[PLL_OFF_STATUS] = 0x24,
89
89
},
90
-
[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = {
90
+
[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = {
91
91
[PLL_OFF_L_VAL] = 0x08,
92
92
[PLL_OFF_ALPHA_VAL] = 0x10,
93
93
[PLL_OFF_USER_CTL] = 0x18,
···
97
97
[PLL_OFF_TEST_CTL] = 0x30,
98
98
[PLL_OFF_TEST_CTL_U] = 0x34,
99
99
},
100
-
[CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = {
100
+
[CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = {
101
101
[PLL_OFF_L_VAL] = 0x04,
102
102
[PLL_OFF_ALPHA_VAL] = 0x08,
103
103
[PLL_OFF_USER_CTL] = 0x0c,
···
110
110
[PLL_OFF_OPMODE] = 0x28,
111
111
[PLL_OFF_STATUS] = 0x38,
112
112
},
113
-
[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
113
+
[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
114
114
[PLL_OFF_L_VAL] = 0x04,
115
115
[PLL_OFF_ALPHA_VAL] = 0x08,
116
116
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
···
119
119
[PLL_OFF_TEST_CTL] = 0x1c,
120
120
[PLL_OFF_STATUS] = 0x24,
121
121
},
122
-
[CLK_ALPHA_PLL_TYPE_FABIA] = {
122
+
[CLK_ALPHA_PLL_TYPE_FABIA] = {
123
123
[PLL_OFF_L_VAL] = 0x04,
124
124
[PLL_OFF_USER_CTL] = 0x0c,
125
125
[PLL_OFF_USER_CTL_U] = 0x10,
···
147
147
[PLL_OFF_OPMODE] = 0x38,
148
148
[PLL_OFF_ALPHA_VAL] = 0x40,
149
149
},
150
-
[CLK_ALPHA_PLL_TYPE_AGERA] = {
150
+
[CLK_ALPHA_PLL_TYPE_AGERA] = {
151
151
[PLL_OFF_L_VAL] = 0x04,
152
152
[PLL_OFF_ALPHA_VAL] = 0x08,
153
153
[PLL_OFF_USER_CTL] = 0x0c,
···
157
157
[PLL_OFF_TEST_CTL_U] = 0x1c,
158
158
[PLL_OFF_STATUS] = 0x2c,
159
159
},
160
-
[CLK_ALPHA_PLL_TYPE_ZONDA] = {
160
+
[CLK_ALPHA_PLL_TYPE_ZONDA] = {
161
161
[PLL_OFF_L_VAL] = 0x04,
162
162
[PLL_OFF_ALPHA_VAL] = 0x08,
163
163
[PLL_OFF_USER_CTL] = 0x0c,
···
243
243
[PLL_OFF_TEST_CTL] = 0x28,
244
244
[PLL_OFF_TEST_CTL_U] = 0x2c,
245
245
},
246
-
[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
246
+
[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
247
247
[PLL_OFF_L_VAL] = 0x04,
248
248
[PLL_OFF_ALPHA_VAL] = 0x08,
249
249
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
···
254
254
[PLL_OFF_CONFIG_CTL] = 0x20,
255
255
[PLL_OFF_STATUS] = 0x24,
256
256
},
257
-
[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
257
+
[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
258
258
[PLL_OFF_L_VAL] = 0x04,
259
259
[PLL_OFF_ALPHA_VAL] = 0x08,
260
260
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
···
275
275
[PLL_OFF_TEST_CTL] = 0x30,
276
276
[PLL_OFF_TEST_CTL_U] = 0x34,
277
277
},
278
-
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
278
+
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
279
279
[PLL_OFF_L_VAL] = 0x04,
280
280
[PLL_OFF_USER_CTL] = 0x08,
281
281
[PLL_OFF_USER_CTL_U] = 0x0c,
···
286
286
[PLL_OFF_ALPHA_VAL] = 0x24,
287
287
[PLL_OFF_ALPHA_VAL_U] = 0x28,
288
288
},
289
-
[CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = {
289
+
[CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = {
290
290
[PLL_OFF_L_VAL] = 0x04,
291
291
[PLL_OFF_ALPHA_VAL] = 0x08,
292
292
[PLL_OFF_USER_CTL] = 0x0c,
···
301
301
[PLL_OFF_OPMODE] = 0x30,
302
302
[PLL_OFF_STATUS] = 0x3c,
303
303
},
304
-
[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
304
+
[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
305
305
[PLL_OFF_L_VAL] = 0x04,
306
306
[PLL_OFF_ALPHA_VAL] = 0x08,
307
307
[PLL_OFF_TEST_CTL] = 0x0c,
+1
-1
drivers/clk/qcom/clk-rcg.c
+1
-1
drivers/clk/qcom/clk-rcg.c
+4
-4
drivers/clk/qcom/clk-rcg2.c
+4
-4
drivers/clk/qcom/clk-rcg2.c
···
201
201
regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
202
202
m &= mask;
203
203
regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n);
204
-
n = ~n;
204
+
n = ~n;
205
205
n &= mask;
206
206
n += m;
207
207
mode = cfg & CFG_MODE_MASK;
···
274
274
rate = tmp;
275
275
}
276
276
} else {
277
-
rate = clk_hw_get_rate(p);
277
+
rate = clk_hw_get_rate(p);
278
278
}
279
279
req->best_parent_hw = p;
280
280
req->best_parent_rate = rate;
···
311
311
if (!p)
312
312
continue;
313
313
314
-
parent_rate = clk_hw_get_rate(p);
314
+
parent_rate = clk_hw_get_rate(p);
315
315
rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div);
316
316
317
317
if (rate == req_rate) {
···
382
382
rate = tmp;
383
383
}
384
384
} else {
385
-
rate = clk_hw_get_rate(p);
385
+
rate = clk_hw_get_rate(p);
386
386
}
387
387
388
388
req->best_parent_hw = p;
+3
-3
drivers/clk/qcom/clk-rpmh.c
+3
-3
drivers/clk/qcom/clk-rpmh.c
···
87
87
.hw.init = &(struct clk_init_data){ \
88
88
.ops = &clk_rpmh_ops, \
89
89
.name = #_name, \
90
-
.parent_data = &(const struct clk_parent_data){ \
90
+
.parent_data = &(const struct clk_parent_data){ \
91
91
.fw_name = "xo", \
92
92
.name = "xo_board", \
93
93
}, \
···
105
105
.hw.init = &(struct clk_init_data){ \
106
106
.ops = &clk_rpmh_ops, \
107
107
.name = #_name "_ao", \
108
-
.parent_data = &(const struct clk_parent_data){ \
108
+
.parent_data = &(const struct clk_parent_data){ \
109
109
.fw_name = "xo", \
110
110
.name = "xo_board", \
111
111
}, \
···
182
182
}
183
183
184
184
c->last_sent_aggr_state = c->aggr_state;
185
-
c->peer->last_sent_aggr_state = c->last_sent_aggr_state;
185
+
c->peer->last_sent_aggr_state = c->last_sent_aggr_state;
186
186
187
187
return 0;
188
188
}
+4
-4
drivers/clk/qcom/clk-smd-rpm.c
+4
-4
drivers/clk/qcom/clk-smd-rpm.c
···
30
30
.hw.init = &(struct clk_init_data){ \
31
31
.ops = &clk_smd_rpm_ops, \
32
32
.name = #_name, \
33
-
.parent_data = &(const struct clk_parent_data){ \
33
+
.parent_data = &(const struct clk_parent_data){ \
34
34
.fw_name = "xo", \
35
35
.name = "xo_board", \
36
36
}, \
···
47
47
.hw.init = &(struct clk_init_data){ \
48
48
.ops = &clk_smd_rpm_ops, \
49
49
.name = #_active, \
50
-
.parent_data = &(const struct clk_parent_data){ \
50
+
.parent_data = &(const struct clk_parent_data){ \
51
51
.fw_name = "xo", \
52
52
.name = "xo_board", \
53
53
}, \
···
74
74
.hw.init = &(struct clk_init_data){ \
75
75
.ops = &clk_smd_rpm_branch_ops, \
76
76
.name = #_name, \
77
-
.parent_data = &(const struct clk_parent_data){ \
77
+
.parent_data = &(const struct clk_parent_data){ \
78
78
.fw_name = "xo", \
79
79
.name = "xo_board", \
80
80
}, \
···
92
92
.hw.init = &(struct clk_init_data){ \
93
93
.ops = &clk_smd_rpm_branch_ops, \
94
94
.name = #_active, \
95
-
.parent_data = &(const struct clk_parent_data){ \
95
+
.parent_data = &(const struct clk_parent_data){ \
96
96
.fw_name = "xo", \
97
97
.name = "xo_board", \
98
98
}, \
+1
-1
drivers/clk/qcom/gcc-qcs404.c
+1
-1
drivers/clk/qcom/gcc-qcs404.c
···
2754
2754
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
2755
2755
[GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
2756
2756
[GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
2757
-
[GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr,
2757
+
[GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr,
2758
2758
2759
2759
};
2760
2760
+3
-3
drivers/clk/qcom/gpucc-sa8775p.c
+3
-3
drivers/clk/qcom/gpucc-sa8775p.c
···
365
365
&gpu_cc_gmu_clk_src.clkr.hw,
366
366
},
367
367
.num_parents = 1,
368
-
.flags = CLK_SET_RATE_PARENT,
368
+
.flags = CLK_SET_RATE_PARENT,
369
369
.ops = &clk_branch2_aon_ops,
370
370
},
371
371
},
···
414
414
&gpu_cc_xo_clk_src.clkr.hw,
415
415
},
416
416
.num_parents = 1,
417
-
.flags = CLK_SET_RATE_PARENT,
417
+
.flags = CLK_SET_RATE_PARENT,
418
418
.ops = &clk_branch2_ops,
419
419
},
420
420
},
···
499
499
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
500
500
},
501
501
.num_parents = 1,
502
-
.flags = CLK_SET_RATE_PARENT,
502
+
.flags = CLK_SET_RATE_PARENT,
503
503
.ops = &clk_branch2_aon_ops,
504
504
},
505
505
},
+1
-1
drivers/clk/qcom/gpucc-sc7180.c
+1
-1
drivers/clk/qcom/gpucc-sc7180.c
+2
-2
drivers/clk/qcom/gpucc-sm6350.c
+2
-2
drivers/clk/qcom/gpucc-sm6350.c
···
67
67
.clkr = {
68
68
.hw.init = &(struct clk_init_data){
69
69
.name = "gpu_cc_pll0",
70
-
.parent_data = &(const struct clk_parent_data){
70
+
.parent_data = &(const struct clk_parent_data){
71
71
.index = DT_BI_TCXO,
72
72
.fw_name = "bi_tcxo",
73
73
},
···
111
111
.clkr = {
112
112
.hw.init = &(struct clk_init_data){
113
113
.name = "gpu_cc_pll1",
114
-
.parent_data = &(const struct clk_parent_data){
114
+
.parent_data = &(const struct clk_parent_data){
115
115
.index = DT_BI_TCXO,
116
116
.fw_name = "bi_tcxo",
117
117
},
+1
-1
drivers/clk/qcom/gpucc-sm8150.c
+1
-1
drivers/clk/qcom/gpucc-sm8150.c
+1
-1
drivers/clk/qcom/gpucc-sm8250.c
+1
-1
drivers/clk/qcom/gpucc-sm8250.c
+2
-2
drivers/clk/qcom/lpassaudiocc-sc7280.c
+2
-2
drivers/clk/qcom/lpassaudiocc-sc7280.c
···
709
709
};
710
710
711
711
static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = {
712
-
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
713
-
[LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
712
+
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
713
+
[LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
714
714
[LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
715
715
};
716
716
+2
-2
drivers/clk/qcom/lpasscc-sc8280xp.c
+2
-2
drivers/clk/qcom/lpasscc-sc8280xp.c
···
18
18
#include "reset.h"
19
19
20
20
static const struct qcom_reset_map lpass_audiocc_sc8280xp_resets[] = {
21
-
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
21
+
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
22
22
[LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
23
-
[LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 },
23
+
[LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 },
24
24
};
25
25
26
26
static const struct regmap_config lpass_audiocc_sc8280xp_regmap_config = {
+1
-1
drivers/clk/qcom/lpasscc-sm6115.c
+1
-1
drivers/clk/qcom/lpasscc-sm6115.c
···
17
17
#include "reset.h"
18
18
19
19
static const struct qcom_reset_map lpass_audiocc_sm6115_resets[] = {
20
-
[LPASS_AUDIO_SWR_RX_CGCR] = { .reg = 0x98, .bit = 1, .udelay = 500 },
20
+
[LPASS_AUDIO_SWR_RX_CGCR] = { .reg = 0x98, .bit = 1, .udelay = 500 },
21
21
};
22
22
23
23
static struct regmap_config lpass_audiocc_sm6115_regmap_config = {
+1
-1
drivers/clk/qcom/lpasscorecc-sc7180.c
+1
-1
drivers/clk/qcom/lpasscorecc-sc7180.c
+1
-1
drivers/clk/qcom/mmcc-sdm660.c
+1
-1
drivers/clk/qcom/mmcc-sdm660.c
+1
-1
drivers/clk/qcom/nsscc-ipq9574.c
+1
-1
drivers/clk/qcom/nsscc-ipq9574.c
···
3016
3016
[NSSPORT4_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(5, 4) },
3017
3017
[NSSPORT5_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(3, 2) },
3018
3018
[NSSPORT6_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(1, 0) },
3019
-
[EDMA_HW_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(16, 15) },
3019
+
[EDMA_HW_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(16, 15) },
3020
3020
};
3021
3021
3022
3022
static const struct regmap_config nss_cc_ipq9574_regmap_config = {