tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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phy: qcom-qmp: Add SM8250 PCIe QMP PHYs

SM8250 has multiple different PHY versions:
QMP GEN3x1 PHY - 1 lane
QMP GEN3x2 PHY - 2 lanes
QMP Modem PHY - 2 lanes

Add support for these with relevant init sequence. In order to abstract
the init sequence, this commit introduces secondary tables which can
be used to factor out the unique sequence for each PHY while the former
tables can have the common sequence.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20201027170033.8475-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Manivannan Sadhasivam and committed by
Vinod Koul 6edf7700 5594b407

+295 -4
+277 -4
drivers/phy/qualcomm/phy-qcom-qmp.c
··· 217 217 [QPHY_PCS_READY_STATUS] = 0x160, 218 218 }; 219 219 220 + static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 221 + [QPHY_SW_RESET] = 0x00, 222 + [QPHY_START_CTRL] = 0x44, 223 + [QPHY_PCS_STATUS] = 0x14, 224 + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 225 + }; 226 + 220 227 static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { 221 228 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, 222 229 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, ··· 1831 1824 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1832 1825 }; 1833 1826 1827 + static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 1828 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1829 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1830 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 1831 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1832 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 1833 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 1834 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 1835 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 1836 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1837 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1838 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1839 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 1840 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 1841 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 1842 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 1843 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 1844 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 1845 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1846 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1847 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1848 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1849 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1850 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1851 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1852 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1853 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1854 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1855 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1856 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1857 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1858 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1859 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1860 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1861 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1862 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1863 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1864 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1865 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1866 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1867 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1868 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1869 + }; 1870 + 1871 + static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 1872 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1873 + }; 1874 + 1875 + static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 1876 + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1877 + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 1878 + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1879 + }; 1880 + 1881 + static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 1882 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1883 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1884 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 1885 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1886 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1887 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 1888 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 1889 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 1890 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1891 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1892 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1893 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1894 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1895 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1896 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1897 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1898 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1899 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1900 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1901 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1902 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1903 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1904 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1905 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1906 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1907 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1908 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1909 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1910 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1911 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1912 + }; 1913 + 1914 + static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 1915 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 1916 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 1917 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1918 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 1919 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 1920 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1921 + }; 1922 + 1923 + static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 1924 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1925 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1926 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1927 + }; 1928 + 1929 + static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 1930 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1931 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 1932 + }; 1933 + 1934 + static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 1935 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1936 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1937 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1938 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1939 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1940 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1941 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1942 + }; 1943 + 1944 + static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1945 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1946 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 1947 + }; 1948 + 1949 + static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 1950 + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1951 + }; 1952 + 1953 + static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 1954 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1955 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1956 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 1957 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1958 + }; 1959 + 1960 + static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 1961 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 1962 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1963 + }; 1964 + 1965 + static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1966 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1967 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1968 + }; 1969 + 1834 1970 /* struct qmp_phy_cfg - per-PHY initialization config */ 1835 1971 struct qmp_phy_cfg { 1836 1972 /* phy-type - PCIE/UFS/USB */ ··· 1984 1834 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1985 1835 const struct qmp_phy_init_tbl *serdes_tbl; 1986 1836 int serdes_tbl_num; 1837 + const struct qmp_phy_init_tbl *serdes_tbl_sec; 1838 + int serdes_tbl_num_sec; 1987 1839 const struct qmp_phy_init_tbl *tx_tbl; 1988 1840 int tx_tbl_num; 1841 + const struct qmp_phy_init_tbl *tx_tbl_sec; 1842 + int tx_tbl_num_sec; 1989 1843 const struct qmp_phy_init_tbl *rx_tbl; 1990 1844 int rx_tbl_num; 1845 + const struct qmp_phy_init_tbl *rx_tbl_sec; 1846 + int rx_tbl_num_sec; 1991 1847 const struct qmp_phy_init_tbl *pcs_tbl; 1992 1848 int pcs_tbl_num; 1849 + const struct qmp_phy_init_tbl *pcs_tbl_sec; 1850 + int pcs_tbl_num_sec; 1993 1851 const struct qmp_phy_init_tbl *pcs_misc_tbl; 1994 1852 int pcs_misc_tbl_num; 1853 + const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; 1854 + int pcs_misc_tbl_num_sec; 1995 1855 1996 1856 /* Init sequence for DP PHY block link rates */ 1997 1857 const struct qmp_phy_init_tbl *serdes_tbl_rbr; ··· 2405 2245 .pwrdn_delay_max = 1005, /* us */ 2406 2246 }; 2407 2247 2248 + static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 2249 + .type = PHY_TYPE_PCIE, 2250 + .nlanes = 1, 2251 + 2252 + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, 2253 + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 2254 + .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, 2255 + .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 2256 + .tx_tbl = sm8250_qmp_pcie_tx_tbl, 2257 + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 2258 + .rx_tbl = sm8250_qmp_pcie_rx_tbl, 2259 + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 2260 + .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, 2261 + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 2262 + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, 2263 + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 2264 + .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, 2265 + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 2266 + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, 2267 + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 2268 + .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 2269 + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 2270 + .clk_list = sdm845_pciephy_clk_l, 2271 + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2272 + .reset_list = sdm845_pciephy_reset_l, 2273 + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2274 + .vreg_list = qmp_phy_vreg_l, 2275 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2276 + .regs = sm8250_pcie_regs_layout, 2277 + 2278 + .start_ctrl = PCS_START | SERDES_START, 2279 + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2280 + 2281 + .has_pwrdn_delay = true, 2282 + .pwrdn_delay_min = 995, /* us */ 2283 + .pwrdn_delay_max = 1005, /* us */ 2284 + }; 2285 + 2286 + static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 2287 + .type = PHY_TYPE_PCIE, 2288 + .nlanes = 2, 2289 + 2290 + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, 2291 + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 2292 + .tx_tbl = sm8250_qmp_pcie_tx_tbl, 2293 + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 2294 + .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, 2295 + .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 2296 + .rx_tbl = sm8250_qmp_pcie_rx_tbl, 2297 + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 2298 + .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, 2299 + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 2300 + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, 2301 + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 2302 + .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, 2303 + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 2304 + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, 2305 + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 2306 + .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 2307 + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 2308 + .clk_list = sdm845_pciephy_clk_l, 2309 + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2310 + .reset_list = sdm845_pciephy_reset_l, 2311 + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2312 + .vreg_list = qmp_phy_vreg_l, 2313 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2314 + .regs = sm8250_pcie_regs_layout, 2315 + 2316 + .start_ctrl = PCS_START | SERDES_START, 2317 + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2318 + 2319 + .is_dual_lane_phy = true, 2320 + .has_pwrdn_delay = true, 2321 + .pwrdn_delay_min = 995, /* us */ 2322 + .pwrdn_delay_max = 1005, /* us */ 2323 + }; 2324 + 2408 2325 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { 2409 2326 .type = PHY_TYPE_USB3, 2410 2327 .nlanes = 1, ··· 2866 2629 int ret; 2867 2630 2868 2631 qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 2632 + if (cfg->serdes_tbl_sec) 2633 + qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, 2634 + cfg->serdes_tbl_num_sec); 2869 2635 2870 2636 if (cfg->type == PHY_TYPE_DP) { 2871 2637 switch (dp_opts->link_rate) { ··· 3357 3117 /* Tx, Rx, and PCS configurations */ 3358 3118 qcom_qmp_phy_configure_lane(tx, cfg->regs, 3359 3119 cfg->tx_tbl, cfg->tx_tbl_num, 1); 3120 + if (cfg->tx_tbl_sec) 3121 + qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, 3122 + cfg->tx_tbl_num_sec, 1); 3123 + 3360 3124 /* Configuration for other LANE for USB-DP combo PHY */ 3361 - if (cfg->is_dual_lane_phy) 3125 + if (cfg->is_dual_lane_phy) { 3362 3126 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, 3363 3127 cfg->tx_tbl, cfg->tx_tbl_num, 2); 3128 + if (cfg->tx_tbl_sec) 3129 + qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, 3130 + cfg->tx_tbl_sec, 3131 + cfg->tx_tbl_num_sec, 2); 3132 + } 3364 3133 3365 3134 /* Configure special DP tx tunings */ 3366 3135 if (cfg->type == PHY_TYPE_DP) ··· 3377 3128 3378 3129 qcom_qmp_phy_configure_lane(rx, cfg->regs, 3379 3130 cfg->rx_tbl, cfg->rx_tbl_num, 1); 3131 + if (cfg->rx_tbl_sec) 3132 + qcom_qmp_phy_configure_lane(rx, cfg->regs, 3133 + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); 3380 3134 3381 - if (cfg->is_dual_lane_phy) 3135 + if (cfg->is_dual_lane_phy) { 3382 3136 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, 3383 3137 cfg->rx_tbl, cfg->rx_tbl_num, 2); 3138 + if (cfg->rx_tbl_sec) 3139 + qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, 3140 + cfg->rx_tbl_sec, 3141 + cfg->rx_tbl_num_sec, 2); 3142 + } 3384 3143 3385 3144 /* Configure link rate, swing, etc. */ 3386 - if (cfg->type == PHY_TYPE_DP) 3145 + if (cfg->type == PHY_TYPE_DP) { 3387 3146 qcom_qmp_phy_configure_dp_phy(qphy); 3388 - else 3147 + } else { 3389 3148 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 3149 + if (cfg->pcs_tbl_sec) 3150 + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 3151 + cfg->pcs_tbl_num_sec); 3152 + } 3390 3153 3391 3154 ret = reset_control_deassert(qmp->ufs_reset); 3392 3155 if (ret) ··· 3406 3145 3407 3146 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, 3408 3147 cfg->pcs_misc_tbl_num); 3148 + if (cfg->pcs_misc_tbl_sec) 3149 + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, 3150 + cfg->pcs_misc_tbl_num_sec); 3409 3151 3410 3152 /* 3411 3153 * Pull out PHY from POWER DOWN state. ··· 4164 3900 }, { 4165 3901 .compatible = "qcom,sm8250-qmp-usb3-uni-phy", 4166 3902 .data = &sm8250_usb3_uniphy_cfg, 3903 + }, { 3904 + .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 3905 + .data = &sm8250_qmp_gen3x1_pciephy_cfg, 3906 + }, { 3907 + .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 3908 + .data = &sm8250_qmp_gen3x2_pciephy_cfg, 3909 + }, { 3910 + .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 3911 + .data = &sm8250_qmp_gen3x2_pciephy_cfg, 4167 3912 }, 4168 3913 { }, 4169 3914 };
+18
drivers/phy/qualcomm/phy-qcom-qmp.h
··· 403 403 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 404 404 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 405 405 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 406 + #define QSERDES_V4_COM_CLK_ENABLE1 0x048 406 407 #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 407 408 #define QSERDES_V4_COM_PLL_IVCO 0x058 408 409 #define QSERDES_V4_COM_CMN_IPTRIM 0x060 ··· 433 432 #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 434 433 #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 435 434 #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 435 + #define QSERDES_V4_COM_CLK_SELECT 0x154 436 436 #define QSERDES_V4_COM_HSCLK_SEL 0x158 437 437 #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 438 438 #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c ··· 473 471 #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 474 472 #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 475 473 #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 474 + #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 476 475 #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 477 476 #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 478 477 #define QSERDES_V4_RX_RX_TERM_BW 0x080 479 478 #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 480 479 #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 481 480 #define QSERDES_V4_RX_GM_CAL 0x0dc 481 + #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 482 482 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 483 483 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 484 484 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 ··· 489 485 #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 490 486 #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 491 487 #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 488 + #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 492 489 #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 493 490 #define QSERDES_V4_RX_SIGDET_LVL 0x120 494 491 #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 ··· 810 805 #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 811 806 #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 812 807 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 808 + 809 + /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 810 + #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 811 + #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 812 + #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 813 + #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 814 + #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 815 + #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 816 + #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 817 + #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 818 + #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 819 + #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 820 + #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 813 821 814 822 #endif