tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clocksource/drivers/tcb_clksrc: Make IO endian agnostic

Now that AVR32 is gone, we can use the proper IO accessors that are
correctly handling endianness.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

authored by

Alexandre Belloni and committed by
Daniel Lezcano 6ec8be25 239751ed

+29 -29
+29 -29
drivers/clocksource/tcb_clksrc.c
··· 57 57 58 58 raw_local_irq_save(flags); 59 59 do { 60 - upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)); 61 - lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV)); 62 - } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV))); 60 + upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)); 61 + lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV)); 62 + } while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV))); 63 63 64 64 raw_local_irq_restore(flags); 65 65 return (upper << 16) | lower; ··· 67 67 68 68 static u64 tc_get_cycles32(struct clocksource *cs) 69 69 { 70 - return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV)); 70 + return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV)); 71 71 } 72 72 73 73 void tc_clksrc_suspend(struct clocksource *cs) ··· 147 147 struct tc_clkevt_device *tcd = to_tc_clkevt(d); 148 148 void __iomem *regs = tcd->regs; 149 149 150 - __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR)); 151 - __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); 150 + writel(0xff, regs + ATMEL_TC_REG(2, IDR)); 151 + writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); 152 152 if (!clockevent_state_detached(d)) 153 153 clk_disable(tcd->clk); 154 154 ··· 166 166 clk_enable(tcd->clk); 167 167 168 168 /* slow clock, count up to RC, then irq and stop */ 169 - __raw_writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE | 169 + writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE | 170 170 ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR)); 171 - __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); 171 + writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); 172 172 173 173 /* set_next_event() configures and starts the timer */ 174 174 return 0; ··· 188 188 clk_enable(tcd->clk); 189 189 190 190 /* slow clock, count up to RC, then irq and restart */ 191 - __raw_writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO, 191 + writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO, 192 192 regs + ATMEL_TC_REG(2, CMR)); 193 - __raw_writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); 193 + writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); 194 194 195 195 /* Enable clock and interrupts on RC compare */ 196 - __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); 196 + writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); 197 197 198 198 /* go go gadget! */ 199 - __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs + 199 + writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs + 200 200 ATMEL_TC_REG(2, CCR)); 201 201 return 0; 202 202 } 203 203 204 204 static int tc_next_event(unsigned long delta, struct clock_event_device *d) 205 205 { 206 - __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC)); 206 + writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC)); 207 207 208 208 /* go go gadget! */ 209 - __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, 209 + writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, 210 210 tcaddr + ATMEL_TC_REG(2, CCR)); 211 211 return 0; 212 212 } ··· 230 230 struct tc_clkevt_device *dev = handle; 231 231 unsigned int sr; 232 232 233 - sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR)); 233 + sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR)); 234 234 if (sr & ATMEL_TC_CPCS) { 235 235 dev->clkevt.event_handler(&dev->clkevt); 236 236 return IRQ_HANDLED; ··· 290 290 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx) 291 291 { 292 292 /* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */ 293 - __raw_writel(mck_divisor_idx /* likely divide-by-8 */ 293 + writel(mck_divisor_idx /* likely divide-by-8 */ 294 294 | ATMEL_TC_WAVE 295 295 | ATMEL_TC_WAVESEL_UP /* free-run */ 296 296 | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */ 297 297 | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */ 298 298 tcaddr + ATMEL_TC_REG(0, CMR)); 299 - __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA)); 300 - __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC)); 301 - __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ 302 - __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); 299 + writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA)); 300 + writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC)); 301 + writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ 302 + writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); 303 303 304 304 /* channel 1: waveform mode, input TIOA0 */ 305 - __raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */ 305 + writel(ATMEL_TC_XC1 /* input: TIOA0 */ 306 306 | ATMEL_TC_WAVE 307 307 | ATMEL_TC_WAVESEL_UP, /* free-run */ 308 308 tcaddr + ATMEL_TC_REG(1, CMR)); 309 - __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */ 310 - __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); 309 + writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */ 310 + writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); 311 311 312 312 /* chain channel 0 to channel 1*/ 313 - __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR); 313 + writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR); 314 314 /* then reset all the timers */ 315 - __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); 315 + writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); 316 316 } 317 317 318 318 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx) 319 319 { 320 320 /* channel 0: waveform mode, input mclk/8 */ 321 - __raw_writel(mck_divisor_idx /* likely divide-by-8 */ 321 + writel(mck_divisor_idx /* likely divide-by-8 */ 322 322 | ATMEL_TC_WAVE 323 323 | ATMEL_TC_WAVESEL_UP, /* free-run */ 324 324 tcaddr + ATMEL_TC_REG(0, CMR)); 325 - __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ 326 - __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); 325 + writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ 326 + writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); 327 327 328 328 /* then reset all the timers */ 329 - __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); 329 + writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); 330 330 } 331 331 332 332 static int __init tcb_clksrc_init(void)