fsl-rio: Split rio driver into two parts, RapidIO endpoint and message unit

+1 -1

arch/powerpc/sysdev/Makefile

··· 20 20 obj-$(CONFIG_FSL_GTM) += fsl_gtm.o 21 21 obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o 22 22 obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o 23 - obj-$(CONFIG_FSL_RIO) += fsl_rio.o 23 + obj-$(CONFIG_FSL_RIO) += fsl_rio.o fsl_rmu.o 24 24 obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 25 25 obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 26 26 obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/

+25 -1127

arch/powerpc/sysdev/fsl_rio.c

··· 10 10 * - Added Port-Write message handling 11 11 * - Added Machine Check exception handling 12 12 * 13 - * Copyright (C) 2007, 2008, 2010 Freescale Semiconductor, Inc. 13 + * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc. 14 14 * Zhang Wei <wei.zhang@freescale.com> 15 15 * 16 16 * Copyright 2005 MontaVista Software, Inc. ··· 28 28 #include <linux/dma-mapping.h> 29 29 #include <linux/interrupt.h> 30 30 #include <linux/device.h> 31 - #include <linux/rio.h> 32 - #include <linux/rio_drv.h> 33 31 #include <linux/of_platform.h> 34 32 #include <linux/delay.h> 35 33 #include <linux/slab.h> 36 - #include <linux/kfifo.h> 37 34 38 - #include <asm/io.h> 35 + #include <linux/io.h> 36 + #include <linux/uaccess.h> 39 37 #include <asm/machdep.h> 40 - #include <asm/uaccess.h> 38 + 39 + #include "fsl_rio.h" 41 40 42 41 #undef DEBUG_PW /* Port-Write debugging */ 43 - 44 - /* RapidIO definition irq, which read from OF-tree */ 45 - #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq) 46 - #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq) 47 - #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq) 48 - #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq) 49 - 50 - #define IPWSR_CLEAR 0x98 51 - #define OMSR_CLEAR 0x1cb3 52 - #define IMSR_CLEAR 0x491 53 - #define IDSR_CLEAR 0x91 54 - #define ODSR_CLEAR 0x1c00 55 - #define LTLEECSR_ENABLE_ALL 0xFFC000FC 56 - #define ESCSR_CLEAR 0x07120204 57 - #define IECSR_CLEAR 0x80000000 58 42 59 43 #define RIO_PORT1_EDCSR 0x0640 60 44 #define RIO_PORT2_EDCSR 0x0680 61 45 #define RIO_PORT1_IECSR 0x10130 62 46 #define RIO_PORT2_IECSR 0x101B0 63 - #define RIO_IM0SR 0x13064 64 - #define RIO_IM1SR 0x13164 65 - #define RIO_OM0SR 0x13004 66 - #define RIO_OM1SR 0x13104 67 47 68 48 #define RIO_ATMU_REGS_OFFSET 0x10c00 69 - #define RIO_P_MSG_REGS_OFFSET 0x11000 70 - #define RIO_S_MSG_REGS_OFFSET 0x13000 71 49 #define RIO_GCCSR 0x13c 72 50 #define RIO_ESCSR 0x158 51 + #define ESCSR_CLEAR 0x07120204 73 52 #define RIO_PORT2_ESCSR 0x178 74 53 #define RIO_CCSR 0x15c 75 - #define RIO_LTLEDCSR 0x0608 76 54 #define RIO_LTLEDCSR_IER 0x80000000 77 55 #define RIO_LTLEDCSR_PRT 0x01000000 78 - #define RIO_LTLEECSR 0x060c 79 - #define RIO_EPWISR 0x10010 56 + #define IECSR_CLEAR 0x80000000 80 57 #define RIO_ISR_AACR 0x10120 81 58 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ 82 - #define RIO_MAINT_WIN_SIZE 0x400000 83 - #define RIO_DBELL_WIN_SIZE 0x1000 84 - 85 - #define RIO_MSG_OMR_MUI 0x00000002 86 - #define RIO_MSG_OSR_TE 0x00000080 87 - #define RIO_MSG_OSR_QOI 0x00000020 88 - #define RIO_MSG_OSR_QFI 0x00000010 89 - #define RIO_MSG_OSR_MUB 0x00000004 90 - #define RIO_MSG_OSR_EOMI 0x00000002 91 - #define RIO_MSG_OSR_QEI 0x00000001 92 - 93 - #define RIO_MSG_IMR_MI 0x00000002 94 - #define RIO_MSG_ISR_TE 0x00000080 95 - #define RIO_MSG_ISR_QFI 0x00000010 96 - #define RIO_MSG_ISR_DIQI 0x00000001 97 - 98 - #define RIO_IPWMR_SEN 0x00100000 99 - #define RIO_IPWMR_QFIE 0x00000100 100 - #define RIO_IPWMR_EIE 0x00000020 101 - #define RIO_IPWMR_CQ 0x00000002 102 - #define RIO_IPWMR_PWE 0x00000001 103 - 104 - #define RIO_IPWSR_QF 0x00100000 105 - #define RIO_IPWSR_TE 0x00000080 106 - #define RIO_IPWSR_QFI 0x00000010 107 - #define RIO_IPWSR_PWD 0x00000008 108 - #define RIO_IPWSR_PWB 0x00000004 109 - 110 - /* EPWISR Error match value */ 111 - #define RIO_EPWISR_PINT1 0x80000000 112 - #define RIO_EPWISR_PINT2 0x40000000 113 - #define RIO_EPWISR_MU 0x00000002 114 - #define RIO_EPWISR_PW 0x00000001 115 - 116 - #define RIO_MSG_DESC_SIZE 32 117 - #define RIO_MSG_BUFFER_SIZE 4096 118 - #define RIO_MIN_TX_RING_SIZE 2 119 - #define RIO_MAX_TX_RING_SIZE 2048 120 - #define RIO_MIN_RX_RING_SIZE 2 121 - #define RIO_MAX_RX_RING_SIZE 2048 122 - 123 - #define DOORBELL_DMR_DI 0x00000002 124 - #define DOORBELL_DSR_TE 0x00000080 125 - #define DOORBELL_DSR_QFI 0x00000010 126 - #define DOORBELL_DSR_DIQI 0x00000001 127 - #define DOORBELL_TID_OFFSET 0x02 128 - #define DOORBELL_SID_OFFSET 0x04 129 - #define DOORBELL_INFO_OFFSET 0x06 130 - 131 - #define DOORBELL_MESSAGE_SIZE 0x08 132 - #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET)) 133 - #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET)) 134 - #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) 135 - 136 - struct rio_atmu_regs { 137 - u32 rowtar; 138 - u32 rowtear; 139 - u32 rowbar; 140 - u32 pad2; 141 - u32 rowar; 142 - u32 pad3[3]; 143 - }; 144 - 145 - struct rio_msg_regs { 146 - u32 omr; /* 0xD_3000 - Outbound message 0 mode register */ 147 - u32 osr; /* 0xD_3004 - Outbound message 0 status register */ 148 - u32 pad1; 149 - u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue 150 - dequeue pointer address register */ 151 - u32 pad2; 152 - u32 osar; /* 0xD_3014 - Outbound message 0 source address 153 - register */ 154 - u32 odpr; /* 0xD_3018 - Outbound message 0 destination port 155 - register */ 156 - u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes 157 - Register*/ 158 - u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count 159 - register */ 160 - u32 pad3; 161 - u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue 162 - enqueue pointer address register */ 163 - u32 pad4[13]; 164 - u32 imr; /* 0xD_3060 - Inbound message 0 mode register */ 165 - u32 isr; /* 0xD_3064 - Inbound message 0 status register */ 166 - u32 pad5; 167 - u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue 168 - pointer address register*/ 169 - u32 pad6; 170 - u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue 171 - pointer address register */ 172 - u32 pad7[226]; 173 - u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */ 174 - u32 odsr; /* 0xD_3404 - Outbound doorbell status register */ 175 - u32 res0[4]; 176 - u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port 177 - register */ 178 - u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes 179 - register */ 180 - u32 res1[3]; 181 - u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold 182 - configuration register */ 183 - u32 res2[12]; 184 - u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */ 185 - u32 dsr; /* 0xD_3464 - Inbound doorbell status register */ 186 - u32 pad8; 187 - u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer 188 - address register */ 189 - u32 pad9; 190 - u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer 191 - address register */ 192 - u32 pad10[26]; 193 - u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */ 194 - u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */ 195 - u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address 196 - register */ 197 - u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address 198 - register */ 199 - }; 200 - 201 - struct rio_tx_desc { 202 - u32 res1; 203 - u32 saddr; 204 - u32 dport; 205 - u32 dattr; 206 - u32 res2; 207 - u32 res3; 208 - u32 dwcnt; 209 - u32 res4; 210 - }; 211 - 212 - struct rio_dbell_ring { 213 - void *virt; 214 - dma_addr_t phys; 215 - }; 216 - 217 - struct rio_msg_tx_ring { 218 - void *virt; 219 - dma_addr_t phys; 220 - void *virt_buffer[RIO_MAX_TX_RING_SIZE]; 221 - dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; 222 - int tx_slot; 223 - int size; 224 - void *dev_id; 225 - }; 226 - 227 - struct rio_msg_rx_ring { 228 - void *virt; 229 - dma_addr_t phys; 230 - void *virt_buffer[RIO_MAX_RX_RING_SIZE]; 231 - int rx_slot; 232 - int size; 233 - void *dev_id; 234 - }; 235 - 236 - struct rio_port_write_msg { 237 - void *virt; 238 - dma_addr_t phys; 239 - u32 msg_count; 240 - u32 err_count; 241 - u32 discard_count; 242 - }; 243 - 244 - struct rio_priv { 245 - struct device *dev; 246 - void __iomem *regs_win; 247 - struct rio_atmu_regs __iomem *atmu_regs; 248 - struct rio_atmu_regs __iomem *maint_atmu_regs; 249 - struct rio_atmu_regs __iomem *dbell_atmu_regs; 250 - void __iomem *dbell_win; 251 - void __iomem *maint_win; 252 - struct rio_msg_regs __iomem *msg_regs; 253 - struct rio_dbell_ring dbell_ring; 254 - struct rio_msg_tx_ring msg_tx_ring; 255 - struct rio_msg_rx_ring msg_rx_ring; 256 - struct rio_port_write_msg port_write_msg; 257 - int bellirq; 258 - int txirq; 259 - int rxirq; 260 - int pwirq; 261 - struct work_struct pw_work; 262 - struct kfifo pw_fifo; 263 - spinlock_t pw_fifo_lock; 264 - }; 265 59 266 60 #define __fsl_read_rio_config(x, addr, err, op) \ 267 61 __asm__ __volatile__( \ ··· 73 279 : "=r" (err), "=r" (x) \ 74 280 : "b" (addr), "i" (-EFAULT), "0" (err)) 75 281 76 - static void __iomem *rio_regs_win; 282 + void __iomem *rio_regs_win; 77 283 78 284 #ifdef CONFIG_E500 79 285 int fsl_rio_mcheck_exception(struct pt_regs *regs) ··· 105 311 #endif 106 312 107 313 /** 108 - * fsl_rio_doorbell_send - Send a MPC85xx doorbell message 109 - * @mport: RapidIO master port info 110 - * @index: ID of RapidIO interface 111 - * @destid: Destination ID of target device 112 - * @data: 16-bit info field of RapidIO doorbell message 113 - * 114 - * Sends a MPC85xx doorbell message. Returns %0 on success or 115 - * %-EINVAL on failure. 116 - */ 117 - static int fsl_rio_doorbell_send(struct rio_mport *mport, 118 - int index, u16 destid, u16 data) 119 - { 120 - struct rio_priv *priv = mport->priv; 121 - pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n", 122 - index, destid, data); 123 - switch (mport->phy_type) { 124 - case RIO_PHY_PARALLEL: 125 - out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22); 126 - out_be16(priv->dbell_win, data); 127 - break; 128 - case RIO_PHY_SERIAL: 129 - /* In the serial version silicons, such as MPC8548, MPC8641, 130 - * below operations is must be. 131 - */ 132 - out_be32(&priv->msg_regs->odmr, 0x00000000); 133 - out_be32(&priv->msg_regs->odretcr, 0x00000004); 134 - out_be32(&priv->msg_regs->oddpr, destid << 16); 135 - out_be32(&priv->msg_regs->oddatr, data); 136 - out_be32(&priv->msg_regs->odmr, 0x00000001); 137 - break; 138 - } 139 - 140 - return 0; 141 - } 142 - 143 - /** 144 314 * fsl_local_config_read - Generate a MPC85xx local config space read 145 315 * @mport: RapidIO master port info 146 316 * @index: ID of RapdiIO interface ··· 120 362 { 121 363 struct rio_priv *priv = mport->priv; 122 364 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index, 123 - offset); 365 + offset); 124 366 *data = in_be32(priv->regs_win + offset); 125 367 126 368 return 0; ··· 142 384 { 143 385 struct rio_priv *priv = mport->priv; 144 386 pr_debug 145 - ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", 146 - index, offset, data); 387 + ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", 388 + index, offset, data); 147 389 out_be32(priv->regs_win + offset, data); 148 390 149 391 return 0; ··· 171 413 u32 rval, err = 0; 172 414 173 415 pr_debug 174 - ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", 416 + ("fsl_rio_config_read:" 417 + " index %d destid %d hopcount %d offset %8.8x len %d\n", 175 418 index, destid, hopcount, offset, len); 176 419 177 420 /* 16MB maintenance window possible */ ··· 182 423 183 424 out_be32(&priv->maint_atmu_regs->rowtar, 184 425 (destid << 22) | (hopcount << 12) | (offset >> 12)); 185 - out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 426 + out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 186 427 187 428 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 188 429 switch (len) { ··· 229 470 struct rio_priv *priv = mport->priv; 230 471 u8 *data; 231 472 pr_debug 232 - ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", 473 + ("fsl_rio_config_write:" 474 + "index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", 233 475 index, destid, hopcount, offset, len, val); 234 476 235 477 /* 16MB maintenance windows possible */ ··· 240 480 241 481 out_be32(&priv->maint_atmu_regs->rowtar, 242 482 (destid << 22) | (hopcount << 12) | (offset >> 12)); 243 - out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 483 + out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); 244 484 245 485 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); 246 486 switch (len) { ··· 260 500 return 0; 261 501 } 262 502 263 - /** 264 - * fsl_add_outb_message - Add message to the MPC85xx outbound message queue 265 - * @mport: Master port with outbound message queue 266 - * @rdev: Target of outbound message 267 - * @mbox: Outbound mailbox 268 - * @buffer: Message to add to outbound queue 269 - * @len: Length of message 270 - * 271 - * Adds the @buffer message to the MPC85xx outbound message queue. Returns 272 - * %0 on success or %-EINVAL on failure. 273 - */ 274 - static int 275 - fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, 276 - void *buffer, size_t len) 277 - { 278 - struct rio_priv *priv = mport->priv; 279 - u32 omr; 280 - struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt 281 - + priv->msg_tx_ring.tx_slot; 282 - int ret = 0; 283 - 284 - pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \ 285 - "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len); 286 - 287 - if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { 288 - ret = -EINVAL; 289 - goto out; 290 - } 291 - 292 - /* Copy and clear rest of buffer */ 293 - memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer, 294 - len); 295 - if (len < (RIO_MAX_MSG_SIZE - 4)) 296 - memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot] 297 - + len, 0, RIO_MAX_MSG_SIZE - len); 298 - 299 - switch (mport->phy_type) { 300 - case RIO_PHY_PARALLEL: 301 - /* Set mbox field for message */ 302 - desc->dport = mbox & 0x3; 303 - 304 - /* Enable EOMI interrupt, set priority, and set destid */ 305 - desc->dattr = 0x28000000 | (rdev->destid << 2); 306 - break; 307 - case RIO_PHY_SERIAL: 308 - /* Set mbox field for message, and set destid */ 309 - desc->dport = (rdev->destid << 16) | (mbox & 0x3); 310 - 311 - /* Enable EOMI interrupt and priority */ 312 - desc->dattr = 0x28000000; 313 - break; 314 - } 315 - 316 - /* Set transfer size aligned to next power of 2 (in double words) */ 317 - desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); 318 - 319 - /* Set snooping and source buffer address */ 320 - desc->saddr = 0x00000004 321 - | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot]; 322 - 323 - /* Increment enqueue pointer */ 324 - omr = in_be32(&priv->msg_regs->omr); 325 - out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI); 326 - 327 - /* Go to next descriptor */ 328 - if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size) 329 - priv->msg_tx_ring.tx_slot = 0; 330 - 331 - out: 332 - return ret; 333 - } 334 - 335 - /** 336 - * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler 337 - * @irq: Linux interrupt number 338 - * @dev_instance: Pointer to interrupt-specific data 339 - * 340 - * Handles outbound message interrupts. Executes a register outbound 341 - * mailbox event handler and acks the interrupt occurrence. 342 - */ 343 - static irqreturn_t 344 - fsl_rio_tx_handler(int irq, void *dev_instance) 345 - { 346 - int osr; 347 - struct rio_mport *port = (struct rio_mport *)dev_instance; 348 - struct rio_priv *priv = port->priv; 349 - 350 - osr = in_be32(&priv->msg_regs->osr); 351 - 352 - if (osr & RIO_MSG_OSR_TE) { 353 - pr_info("RIO: outbound message transmission error\n"); 354 - out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE); 355 - goto out; 356 - } 357 - 358 - if (osr & RIO_MSG_OSR_QOI) { 359 - pr_info("RIO: outbound message queue overflow\n"); 360 - out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI); 361 - goto out; 362 - } 363 - 364 - if (osr & RIO_MSG_OSR_EOMI) { 365 - u32 dqp = in_be32(&priv->msg_regs->odqdpar); 366 - int slot = (dqp - priv->msg_tx_ring.phys) >> 5; 367 - port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1, 368 - slot); 369 - 370 - /* Ack the end-of-message interrupt */ 371 - out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI); 372 - } 373 - 374 - out: 375 - return IRQ_HANDLED; 376 - } 377 - 378 - /** 379 - * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox 380 - * @mport: Master port implementing the outbound message unit 381 - * @dev_id: Device specific pointer to pass on event 382 - * @mbox: Mailbox to open 383 - * @entries: Number of entries in the outbound mailbox ring 384 - * 385 - * Initializes buffer ring, request the outbound message interrupt, 386 - * and enables the outbound message unit. Returns %0 on success and 387 - * %-EINVAL or %-ENOMEM on failure. 388 - */ 389 - static int 390 - fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 391 - { 392 - int i, j, rc = 0; 393 - struct rio_priv *priv = mport->priv; 394 - 395 - if ((entries < RIO_MIN_TX_RING_SIZE) || 396 - (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { 397 - rc = -EINVAL; 398 - goto out; 399 - } 400 - 401 - /* Initialize shadow copy ring */ 402 - priv->msg_tx_ring.dev_id = dev_id; 403 - priv->msg_tx_ring.size = entries; 404 - 405 - for (i = 0; i < priv->msg_tx_ring.size; i++) { 406 - priv->msg_tx_ring.virt_buffer[i] = 407 - dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 408 - &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL); 409 - if (!priv->msg_tx_ring.virt_buffer[i]) { 410 - rc = -ENOMEM; 411 - for (j = 0; j < priv->msg_tx_ring.size; j++) 412 - if (priv->msg_tx_ring.virt_buffer[j]) 413 - dma_free_coherent(priv->dev, 414 - RIO_MSG_BUFFER_SIZE, 415 - priv->msg_tx_ring. 416 - virt_buffer[j], 417 - priv->msg_tx_ring. 418 - phys_buffer[j]); 419 - goto out; 420 - } 421 - } 422 - 423 - /* Initialize outbound message descriptor ring */ 424 - priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, 425 - priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 426 - &priv->msg_tx_ring.phys, GFP_KERNEL); 427 - if (!priv->msg_tx_ring.virt) { 428 - rc = -ENOMEM; 429 - goto out_dma; 430 - } 431 - memset(priv->msg_tx_ring.virt, 0, 432 - priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE); 433 - priv->msg_tx_ring.tx_slot = 0; 434 - 435 - /* Point dequeue/enqueue pointers at first entry in ring */ 436 - out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys); 437 - out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys); 438 - 439 - /* Configure for snooping */ 440 - out_be32(&priv->msg_regs->osar, 0x00000004); 441 - 442 - /* Clear interrupt status */ 443 - out_be32(&priv->msg_regs->osr, 0x000000b3); 444 - 445 - /* Hook up outbound message handler */ 446 - rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, 447 - "msg_tx", (void *)mport); 448 - if (rc < 0) 449 - goto out_irq; 450 - 451 - /* 452 - * Configure outbound message unit 453 - * Snooping 454 - * Interrupts (all enabled, except QEIE) 455 - * Chaining mode 456 - * Disable 457 - */ 458 - out_be32(&priv->msg_regs->omr, 0x00100220); 459 - 460 - /* Set number of entries */ 461 - out_be32(&priv->msg_regs->omr, 462 - in_be32(&priv->msg_regs->omr) | 463 - ((get_bitmask_order(entries) - 2) << 12)); 464 - 465 - /* Now enable the unit */ 466 - out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1); 467 - 468 - out: 469 - return rc; 470 - 471 - out_irq: 472 - dma_free_coherent(priv->dev, 473 - priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 474 - priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); 475 - 476 - out_dma: 477 - for (i = 0; i < priv->msg_tx_ring.size; i++) 478 - dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 479 - priv->msg_tx_ring.virt_buffer[i], 480 - priv->msg_tx_ring.phys_buffer[i]); 481 - 482 - return rc; 483 - } 484 - 485 - /** 486 - * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox 487 - * @mport: Master port implementing the outbound message unit 488 - * @mbox: Mailbox to close 489 - * 490 - * Disables the outbound message unit, free all buffers, and 491 - * frees the outbound message interrupt. 492 - */ 493 - static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox) 494 - { 495 - struct rio_priv *priv = mport->priv; 496 - /* Disable inbound message unit */ 497 - out_be32(&priv->msg_regs->omr, 0); 498 - 499 - /* Free ring */ 500 - dma_free_coherent(priv->dev, 501 - priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 502 - priv->msg_tx_ring.virt, priv->msg_tx_ring.phys); 503 - 504 - /* Free interrupt */ 505 - free_irq(IRQ_RIO_TX(mport), (void *)mport); 506 - } 507 - 508 - /** 509 - * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler 510 - * @irq: Linux interrupt number 511 - * @dev_instance: Pointer to interrupt-specific data 512 - * 513 - * Handles inbound message interrupts. Executes a registered inbound 514 - * mailbox event handler and acks the interrupt occurrence. 515 - */ 516 - static irqreturn_t 517 - fsl_rio_rx_handler(int irq, void *dev_instance) 518 - { 519 - int isr; 520 - struct rio_mport *port = (struct rio_mport *)dev_instance; 521 - struct rio_priv *priv = port->priv; 522 - 523 - isr = in_be32(&priv->msg_regs->isr); 524 - 525 - if (isr & RIO_MSG_ISR_TE) { 526 - pr_info("RIO: inbound message reception error\n"); 527 - out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE); 528 - goto out; 529 - } 530 - 531 - /* XXX Need to check/dispatch until queue empty */ 532 - if (isr & RIO_MSG_ISR_DIQI) { 533 - /* 534 - * We implement *only* mailbox 0, but can receive messages 535 - * for any mailbox/letter to that mailbox destination. So, 536 - * make the callback with an unknown/invalid mailbox number 537 - * argument. 538 - */ 539 - port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1); 540 - 541 - /* Ack the queueing interrupt */ 542 - out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI); 543 - } 544 - 545 - out: 546 - return IRQ_HANDLED; 547 - } 548 - 549 - /** 550 - * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox 551 - * @mport: Master port implementing the inbound message unit 552 - * @dev_id: Device specific pointer to pass on event 553 - * @mbox: Mailbox to open 554 - * @entries: Number of entries in the inbound mailbox ring 555 - * 556 - * Initializes buffer ring, request the inbound message interrupt, 557 - * and enables the inbound message unit. Returns %0 on success 558 - * and %-EINVAL or %-ENOMEM on failure. 559 - */ 560 - static int 561 - fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 562 - { 563 - int i, rc = 0; 564 - struct rio_priv *priv = mport->priv; 565 - 566 - if ((entries < RIO_MIN_RX_RING_SIZE) || 567 - (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { 568 - rc = -EINVAL; 569 - goto out; 570 - } 571 - 572 - /* Initialize client buffer ring */ 573 - priv->msg_rx_ring.dev_id = dev_id; 574 - priv->msg_rx_ring.size = entries; 575 - priv->msg_rx_ring.rx_slot = 0; 576 - for (i = 0; i < priv->msg_rx_ring.size; i++) 577 - priv->msg_rx_ring.virt_buffer[i] = NULL; 578 - 579 - /* Initialize inbound message ring */ 580 - priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, 581 - priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 582 - &priv->msg_rx_ring.phys, GFP_KERNEL); 583 - if (!priv->msg_rx_ring.virt) { 584 - rc = -ENOMEM; 585 - goto out; 586 - } 587 - 588 - /* Point dequeue/enqueue pointers at first entry in ring */ 589 - out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys); 590 - out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys); 591 - 592 - /* Clear interrupt status */ 593 - out_be32(&priv->msg_regs->isr, 0x00000091); 594 - 595 - /* Hook up inbound message handler */ 596 - rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, 597 - "msg_rx", (void *)mport); 598 - if (rc < 0) { 599 - dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 600 - priv->msg_tx_ring.virt_buffer[i], 601 - priv->msg_tx_ring.phys_buffer[i]); 602 - goto out; 603 - } 604 - 605 - /* 606 - * Configure inbound message unit: 607 - * Snooping 608 - * 4KB max message size 609 - * Unmask all interrupt sources 610 - * Disable 611 - */ 612 - out_be32(&priv->msg_regs->imr, 0x001b0060); 613 - 614 - /* Set number of queue entries */ 615 - setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); 616 - 617 - /* Now enable the unit */ 618 - setbits32(&priv->msg_regs->imr, 0x1); 619 - 620 - out: 621 - return rc; 622 - } 623 - 624 - /** 625 - * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox 626 - * @mport: Master port implementing the inbound message unit 627 - * @mbox: Mailbox to close 628 - * 629 - * Disables the inbound message unit, free all buffers, and 630 - * frees the inbound message interrupt. 631 - */ 632 - static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox) 633 - { 634 - struct rio_priv *priv = mport->priv; 635 - /* Disable inbound message unit */ 636 - out_be32(&priv->msg_regs->imr, 0); 637 - 638 - /* Free ring */ 639 - dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 640 - priv->msg_rx_ring.virt, priv->msg_rx_ring.phys); 641 - 642 - /* Free interrupt */ 643 - free_irq(IRQ_RIO_RX(mport), (void *)mport); 644 - } 645 - 646 - /** 647 - * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue 648 - * @mport: Master port implementing the inbound message unit 649 - * @mbox: Inbound mailbox number 650 - * @buf: Buffer to add to inbound queue 651 - * 652 - * Adds the @buf buffer to the MPC85xx inbound message queue. Returns 653 - * %0 on success or %-EINVAL on failure. 654 - */ 655 - static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) 656 - { 657 - int rc = 0; 658 - struct rio_priv *priv = mport->priv; 659 - 660 - pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", 661 - priv->msg_rx_ring.rx_slot); 662 - 663 - if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) { 664 - printk(KERN_ERR 665 - "RIO: error adding inbound buffer %d, buffer exists\n", 666 - priv->msg_rx_ring.rx_slot); 667 - rc = -EINVAL; 668 - goto out; 669 - } 670 - 671 - priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf; 672 - if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size) 673 - priv->msg_rx_ring.rx_slot = 0; 674 - 675 - out: 676 - return rc; 677 - } 678 - 679 - /** 680 - * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit 681 - * @mport: Master port implementing the inbound message unit 682 - * @mbox: Inbound mailbox number 683 - * 684 - * Gets the next available inbound message from the inbound message queue. 685 - * A pointer to the message is returned on success or NULL on failure. 686 - */ 687 - static void *fsl_get_inb_message(struct rio_mport *mport, int mbox) 688 - { 689 - struct rio_priv *priv = mport->priv; 690 - u32 phys_buf, virt_buf; 691 - void *buf = NULL; 692 - int buf_idx; 693 - 694 - phys_buf = in_be32(&priv->msg_regs->ifqdpar); 695 - 696 - /* If no more messages, then bail out */ 697 - if (phys_buf == in_be32(&priv->msg_regs->ifqepar)) 698 - goto out2; 699 - 700 - virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf 701 - - priv->msg_rx_ring.phys); 702 - buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; 703 - buf = priv->msg_rx_ring.virt_buffer[buf_idx]; 704 - 705 - if (!buf) { 706 - printk(KERN_ERR 707 - "RIO: inbound message copy failed, no buffers\n"); 708 - goto out1; 709 - } 710 - 711 - /* Copy max message size, caller is expected to allocate that big */ 712 - memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); 713 - 714 - /* Clear the available buffer */ 715 - priv->msg_rx_ring.virt_buffer[buf_idx] = NULL; 716 - 717 - out1: 718 - setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI); 719 - 720 - out2: 721 - return buf; 722 - } 723 - 724 - /** 725 - * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler 726 - * @irq: Linux interrupt number 727 - * @dev_instance: Pointer to interrupt-specific data 728 - * 729 - * Handles doorbell interrupts. Parses a list of registered 730 - * doorbell event handlers and executes a matching event handler. 731 - */ 732 - static irqreturn_t 733 - fsl_rio_dbell_handler(int irq, void *dev_instance) 734 - { 735 - int dsr; 736 - struct rio_mport *port = (struct rio_mport *)dev_instance; 737 - struct rio_priv *priv = port->priv; 738 - 739 - dsr = in_be32(&priv->msg_regs->dsr); 740 - 741 - if (dsr & DOORBELL_DSR_TE) { 742 - pr_info("RIO: doorbell reception error\n"); 743 - out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE); 744 - goto out; 745 - } 746 - 747 - if (dsr & DOORBELL_DSR_QFI) { 748 - pr_info("RIO: doorbell queue full\n"); 749 - out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI); 750 - } 751 - 752 - /* XXX Need to check/dispatch until queue empty */ 753 - if (dsr & DOORBELL_DSR_DIQI) { 754 - u32 dmsg = 755 - (u32) priv->dbell_ring.virt + 756 - (in_be32(&priv->msg_regs->dqdpar) & 0xfff); 757 - struct rio_dbell *dbell; 758 - int found = 0; 759 - 760 - pr_debug 761 - ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n", 762 - DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 763 - 764 - list_for_each_entry(dbell, &port->dbells, node) { 765 - if ((dbell->res->start <= DBELL_INF(dmsg)) && 766 - (dbell->res->end >= DBELL_INF(dmsg))) { 767 - found = 1; 768 - break; 769 - } 770 - } 771 - if (found) { 772 - dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg), 773 - DBELL_INF(dmsg)); 774 - } else { 775 - pr_debug 776 - ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n", 777 - DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 778 - } 779 - setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI); 780 - out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI); 781 - } 782 - 783 - out: 784 - return IRQ_HANDLED; 785 - } 786 - 787 - /** 788 - * fsl_rio_doorbell_init - MPC85xx doorbell interface init 789 - * @mport: Master port implementing the inbound doorbell unit 790 - * 791 - * Initializes doorbell unit hardware and inbound DMA buffer 792 - * ring. Called from fsl_rio_setup(). Returns %0 on success 793 - * or %-ENOMEM on failure. 794 - */ 795 - static int fsl_rio_doorbell_init(struct rio_mport *mport) 796 - { 797 - struct rio_priv *priv = mport->priv; 798 - int rc = 0; 799 - 800 - /* Map outbound doorbell window immediately after maintenance window */ 801 - priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE, 802 - RIO_DBELL_WIN_SIZE); 803 - if (!priv->dbell_win) { 804 - printk(KERN_ERR 805 - "RIO: unable to map outbound doorbell window\n"); 806 - rc = -ENOMEM; 807 - goto out; 808 - } 809 - 810 - /* Initialize inbound doorbells */ 811 - priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 * 812 - DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL); 813 - if (!priv->dbell_ring.virt) { 814 - printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); 815 - rc = -ENOMEM; 816 - iounmap(priv->dbell_win); 817 - goto out; 818 - } 819 - 820 - /* Point dequeue/enqueue pointers at first entry in ring */ 821 - out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys); 822 - out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys); 823 - 824 - /* Clear interrupt status */ 825 - out_be32(&priv->msg_regs->dsr, 0x00000091); 826 - 827 - /* Hook up doorbell handler */ 828 - rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0, 829 - "dbell_rx", (void *)mport); 830 - if (rc < 0) { 831 - iounmap(priv->dbell_win); 832 - dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE, 833 - priv->dbell_ring.virt, priv->dbell_ring.phys); 834 - printk(KERN_ERR 835 - "MPC85xx RIO: unable to request inbound doorbell irq"); 836 - goto out; 837 - } 838 - 839 - /* Configure doorbells for snooping, 512 entries, and enable */ 840 - out_be32(&priv->msg_regs->dmr, 0x00108161); 841 - 842 - out: 843 - return rc; 844 - } 845 - 846 - static void port_error_handler(struct rio_mport *port, int offset) 503 + void fsl_rio_port_error_handler(struct rio_mport *port, int offset) 847 504 { 848 505 /*XXX: Error recovery is not implemented, we just clear errors */ 849 506 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); ··· 275 1098 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR); 276 1099 } 277 1100 } 278 - 279 - static void msg_unit_error_handler(struct rio_mport *port) 280 - { 281 - struct rio_priv *priv = port->priv; 282 - 283 - /*XXX: Error recovery is not implemented, we just clear errors */ 284 - out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 285 - 286 - out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR); 287 - out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR); 288 - out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR); 289 - out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR); 290 - 291 - out_be32(&priv->msg_regs->odsr, ODSR_CLEAR); 292 - out_be32(&priv->msg_regs->dsr, IDSR_CLEAR); 293 - 294 - out_be32(&priv->msg_regs->pwsr, IPWSR_CLEAR); 295 - } 296 - 297 - /** 298 - * fsl_rio_port_write_handler - MPC85xx port write interrupt handler 299 - * @irq: Linux interrupt number 300 - * @dev_instance: Pointer to interrupt-specific data 301 - * 302 - * Handles port write interrupts. Parses a list of registered 303 - * port write event handlers and executes a matching event handler. 304 - */ 305 - static irqreturn_t 306 - fsl_rio_port_write_handler(int irq, void *dev_instance) 307 - { 308 - u32 ipwmr, ipwsr; 309 - struct rio_mport *port = (struct rio_mport *)dev_instance; 310 - struct rio_priv *priv = port->priv; 311 - u32 epwisr, tmp; 312 - 313 - epwisr = in_be32(priv->regs_win + RIO_EPWISR); 314 - if (!(epwisr & RIO_EPWISR_PW)) 315 - goto pw_done; 316 - 317 - ipwmr = in_be32(&priv->msg_regs->pwmr); 318 - ipwsr = in_be32(&priv->msg_regs->pwsr); 319 - 320 - #ifdef DEBUG_PW 321 - pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); 322 - if (ipwsr & RIO_IPWSR_QF) 323 - pr_debug(" QF"); 324 - if (ipwsr & RIO_IPWSR_TE) 325 - pr_debug(" TE"); 326 - if (ipwsr & RIO_IPWSR_QFI) 327 - pr_debug(" QFI"); 328 - if (ipwsr & RIO_IPWSR_PWD) 329 - pr_debug(" PWD"); 330 - if (ipwsr & RIO_IPWSR_PWB) 331 - pr_debug(" PWB"); 332 - pr_debug(" )\n"); 333 - #endif 334 - /* Schedule deferred processing if PW was received */ 335 - if (ipwsr & RIO_IPWSR_QFI) { 336 - /* Save PW message (if there is room in FIFO), 337 - * otherwise discard it. 338 - */ 339 - if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) { 340 - priv->port_write_msg.msg_count++; 341 - kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt, 342 - RIO_PW_MSG_SIZE); 343 - } else { 344 - priv->port_write_msg.discard_count++; 345 - pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", 346 - priv->port_write_msg.discard_count); 347 - } 348 - /* Clear interrupt and issue Clear Queue command. This allows 349 - * another port-write to be received. 350 - */ 351 - out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI); 352 - out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ); 353 - 354 - schedule_work(&priv->pw_work); 355 - } 356 - 357 - if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) { 358 - priv->port_write_msg.err_count++; 359 - pr_debug("RIO: Port-Write Transaction Err (%d)\n", 360 - priv->port_write_msg.err_count); 361 - /* Clear Transaction Error: port-write controller should be 362 - * disabled when clearing this error 363 - */ 364 - out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE); 365 - out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE); 366 - out_be32(&priv->msg_regs->pwmr, ipwmr); 367 - } 368 - 369 - if (ipwsr & RIO_IPWSR_PWD) { 370 - priv->port_write_msg.discard_count++; 371 - pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n", 372 - priv->port_write_msg.discard_count); 373 - out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD); 374 - } 375 - 376 - pw_done: 377 - if (epwisr & RIO_EPWISR_PINT1) { 378 - tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 379 - pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 380 - port_error_handler(port, 0); 381 - } 382 - 383 - if (epwisr & RIO_EPWISR_PINT2) { 384 - tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 385 - pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 386 - port_error_handler(port, 1); 387 - } 388 - 389 - if (epwisr & RIO_EPWISR_MU) { 390 - tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 391 - pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 392 - msg_unit_error_handler(port); 393 - } 394 - 395 - return IRQ_HANDLED; 396 - } 397 - 398 - static void fsl_pw_dpc(struct work_struct *work) 399 - { 400 - struct rio_priv *priv = container_of(work, struct rio_priv, pw_work); 401 - unsigned long flags; 402 - u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; 403 - 404 - /* 405 - * Process port-write messages 406 - */ 407 - spin_lock_irqsave(&priv->pw_fifo_lock, flags); 408 - while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer, 409 - RIO_PW_MSG_SIZE)) { 410 - /* Process one message */ 411 - spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); 412 - #ifdef DEBUG_PW 413 - { 414 - u32 i; 415 - pr_debug("%s : Port-Write Message:", __func__); 416 - for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) { 417 - if ((i%4) == 0) 418 - pr_debug("\n0x%02x: 0x%08x", i*4, 419 - msg_buffer[i]); 420 - else 421 - pr_debug(" 0x%08x", msg_buffer[i]); 422 - } 423 - pr_debug("\n"); 424 - } 425 - #endif 426 - /* Pass the port-write message to RIO core for processing */ 427 - rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer); 428 - spin_lock_irqsave(&priv->pw_fifo_lock, flags); 429 - } 430 - spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); 431 - } 432 - 433 - /** 434 - * fsl_rio_pw_enable - enable/disable port-write interface init 435 - * @mport: Master port implementing the port write unit 436 - * @enable: 1=enable; 0=disable port-write message handling 437 - */ 438 - static int fsl_rio_pw_enable(struct rio_mport *mport, int enable) 439 - { 440 - struct rio_priv *priv = mport->priv; 441 - u32 rval; 442 - 443 - rval = in_be32(&priv->msg_regs->pwmr); 444 - 445 - if (enable) 446 - rval |= RIO_IPWMR_PWE; 447 - else 448 - rval &= ~RIO_IPWMR_PWE; 449 - 450 - out_be32(&priv->msg_regs->pwmr, rval); 451 - 452 - return 0; 453 - } 454 - 455 - /** 456 - * fsl_rio_port_write_init - MPC85xx port write interface init 457 - * @mport: Master port implementing the port write unit 458 - * 459 - * Initializes port write unit hardware and DMA buffer 460 - * ring. Called from fsl_rio_setup(). Returns %0 on success 461 - * or %-ENOMEM on failure. 462 - */ 463 - static int fsl_rio_port_write_init(struct rio_mport *mport) 464 - { 465 - struct rio_priv *priv = mport->priv; 466 - int rc = 0; 467 - 468 - /* Following configurations require a disabled port write controller */ 469 - out_be32(&priv->msg_regs->pwmr, 470 - in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE); 471 - 472 - /* Initialize port write */ 473 - priv->port_write_msg.virt = dma_alloc_coherent(priv->dev, 474 - RIO_PW_MSG_SIZE, 475 - &priv->port_write_msg.phys, GFP_KERNEL); 476 - if (!priv->port_write_msg.virt) { 477 - pr_err("RIO: unable allocate port write queue\n"); 478 - return -ENOMEM; 479 - } 480 - 481 - priv->port_write_msg.err_count = 0; 482 - priv->port_write_msg.discard_count = 0; 483 - 484 - /* Point dequeue/enqueue pointers at first entry */ 485 - out_be32(&priv->msg_regs->epwqbar, 0); 486 - out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys); 487 - 488 - pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n", 489 - in_be32(&priv->msg_regs->epwqbar), 490 - in_be32(&priv->msg_regs->pwqbar)); 491 - 492 - /* Clear interrupt status IPWSR */ 493 - out_be32(&priv->msg_regs->pwsr, 494 - (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); 495 - 496 - /* Configure port write contoller for snooping enable all reporting, 497 - clear queue full */ 498 - out_be32(&priv->msg_regs->pwmr, 499 - RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ); 500 - 501 - 502 - /* Hook up port-write handler */ 503 - rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 504 - IRQF_SHARED, "port-write", (void *)mport); 505 - if (rc < 0) { 506 - pr_err("MPC85xx RIO: unable to request inbound doorbell irq"); 507 - goto err_out; 508 - } 509 - /* Enable Error Interrupt */ 510 - out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL); 511 - 512 - INIT_WORK(&priv->pw_work, fsl_pw_dpc); 513 - spin_lock_init(&priv->pw_fifo_lock); 514 - if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { 515 - pr_err("FIFO allocation failed\n"); 516 - rc = -ENOMEM; 517 - goto err_out_irq; 518 - } 519 - 520 - pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n", 521 - in_be32(&priv->msg_regs->pwmr), 522 - in_be32(&priv->msg_regs->pwsr)); 523 - 524 - return rc; 525 - 526 - err_out_irq: 527 - free_irq(IRQ_RIO_PW(mport), (void *)mport); 528 - err_out: 529 - dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE, 530 - priv->port_write_msg.virt, 531 - priv->port_write_msg.phys); 532 - return rc; 533 - } 534 - 535 1101 static inline void fsl_rio_info(struct device *dev, u32 ccsr) 536 1102 { 537 1103 const char *str; ··· 349 1429 dev->dev.of_node->full_name); 350 1430 return -EFAULT; 351 1431 } 352 - dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name); 1432 + dev_info(&dev->dev, "Of-device full name %s\n", 1433 + dev->dev.of_node->full_name); 353 1434 dev_info(&dev->dev, "Regs: %pR\n", &regs); 354 1435 355 1436 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen); ··· 390 1469 ops->lcwrite = fsl_local_config_write; 391 1470 ops->cread = fsl_rio_config_read; 392 1471 ops->cwrite = fsl_rio_config_write; 393 - ops->dsend = fsl_rio_doorbell_send; 394 1472 ops->pwenable = fsl_rio_pw_enable; 395 - ops->open_outb_mbox = fsl_open_outb_mbox; 396 - ops->open_inb_mbox = fsl_open_inb_mbox; 397 - ops->close_outb_mbox = fsl_close_outb_mbox; 398 - ops->close_inb_mbox = fsl_close_inb_mbox; 399 - ops->add_outb_message = fsl_add_outb_message; 400 - ops->add_inb_buffer = fsl_add_inb_buffer; 401 - ops->get_inb_message = fsl_get_inb_message; 402 1473 403 1474 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); 404 1475 if (!port) { ··· 420 1507 goto err_res; 421 1508 } 422 1509 423 - priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); 424 - priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2); 425 - priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3); 426 - priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4); 427 - dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n", 428 - priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq); 429 - 430 - rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 431 - rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); 432 - rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); 1510 + priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0); 1511 + dev_info(&dev->dev, "pwirq: %d\n", priv->pwirq); 433 1512 strcpy(port->name, "RIO0 mport"); 434 1513 435 1514 priv->dev = &dev->dev; ··· 443 1538 /* Checking the port training status */ 444 1539 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) { 445 1540 dev_err(&dev->dev, "Port is not ready. " 446 - "Try to restart connection...\n"); 1541 + "Try to restart connection...\n"); 447 1542 switch (port->phy_type) { 448 1543 case RIO_PHY_SERIAL: 449 1544 /* Disable ports */ ··· 487 1582 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win 488 1583 + RIO_ATMU_REGS_OFFSET); 489 1584 priv->maint_atmu_regs = priv->atmu_regs + 1; 490 - priv->dbell_atmu_regs = priv->atmu_regs + 2; 491 - priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win + 492 - ((port->phy_type == RIO_PHY_SERIAL) ? 493 - RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET)); 494 1585 495 1586 /* Set to receive any dist ID for serial RapidIO controller. */ 496 1587 if (port->phy_type == RIO_PHY_SERIAL) ··· 499 1598 500 1599 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE); 501 1600 502 - /* Configure outbound doorbell window */ 503 - out_be32(&priv->dbell_atmu_regs->rowbar, 504 - (law_start + RIO_MAINT_WIN_SIZE) >> 12); 505 - out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */ 506 - fsl_rio_doorbell_init(port); 1601 + fsl_rio_setup_rmu(port, dev->dev.of_node); 1602 + 507 1603 fsl_rio_port_write_init(port); 508 1604 509 1605 return 0;

+78

arch/powerpc/sysdev/fsl_rio.h

··· 1 + /* 2 + * Freescale MPC85xx/MPC86xx RapidIO support 3 + * 4 + * Copyright 2009 Sysgo AG 5 + * Thomas Moll <thomas.moll@sysgo.com> 6 + * - fixed maintenance access routines, check for aligned access 7 + * 8 + * Copyright 2009 Integrated Device Technology, Inc. 9 + * Alex Bounine <alexandre.bounine@idt.com> 10 + * - Added Port-Write message handling 11 + * - Added Machine Check exception handling 12 + * 13 + * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc. 14 + * Zhang Wei <wei.zhang@freescale.com> 15 + * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com> 16 + * Liu Gang <Gang.Liu@freescale.com> 17 + * 18 + * Copyright 2005 MontaVista Software, Inc. 19 + * Matt Porter <mporter@kernel.crashing.org> 20 + * 21 + * This program is free software; you can redistribute it and/or modify it 22 + * under the terms of the GNU General Public License as published by the 23 + * Free Software Foundation; either version 2 of the License, or (at your 24 + * option) any later version. 25 + */ 26 + 27 + #ifndef __FSL_RIO_H 28 + #define __FSL_RIO_H 29 + 30 + #include <linux/rio.h> 31 + #include <linux/rio_drv.h> 32 + #include <linux/kfifo.h> 33 + 34 + #define RIO_REGS_WIN(mport) (((struct rio_priv *)(mport->priv))->regs_win) 35 + 36 + #define RIO_MAINT_WIN_SIZE 0x400000 37 + #define RIO_LTLEDCSR 0x0608 38 + 39 + struct rio_atmu_regs { 40 + u32 rowtar; 41 + u32 rowtear; 42 + u32 rowbar; 43 + u32 pad2; 44 + u32 rowar; 45 + u32 pad3[3]; 46 + }; 47 + 48 + struct rio_port_write_msg { 49 + void *virt; 50 + dma_addr_t phys; 51 + u32 msg_count; 52 + u32 err_count; 53 + u32 discard_count; 54 + }; 55 + 56 + struct rio_priv { 57 + struct device *dev; 58 + void __iomem *regs_win; 59 + struct rio_atmu_regs __iomem *atmu_regs; 60 + struct rio_atmu_regs __iomem *maint_atmu_regs; 61 + void __iomem *maint_win; 62 + struct rio_port_write_msg port_write_msg; 63 + int pwirq; 64 + struct work_struct pw_work; 65 + struct kfifo pw_fifo; 66 + spinlock_t pw_fifo_lock; 67 + void *rmm_handle; /* RapidIO message manager(unit) Handle */ 68 + }; 69 + 70 + extern void __iomem *rio_regs_win; 71 + 72 + extern int fsl_rio_setup_rmu(struct rio_mport *mport, 73 + struct device_node *node); 74 + extern int fsl_rio_port_write_init(struct rio_mport *mport); 75 + extern int fsl_rio_pw_enable(struct rio_mport *mport, int enable); 76 + extern void fsl_rio_port_error_handler(struct rio_mport *port, int offset); 77 + 78 + #endif

+1163

arch/powerpc/sysdev/fsl_rmu.c

··· 1 + /* 2 + * Freescale MPC85xx/MPC86xx RapidIO RMU support 3 + * 4 + * Copyright 2009 Sysgo AG 5 + * Thomas Moll <thomas.moll@sysgo.com> 6 + * - fixed maintenance access routines, check for aligned access 7 + * 8 + * Copyright 2009 Integrated Device Technology, Inc. 9 + * Alex Bounine <alexandre.bounine@idt.com> 10 + * - Added Port-Write message handling 11 + * - Added Machine Check exception handling 12 + * 13 + * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc. 14 + * Zhang Wei <wei.zhang@freescale.com> 15 + * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com> 16 + * Liu Gang <Gang.Liu@freescale.com> 17 + * 18 + * Copyright 2005 MontaVista Software, Inc. 19 + * Matt Porter <mporter@kernel.crashing.org> 20 + * 21 + * This program is free software; you can redistribute it and/or modify it 22 + * under the terms of the GNU General Public License as published by the 23 + * Free Software Foundation; either version 2 of the License, or (at your 24 + * option) any later version. 25 + */ 26 + 27 + #include <linux/types.h> 28 + #include <linux/dma-mapping.h> 29 + #include <linux/interrupt.h> 30 + #include <linux/of_platform.h> 31 + #include <linux/slab.h> 32 + 33 + #include "fsl_rio.h" 34 + 35 + #define GET_RMM_HANDLE(mport) \ 36 + (((struct rio_priv *)(mport->priv))->rmm_handle) 37 + 38 + /* RapidIO definition irq, which read from OF-tree */ 39 + #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq) 40 + #define IRQ_RIO_BELL(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->bellirq) 41 + #define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq) 42 + #define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq) 43 + 44 + #define RIO_MIN_TX_RING_SIZE 2 45 + #define RIO_MAX_TX_RING_SIZE 2048 46 + #define RIO_MIN_RX_RING_SIZE 2 47 + #define RIO_MAX_RX_RING_SIZE 2048 48 + 49 + #define RIO_IPWMR_SEN 0x00100000 50 + #define RIO_IPWMR_QFIE 0x00000100 51 + #define RIO_IPWMR_EIE 0x00000020 52 + #define RIO_IPWMR_CQ 0x00000002 53 + #define RIO_IPWMR_PWE 0x00000001 54 + 55 + #define RIO_IPWSR_QF 0x00100000 56 + #define RIO_IPWSR_TE 0x00000080 57 + #define RIO_IPWSR_QFI 0x00000010 58 + #define RIO_IPWSR_PWD 0x00000008 59 + #define RIO_IPWSR_PWB 0x00000004 60 + 61 + #define RIO_EPWISR 0x10010 62 + /* EPWISR Error match value */ 63 + #define RIO_EPWISR_PINT1 0x80000000 64 + #define RIO_EPWISR_PINT2 0x40000000 65 + #define RIO_EPWISR_MU 0x00000002 66 + #define RIO_EPWISR_PW 0x00000001 67 + 68 + #define IPWSR_CLEAR 0x98 69 + #define OMSR_CLEAR 0x1cb3 70 + #define IMSR_CLEAR 0x491 71 + #define IDSR_CLEAR 0x91 72 + #define ODSR_CLEAR 0x1c00 73 + #define LTLEECSR_ENABLE_ALL 0xFFC000FC 74 + #define RIO_LTLEECSR 0x060c 75 + 76 + #define RIO_IM0SR 0x13064 77 + #define RIO_IM1SR 0x13164 78 + #define RIO_OM0SR 0x13004 79 + #define RIO_OM1SR 0x13104 80 + 81 + #define RIO_P_MSG_REGS_OFFSET 0x11000 82 + #define RIO_S_MSG_REGS_OFFSET 0x13000 83 + 84 + #define RIO_DBELL_WIN_SIZE 0x1000 85 + 86 + #define RIO_MSG_OMR_MUI 0x00000002 87 + #define RIO_MSG_OSR_TE 0x00000080 88 + #define RIO_MSG_OSR_QOI 0x00000020 89 + #define RIO_MSG_OSR_QFI 0x00000010 90 + #define RIO_MSG_OSR_MUB 0x00000004 91 + #define RIO_MSG_OSR_EOMI 0x00000002 92 + #define RIO_MSG_OSR_QEI 0x00000001 93 + 94 + #define RIO_MSG_IMR_MI 0x00000002 95 + #define RIO_MSG_ISR_TE 0x00000080 96 + #define RIO_MSG_ISR_QFI 0x00000010 97 + #define RIO_MSG_ISR_DIQI 0x00000001 98 + 99 + #define RIO_MSG_DESC_SIZE 32 100 + #define RIO_MSG_BUFFER_SIZE 4096 101 + 102 + #define DOORBELL_DMR_DI 0x00000002 103 + #define DOORBELL_DSR_TE 0x00000080 104 + #define DOORBELL_DSR_QFI 0x00000010 105 + #define DOORBELL_DSR_DIQI 0x00000001 106 + #define DOORBELL_TID_OFFSET 0x02 107 + #define DOORBELL_SID_OFFSET 0x04 108 + #define DOORBELL_INFO_OFFSET 0x06 109 + 110 + #define DOORBELL_MESSAGE_SIZE 0x08 111 + #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET)) 112 + #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET)) 113 + #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) 114 + 115 + struct rio_msg_regs { 116 + u32 omr; /* 0xD_3000 - Outbound message 0 mode register */ 117 + u32 osr; /* 0xD_3004 - Outbound message 0 status register */ 118 + u32 pad1; 119 + u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue 120 + dequeue pointer address register */ 121 + u32 pad2; 122 + u32 osar; /* 0xD_3014 - Outbound message 0 source address 123 + register */ 124 + u32 odpr; /* 0xD_3018 - Outbound message 0 destination port 125 + register */ 126 + u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes 127 + Register*/ 128 + u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count 129 + register */ 130 + u32 pad3; 131 + u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue 132 + enqueue pointer address register */ 133 + u32 pad4[13]; 134 + u32 imr; /* 0xD_3060 - Inbound message 0 mode register */ 135 + u32 isr; /* 0xD_3064 - Inbound message 0 status register */ 136 + u32 pad5; 137 + u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue 138 + pointer address register*/ 139 + u32 pad6; 140 + u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue 141 + pointer address register */ 142 + u32 pad7[226]; 143 + u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */ 144 + u32 odsr; /* 0xD_3404 - Outbound doorbell status register */ 145 + u32 res0[4]; 146 + u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port 147 + register */ 148 + u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes 149 + register */ 150 + u32 res1[3]; 151 + u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold 152 + configuration register */ 153 + u32 res2[12]; 154 + u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */ 155 + u32 dsr; /* 0xD_3464 - Inbound doorbell status register */ 156 + u32 pad8; 157 + u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer 158 + address register */ 159 + u32 pad9; 160 + u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer 161 + address register */ 162 + u32 pad10[26]; 163 + u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */ 164 + u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */ 165 + u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address 166 + register */ 167 + u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address 168 + register */ 169 + }; 170 + 171 + struct rio_tx_desc { 172 + u32 res1; 173 + u32 saddr; 174 + u32 dport; 175 + u32 dattr; 176 + u32 res2; 177 + u32 res3; 178 + u32 dwcnt; 179 + u32 res4; 180 + }; 181 + 182 + struct rio_dbell_ring { 183 + void *virt; 184 + dma_addr_t phys; 185 + }; 186 + 187 + struct rio_msg_tx_ring { 188 + void *virt; 189 + dma_addr_t phys; 190 + void *virt_buffer[RIO_MAX_TX_RING_SIZE]; 191 + dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; 192 + int tx_slot; 193 + int size; 194 + void *dev_id; 195 + }; 196 + 197 + struct rio_msg_rx_ring { 198 + void *virt; 199 + dma_addr_t phys; 200 + void *virt_buffer[RIO_MAX_RX_RING_SIZE]; 201 + int rx_slot; 202 + int size; 203 + void *dev_id; 204 + }; 205 + 206 + struct fsl_rmu { 207 + struct rio_atmu_regs __iomem *dbell_atmu_regs; 208 + void __iomem *dbell_win; 209 + struct rio_msg_regs __iomem *msg_regs; 210 + struct rio_dbell_ring dbell_ring; 211 + struct rio_msg_tx_ring msg_tx_ring; 212 + struct rio_msg_rx_ring msg_rx_ring; 213 + int bellirq; 214 + int txirq; 215 + int rxirq; 216 + }; 217 + 218 + /** 219 + * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler 220 + * @irq: Linux interrupt number 221 + * @dev_instance: Pointer to interrupt-specific data 222 + * 223 + * Handles outbound message interrupts. Executes a register outbound 224 + * mailbox event handler and acks the interrupt occurrence. 225 + */ 226 + static irqreturn_t 227 + fsl_rio_tx_handler(int irq, void *dev_instance) 228 + { 229 + int osr; 230 + struct rio_mport *port = (struct rio_mport *)dev_instance; 231 + struct fsl_rmu *rmu = GET_RMM_HANDLE(port); 232 + 233 + osr = in_be32(&rmu->msg_regs->osr); 234 + 235 + if (osr & RIO_MSG_OSR_TE) { 236 + pr_info("RIO: outbound message transmission error\n"); 237 + out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE); 238 + goto out; 239 + } 240 + 241 + if (osr & RIO_MSG_OSR_QOI) { 242 + pr_info("RIO: outbound message queue overflow\n"); 243 + out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI); 244 + goto out; 245 + } 246 + 247 + if (osr & RIO_MSG_OSR_EOMI) { 248 + u32 dqp = in_be32(&rmu->msg_regs->odqdpar); 249 + int slot = (dqp - rmu->msg_tx_ring.phys) >> 5; 250 + port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id, -1, 251 + slot); 252 + 253 + /* Ack the end-of-message interrupt */ 254 + out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI); 255 + } 256 + 257 + out: 258 + return IRQ_HANDLED; 259 + } 260 + 261 + /** 262 + * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler 263 + * @irq: Linux interrupt number 264 + * @dev_instance: Pointer to interrupt-specific data 265 + * 266 + * Handles inbound message interrupts. Executes a registered inbound 267 + * mailbox event handler and acks the interrupt occurrence. 268 + */ 269 + static irqreturn_t 270 + fsl_rio_rx_handler(int irq, void *dev_instance) 271 + { 272 + int isr; 273 + struct rio_mport *port = (struct rio_mport *)dev_instance; 274 + struct fsl_rmu *rmu = GET_RMM_HANDLE(port); 275 + 276 + isr = in_be32(&rmu->msg_regs->isr); 277 + 278 + if (isr & RIO_MSG_ISR_TE) { 279 + pr_info("RIO: inbound message reception error\n"); 280 + out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE); 281 + goto out; 282 + } 283 + 284 + /* XXX Need to check/dispatch until queue empty */ 285 + if (isr & RIO_MSG_ISR_DIQI) { 286 + /* 287 + * We implement *only* mailbox 0, but can receive messages 288 + * for any mailbox/letter to that mailbox destination. So, 289 + * make the callback with an unknown/invalid mailbox number 290 + * argument. 291 + */ 292 + port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id, -1, -1); 293 + 294 + /* Ack the queueing interrupt */ 295 + out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI); 296 + } 297 + 298 + out: 299 + return IRQ_HANDLED; 300 + } 301 + 302 + /** 303 + * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler 304 + * @irq: Linux interrupt number 305 + * @dev_instance: Pointer to interrupt-specific data 306 + * 307 + * Handles doorbell interrupts. Parses a list of registered 308 + * doorbell event handlers and executes a matching event handler. 309 + */ 310 + static irqreturn_t 311 + fsl_rio_dbell_handler(int irq, void *dev_instance) 312 + { 313 + int dsr; 314 + struct rio_mport *port = (struct rio_mport *)dev_instance; 315 + struct fsl_rmu *rmu = GET_RMM_HANDLE(port); 316 + 317 + dsr = in_be32(&rmu->msg_regs->dsr); 318 + 319 + if (dsr & DOORBELL_DSR_TE) { 320 + pr_info("RIO: doorbell reception error\n"); 321 + out_be32(&rmu->msg_regs->dsr, DOORBELL_DSR_TE); 322 + goto out; 323 + } 324 + 325 + if (dsr & DOORBELL_DSR_QFI) { 326 + pr_info("RIO: doorbell queue full\n"); 327 + out_be32(&rmu->msg_regs->dsr, DOORBELL_DSR_QFI); 328 + } 329 + 330 + /* XXX Need to check/dispatch until queue empty */ 331 + if (dsr & DOORBELL_DSR_DIQI) { 332 + u32 dmsg = 333 + (u32) rmu->dbell_ring.virt + 334 + (in_be32(&rmu->msg_regs->dqdpar) & 0xfff); 335 + struct rio_dbell *dbell; 336 + int found = 0; 337 + 338 + pr_debug 339 + ("RIO: processing doorbell," 340 + " sid %2.2x tid %2.2x info %4.4x\n", 341 + DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 342 + 343 + list_for_each_entry(dbell, &port->dbells, node) { 344 + if ((dbell->res->start <= DBELL_INF(dmsg)) && 345 + (dbell->res->end >= DBELL_INF(dmsg))) { 346 + found = 1; 347 + break; 348 + } 349 + } 350 + if (found) { 351 + dbell->dinb(port, dbell->dev_id, 352 + DBELL_SID(dmsg), 353 + DBELL_TID(dmsg), DBELL_INF(dmsg)); 354 + } else { 355 + pr_debug 356 + ("RIO: spurious doorbell," 357 + " sid %2.2x tid %2.2x info %4.4x\n", 358 + DBELL_SID(dmsg), DBELL_TID(dmsg), 359 + DBELL_INF(dmsg)); 360 + } 361 + setbits32(&rmu->msg_regs->dmr, DOORBELL_DMR_DI); 362 + out_be32(&rmu->msg_regs->dsr, DOORBELL_DSR_DIQI); 363 + } 364 + 365 + out: 366 + return IRQ_HANDLED; 367 + } 368 + 369 + void msg_unit_error_handler(struct rio_mport *port) 370 + { 371 + struct fsl_rmu *rmu = GET_RMM_HANDLE(port); 372 + 373 + /*XXX: Error recovery is not implemented, we just clear errors */ 374 + out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); 375 + 376 + out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR); 377 + out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR); 378 + out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR); 379 + out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR); 380 + 381 + out_be32(&rmu->msg_regs->odsr, ODSR_CLEAR); 382 + out_be32(&rmu->msg_regs->dsr, IDSR_CLEAR); 383 + 384 + out_be32(&rmu->msg_regs->pwsr, IPWSR_CLEAR); 385 + } 386 + 387 + /** 388 + * fsl_rio_port_write_handler - MPC85xx port write interrupt handler 389 + * @irq: Linux interrupt number 390 + * @dev_instance: Pointer to interrupt-specific data 391 + * 392 + * Handles port write interrupts. Parses a list of registered 393 + * port write event handlers and executes a matching event handler. 394 + */ 395 + static irqreturn_t 396 + fsl_rio_port_write_handler(int irq, void *dev_instance) 397 + { 398 + u32 ipwmr, ipwsr; 399 + struct rio_mport *port = (struct rio_mport *)dev_instance; 400 + struct rio_priv *priv = port->priv; 401 + struct fsl_rmu *rmu; 402 + u32 epwisr, tmp; 403 + 404 + rmu = GET_RMM_HANDLE(port); 405 + epwisr = in_be32(priv->regs_win + RIO_EPWISR); 406 + if (!(epwisr & RIO_EPWISR_PW)) 407 + goto pw_done; 408 + 409 + ipwmr = in_be32(&rmu->msg_regs->pwmr); 410 + ipwsr = in_be32(&rmu->msg_regs->pwsr); 411 + 412 + #ifdef DEBUG_PW 413 + pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); 414 + if (ipwsr & RIO_IPWSR_QF) 415 + pr_debug(" QF"); 416 + if (ipwsr & RIO_IPWSR_TE) 417 + pr_debug(" TE"); 418 + if (ipwsr & RIO_IPWSR_QFI) 419 + pr_debug(" QFI"); 420 + if (ipwsr & RIO_IPWSR_PWD) 421 + pr_debug(" PWD"); 422 + if (ipwsr & RIO_IPWSR_PWB) 423 + pr_debug(" PWB"); 424 + pr_debug(" )\n"); 425 + #endif 426 + /* Schedule deferred processing if PW was received */ 427 + if (ipwsr & RIO_IPWSR_QFI) { 428 + /* Save PW message (if there is room in FIFO), 429 + * otherwise discard it. 430 + */ 431 + if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) { 432 + priv->port_write_msg.msg_count++; 433 + kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt, 434 + RIO_PW_MSG_SIZE); 435 + } else { 436 + priv->port_write_msg.discard_count++; 437 + pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", 438 + priv->port_write_msg.discard_count); 439 + } 440 + /* Clear interrupt and issue Clear Queue command. This allows 441 + * another port-write to be received. 442 + */ 443 + out_be32(&rmu->msg_regs->pwsr, RIO_IPWSR_QFI); 444 + out_be32(&rmu->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ); 445 + 446 + schedule_work(&priv->pw_work); 447 + } 448 + 449 + if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) { 450 + priv->port_write_msg.err_count++; 451 + pr_debug("RIO: Port-Write Transaction Err (%d)\n", 452 + priv->port_write_msg.err_count); 453 + /* Clear Transaction Error: port-write controller should be 454 + * disabled when clearing this error 455 + */ 456 + out_be32(&rmu->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE); 457 + out_be32(&rmu->msg_regs->pwsr, RIO_IPWSR_TE); 458 + out_be32(&rmu->msg_regs->pwmr, ipwmr); 459 + } 460 + 461 + if (ipwsr & RIO_IPWSR_PWD) { 462 + priv->port_write_msg.discard_count++; 463 + pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n", 464 + priv->port_write_msg.discard_count); 465 + out_be32(&rmu->msg_regs->pwsr, RIO_IPWSR_PWD); 466 + } 467 + 468 + pw_done: 469 + if (epwisr & RIO_EPWISR_PINT1) { 470 + tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 471 + pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 472 + fsl_rio_port_error_handler(port, 0); 473 + } 474 + 475 + if (epwisr & RIO_EPWISR_PINT2) { 476 + tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 477 + pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 478 + fsl_rio_port_error_handler(port, 1); 479 + } 480 + 481 + if (epwisr & RIO_EPWISR_MU) { 482 + tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); 483 + pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); 484 + msg_unit_error_handler(port); 485 + } 486 + 487 + return IRQ_HANDLED; 488 + } 489 + 490 + static void fsl_pw_dpc(struct work_struct *work) 491 + { 492 + struct rio_priv *priv = container_of(work, struct rio_priv, pw_work); 493 + unsigned long flags; 494 + u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; 495 + 496 + /* 497 + * Process port-write messages 498 + */ 499 + spin_lock_irqsave(&priv->pw_fifo_lock, flags); 500 + while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer, 501 + RIO_PW_MSG_SIZE)) { 502 + /* Process one message */ 503 + spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); 504 + #ifdef DEBUG_PW 505 + { 506 + u32 i; 507 + pr_debug("%s : Port-Write Message:", __func__); 508 + for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) { 509 + if ((i%4) == 0) 510 + pr_debug("\n0x%02x: 0x%08x", i*4, 511 + msg_buffer[i]); 512 + else 513 + pr_debug(" 0x%08x", msg_buffer[i]); 514 + } 515 + pr_debug("\n"); 516 + } 517 + #endif 518 + /* Pass the port-write message to RIO core for processing */ 519 + rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer); 520 + spin_lock_irqsave(&priv->pw_fifo_lock, flags); 521 + } 522 + spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); 523 + } 524 + 525 + /** 526 + * fsl_rio_pw_enable - enable/disable port-write interface init 527 + * @mport: Master port implementing the port write unit 528 + * @enable: 1=enable; 0=disable port-write message handling 529 + */ 530 + int fsl_rio_pw_enable(struct rio_mport *mport, int enable) 531 + { 532 + struct fsl_rmu *rmu; 533 + u32 rval; 534 + 535 + rmu = GET_RMM_HANDLE(mport); 536 + 537 + rval = in_be32(&rmu->msg_regs->pwmr); 538 + 539 + if (enable) 540 + rval |= RIO_IPWMR_PWE; 541 + else 542 + rval &= ~RIO_IPWMR_PWE; 543 + 544 + out_be32(&rmu->msg_regs->pwmr, rval); 545 + 546 + return 0; 547 + } 548 + 549 + /** 550 + * fsl_rio_port_write_init - MPC85xx port write interface init 551 + * @mport: Master port implementing the port write unit 552 + * 553 + * Initializes port write unit hardware and DMA buffer 554 + * ring. Called from fsl_rio_setup(). Returns %0 on success 555 + * or %-ENOMEM on failure. 556 + */ 557 + 558 + int fsl_rio_port_write_init(struct rio_mport *mport) 559 + { 560 + struct rio_priv *priv = mport->priv; 561 + struct fsl_rmu *rmu; 562 + int rc = 0; 563 + 564 + rmu = GET_RMM_HANDLE(mport); 565 + 566 + /* Following configurations require a disabled port write controller */ 567 + out_be32(&rmu->msg_regs->pwmr, 568 + in_be32(&rmu->msg_regs->pwmr) & ~RIO_IPWMR_PWE); 569 + 570 + /* Initialize port write */ 571 + priv->port_write_msg.virt = dma_alloc_coherent(priv->dev, 572 + RIO_PW_MSG_SIZE, 573 + &priv->port_write_msg.phys, GFP_KERNEL); 574 + if (!priv->port_write_msg.virt) { 575 + pr_err("RIO: unable allocate port write queue\n"); 576 + return -ENOMEM; 577 + } 578 + 579 + priv->port_write_msg.err_count = 0; 580 + priv->port_write_msg.discard_count = 0; 581 + 582 + /* Point dequeue/enqueue pointers at first entry */ 583 + out_be32(&rmu->msg_regs->epwqbar, 0); 584 + out_be32(&rmu->msg_regs->pwqbar, (u32) priv->port_write_msg.phys); 585 + 586 + pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n", 587 + in_be32(&rmu->msg_regs->epwqbar), 588 + in_be32(&rmu->msg_regs->pwqbar)); 589 + 590 + /* Clear interrupt status IPWSR */ 591 + out_be32(&rmu->msg_regs->pwsr, 592 + (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); 593 + 594 + /* Configure port write contoller for snooping enable all reporting, 595 + clear queue full */ 596 + out_be32(&rmu->msg_regs->pwmr, 597 + RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ); 598 + 599 + 600 + /* Hook up port-write handler */ 601 + rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 602 + IRQF_SHARED, "port-write", (void *)mport); 603 + if (rc < 0) { 604 + pr_err("MPC85xx RIO: unable to request inbound doorbell irq"); 605 + goto err_out; 606 + } 607 + /* Enable Error Interrupt */ 608 + out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL); 609 + 610 + INIT_WORK(&priv->pw_work, fsl_pw_dpc); 611 + spin_lock_init(&priv->pw_fifo_lock); 612 + if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { 613 + pr_err("FIFO allocation failed\n"); 614 + rc = -ENOMEM; 615 + goto err_out_irq; 616 + } 617 + 618 + pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n", 619 + in_be32(&rmu->msg_regs->pwmr), 620 + in_be32(&rmu->msg_regs->pwsr)); 621 + 622 + return rc; 623 + 624 + err_out_irq: 625 + free_irq(IRQ_RIO_PW(mport), (void *)mport); 626 + err_out: 627 + dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE, 628 + priv->port_write_msg.virt, 629 + priv->port_write_msg.phys); 630 + return rc; 631 + } 632 + 633 + /** 634 + * fsl_rio_doorbell_send - Send a MPC85xx doorbell message 635 + * @mport: RapidIO master port info 636 + * @index: ID of RapidIO interface 637 + * @destid: Destination ID of target device 638 + * @data: 16-bit info field of RapidIO doorbell message 639 + * 640 + * Sends a MPC85xx doorbell message. Returns %0 on success or 641 + * %-EINVAL on failure. 642 + */ 643 + static int fsl_rio_doorbell_send(struct rio_mport *mport, 644 + int index, u16 destid, u16 data) 645 + { 646 + struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 647 + 648 + pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n", 649 + index, destid, data); 650 + switch (mport->phy_type) { 651 + case RIO_PHY_PARALLEL: 652 + out_be32(&rmu->dbell_atmu_regs->rowtar, destid << 22); 653 + out_be16(rmu->dbell_win, data); 654 + break; 655 + case RIO_PHY_SERIAL: 656 + /* In the serial version silicons, such as MPC8548, MPC8641, 657 + * below operations is must be. 658 + */ 659 + out_be32(&rmu->msg_regs->odmr, 0x00000000); 660 + out_be32(&rmu->msg_regs->odretcr, 0x00000004); 661 + out_be32(&rmu->msg_regs->oddpr, destid << 16); 662 + out_be32(&rmu->msg_regs->oddatr, data); 663 + out_be32(&rmu->msg_regs->odmr, 0x00000001); 664 + break; 665 + } 666 + 667 + return 0; 668 + } 669 + 670 + /** 671 + * fsl_add_outb_message - Add message to the MPC85xx outbound message queue 672 + * @mport: Master port with outbound message queue 673 + * @rdev: Target of outbound message 674 + * @mbox: Outbound mailbox 675 + * @buffer: Message to add to outbound queue 676 + * @len: Length of message 677 + * 678 + * Adds the @buffer message to the MPC85xx outbound message queue. Returns 679 + * %0 on success or %-EINVAL on failure. 680 + */ 681 + static int 682 + fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, 683 + void *buffer, size_t len) 684 + { 685 + struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 686 + u32 omr; 687 + struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt 688 + + rmu->msg_tx_ring.tx_slot; 689 + int ret = 0; 690 + 691 + pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \ 692 + "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len); 693 + 694 + if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { 695 + ret = -EINVAL; 696 + goto out; 697 + } 698 + 699 + /* Copy and clear rest of buffer */ 700 + memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer, 701 + len); 702 + if (len < (RIO_MAX_MSG_SIZE - 4)) 703 + memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot] 704 + + len, 0, RIO_MAX_MSG_SIZE - len); 705 + 706 + switch (mport->phy_type) { 707 + case RIO_PHY_PARALLEL: 708 + /* Set mbox field for message */ 709 + desc->dport = mbox & 0x3; 710 + 711 + /* Enable EOMI interrupt, set priority, and set destid */ 712 + desc->dattr = 0x28000000 | (rdev->destid << 2); 713 + break; 714 + case RIO_PHY_SERIAL: 715 + /* Set mbox field for message, and set destid */ 716 + desc->dport = (rdev->destid << 16) | (mbox & 0x3); 717 + 718 + /* Enable EOMI interrupt and priority */ 719 + desc->dattr = 0x28000000; 720 + break; 721 + } 722 + 723 + /* Set transfer size aligned to next power of 2 (in double words) */ 724 + desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); 725 + 726 + /* Set snooping and source buffer address */ 727 + desc->saddr = 0x00000004 728 + | rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot]; 729 + 730 + /* Increment enqueue pointer */ 731 + omr = in_be32(&rmu->msg_regs->omr); 732 + out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI); 733 + 734 + /* Go to next descriptor */ 735 + if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size) 736 + rmu->msg_tx_ring.tx_slot = 0; 737 + 738 + out: 739 + return ret; 740 + } 741 + 742 + /** 743 + * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox 744 + * @mport: Master port implementing the outbound message unit 745 + * @dev_id: Device specific pointer to pass on event 746 + * @mbox: Mailbox to open 747 + * @entries: Number of entries in the outbound mailbox ring 748 + * 749 + * Initializes buffer ring, request the outbound message interrupt, 750 + * and enables the outbound message unit. Returns %0 on success and 751 + * %-EINVAL or %-ENOMEM on failure. 752 + */ 753 + static int 754 + fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 755 + { 756 + int i, j, rc = 0; 757 + struct rio_priv *priv = mport->priv; 758 + struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 759 + 760 + if ((entries < RIO_MIN_TX_RING_SIZE) || 761 + (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { 762 + rc = -EINVAL; 763 + goto out; 764 + } 765 + 766 + /* Initialize shadow copy ring */ 767 + rmu->msg_tx_ring.dev_id = dev_id; 768 + rmu->msg_tx_ring.size = entries; 769 + 770 + for (i = 0; i < rmu->msg_tx_ring.size; i++) { 771 + rmu->msg_tx_ring.virt_buffer[i] = 772 + dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 773 + &rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL); 774 + if (!rmu->msg_tx_ring.virt_buffer[i]) { 775 + rc = -ENOMEM; 776 + for (j = 0; j < rmu->msg_tx_ring.size; j++) 777 + if (rmu->msg_tx_ring.virt_buffer[j]) 778 + dma_free_coherent(priv->dev, 779 + RIO_MSG_BUFFER_SIZE, 780 + rmu->msg_tx_ring. 781 + virt_buffer[j], 782 + rmu->msg_tx_ring. 783 + phys_buffer[j]); 784 + goto out; 785 + } 786 + } 787 + 788 + /* Initialize outbound message descriptor ring */ 789 + rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, 790 + rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 791 + &rmu->msg_tx_ring.phys, GFP_KERNEL); 792 + if (!rmu->msg_tx_ring.virt) { 793 + rc = -ENOMEM; 794 + goto out_dma; 795 + } 796 + memset(rmu->msg_tx_ring.virt, 0, 797 + rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE); 798 + rmu->msg_tx_ring.tx_slot = 0; 799 + 800 + /* Point dequeue/enqueue pointers at first entry in ring */ 801 + out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys); 802 + out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys); 803 + 804 + /* Configure for snooping */ 805 + out_be32(&rmu->msg_regs->osar, 0x00000004); 806 + 807 + /* Clear interrupt status */ 808 + out_be32(&rmu->msg_regs->osr, 0x000000b3); 809 + 810 + /* Hook up outbound message handler */ 811 + rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, 812 + "msg_tx", (void *)mport); 813 + if (rc < 0) 814 + goto out_irq; 815 + 816 + /* 817 + * Configure outbound message unit 818 + * Snooping 819 + * Interrupts (all enabled, except QEIE) 820 + * Chaining mode 821 + * Disable 822 + */ 823 + out_be32(&rmu->msg_regs->omr, 0x00100220); 824 + 825 + /* Set number of entries */ 826 + out_be32(&rmu->msg_regs->omr, 827 + in_be32(&rmu->msg_regs->omr) | 828 + ((get_bitmask_order(entries) - 2) << 12)); 829 + 830 + /* Now enable the unit */ 831 + out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1); 832 + 833 + out: 834 + return rc; 835 + 836 + out_irq: 837 + dma_free_coherent(priv->dev, 838 + rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 839 + rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); 840 + 841 + out_dma: 842 + for (i = 0; i < rmu->msg_tx_ring.size; i++) 843 + dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 844 + rmu->msg_tx_ring.virt_buffer[i], 845 + rmu->msg_tx_ring.phys_buffer[i]); 846 + 847 + return rc; 848 + } 849 + 850 + /** 851 + * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox 852 + * @mport: Master port implementing the outbound message unit 853 + * @mbox: Mailbox to close 854 + * 855 + * Disables the outbound message unit, free all buffers, and 856 + * frees the outbound message interrupt. 857 + */ 858 + static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox) 859 + { 860 + struct rio_priv *priv = mport->priv; 861 + struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 862 + 863 + /* Disable inbound message unit */ 864 + out_be32(&rmu->msg_regs->omr, 0); 865 + 866 + /* Free ring */ 867 + dma_free_coherent(priv->dev, 868 + rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, 869 + rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); 870 + 871 + /* Free interrupt */ 872 + free_irq(IRQ_RIO_TX(mport), (void *)mport); 873 + } 874 + 875 + /** 876 + * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox 877 + * @mport: Master port implementing the inbound message unit 878 + * @dev_id: Device specific pointer to pass on event 879 + * @mbox: Mailbox to open 880 + * @entries: Number of entries in the inbound mailbox ring 881 + * 882 + * Initializes buffer ring, request the inbound message interrupt, 883 + * and enables the inbound message unit. Returns %0 on success 884 + * and %-EINVAL or %-ENOMEM on failure. 885 + */ 886 + static int 887 + fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) 888 + { 889 + int i, rc = 0; 890 + struct rio_priv *priv = mport->priv; 891 + struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 892 + 893 + if ((entries < RIO_MIN_RX_RING_SIZE) || 894 + (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { 895 + rc = -EINVAL; 896 + goto out; 897 + } 898 + 899 + /* Initialize client buffer ring */ 900 + rmu->msg_rx_ring.dev_id = dev_id; 901 + rmu->msg_rx_ring.size = entries; 902 + rmu->msg_rx_ring.rx_slot = 0; 903 + for (i = 0; i < rmu->msg_rx_ring.size; i++) 904 + rmu->msg_rx_ring.virt_buffer[i] = NULL; 905 + 906 + /* Initialize inbound message ring */ 907 + rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, 908 + rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 909 + &rmu->msg_rx_ring.phys, GFP_KERNEL); 910 + if (!rmu->msg_rx_ring.virt) { 911 + rc = -ENOMEM; 912 + goto out; 913 + } 914 + 915 + /* Point dequeue/enqueue pointers at first entry in ring */ 916 + out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys); 917 + out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys); 918 + 919 + /* Clear interrupt status */ 920 + out_be32(&rmu->msg_regs->isr, 0x00000091); 921 + 922 + /* Hook up inbound message handler */ 923 + rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, 924 + "msg_rx", (void *)mport); 925 + if (rc < 0) { 926 + dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, 927 + rmu->msg_tx_ring.virt_buffer[i], 928 + rmu->msg_tx_ring.phys_buffer[i]); 929 + goto out; 930 + } 931 + 932 + /* 933 + * Configure inbound message unit: 934 + * Snooping 935 + * 4KB max message size 936 + * Unmask all interrupt sources 937 + * Disable 938 + */ 939 + out_be32(&rmu->msg_regs->imr, 0x001b0060); 940 + 941 + /* Set number of queue entries */ 942 + setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); 943 + 944 + /* Now enable the unit */ 945 + setbits32(&rmu->msg_regs->imr, 0x1); 946 + 947 + out: 948 + return rc; 949 + } 950 + 951 + /** 952 + * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox 953 + * @mport: Master port implementing the inbound message unit 954 + * @mbox: Mailbox to close 955 + * 956 + * Disables the inbound message unit, free all buffers, and 957 + * frees the inbound message interrupt. 958 + */ 959 + static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox) 960 + { 961 + struct rio_priv *priv = mport->priv; 962 + struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 963 + 964 + /* Disable inbound message unit */ 965 + out_be32(&rmu->msg_regs->imr, 0); 966 + 967 + /* Free ring */ 968 + dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, 969 + rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys); 970 + 971 + /* Free interrupt */ 972 + free_irq(IRQ_RIO_RX(mport), (void *)mport); 973 + } 974 + 975 + /** 976 + * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue 977 + * @mport: Master port implementing the inbound message unit 978 + * @mbox: Inbound mailbox number 979 + * @buf: Buffer to add to inbound queue 980 + * 981 + * Adds the @buf buffer to the MPC85xx inbound message queue. Returns 982 + * %0 on success or %-EINVAL on failure. 983 + */ 984 + static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) 985 + { 986 + int rc = 0; 987 + struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 988 + 989 + pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", 990 + rmu->msg_rx_ring.rx_slot); 991 + 992 + if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) { 993 + printk(KERN_ERR 994 + "RIO: error adding inbound buffer %d, buffer exists\n", 995 + rmu->msg_rx_ring.rx_slot); 996 + rc = -EINVAL; 997 + goto out; 998 + } 999 + 1000 + rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf; 1001 + if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size) 1002 + rmu->msg_rx_ring.rx_slot = 0; 1003 + 1004 + out: 1005 + return rc; 1006 + } 1007 + 1008 + /** 1009 + * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit 1010 + * @mport: Master port implementing the inbound message unit 1011 + * @mbox: Inbound mailbox number 1012 + * 1013 + * Gets the next available inbound message from the inbound message queue. 1014 + * A pointer to the message is returned on success or NULL on failure. 1015 + */ 1016 + static void *fsl_get_inb_message(struct rio_mport *mport, int mbox) 1017 + { 1018 + struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 1019 + u32 phys_buf, virt_buf; 1020 + void *buf = NULL; 1021 + int buf_idx; 1022 + 1023 + phys_buf = in_be32(&rmu->msg_regs->ifqdpar); 1024 + 1025 + /* If no more messages, then bail out */ 1026 + if (phys_buf == in_be32(&rmu->msg_regs->ifqepar)) 1027 + goto out2; 1028 + 1029 + virt_buf = (u32) rmu->msg_rx_ring.virt + (phys_buf 1030 + - rmu->msg_rx_ring.phys); 1031 + buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; 1032 + buf = rmu->msg_rx_ring.virt_buffer[buf_idx]; 1033 + 1034 + if (!buf) { 1035 + printk(KERN_ERR 1036 + "RIO: inbound message copy failed, no buffers\n"); 1037 + goto out1; 1038 + } 1039 + 1040 + /* Copy max message size, caller is expected to allocate that big */ 1041 + memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); 1042 + 1043 + /* Clear the available buffer */ 1044 + rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL; 1045 + 1046 + out1: 1047 + setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); 1048 + 1049 + out2: 1050 + return buf; 1051 + } 1052 + 1053 + /** 1054 + * fsl_rio_doorbell_init - MPC85xx doorbell interface init 1055 + * @mport: Master port implementing the inbound doorbell unit 1056 + * 1057 + * Initializes doorbell unit hardware and inbound DMA buffer 1058 + * ring. Called from fsl_rio_setup(). Returns %0 on success 1059 + * or %-ENOMEM on failure. 1060 + */ 1061 + static int fsl_rio_doorbell_init(struct rio_mport *mport) 1062 + { 1063 + struct rio_priv *priv = mport->priv; 1064 + struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 1065 + int rc = 0; 1066 + 1067 + /* Map outbound doorbell window immediately after maintenance window */ 1068 + rmu->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE, 1069 + RIO_DBELL_WIN_SIZE); 1070 + if (!rmu->dbell_win) { 1071 + printk(KERN_ERR 1072 + "RIO: unable to map outbound doorbell window\n"); 1073 + rc = -ENOMEM; 1074 + goto out; 1075 + } 1076 + 1077 + /* Initialize inbound doorbells */ 1078 + rmu->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 * 1079 + DOORBELL_MESSAGE_SIZE, &rmu->dbell_ring.phys, GFP_KERNEL); 1080 + if (!rmu->dbell_ring.virt) { 1081 + printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); 1082 + rc = -ENOMEM; 1083 + iounmap(rmu->dbell_win); 1084 + goto out; 1085 + } 1086 + 1087 + /* Point dequeue/enqueue pointers at first entry in ring */ 1088 + out_be32(&rmu->msg_regs->dqdpar, (u32) rmu->dbell_ring.phys); 1089 + out_be32(&rmu->msg_regs->dqepar, (u32) rmu->dbell_ring.phys); 1090 + 1091 + /* Clear interrupt status */ 1092 + out_be32(&rmu->msg_regs->dsr, 0x00000091); 1093 + 1094 + /* Hook up doorbell handler */ 1095 + rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0, 1096 + "dbell_rx", (void *)mport); 1097 + if (rc < 0) { 1098 + iounmap(rmu->dbell_win); 1099 + dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE, 1100 + rmu->dbell_ring.virt, rmu->dbell_ring.phys); 1101 + printk(KERN_ERR 1102 + "MPC85xx RIO: unable to request inbound doorbell irq"); 1103 + goto out; 1104 + } 1105 + 1106 + /* Configure doorbells for snooping, 512 entries, and enable */ 1107 + out_be32(&rmu->msg_regs->dmr, 0x00108161); 1108 + 1109 + out: 1110 + return rc; 1111 + } 1112 + 1113 + int fsl_rio_setup_rmu(struct rio_mport *mport, struct device_node *node) 1114 + { 1115 + struct rio_priv *priv; 1116 + struct fsl_rmu *rmu; 1117 + struct rio_ops *ops; 1118 + 1119 + if (!mport || !mport->priv || !node) 1120 + return -1; 1121 + 1122 + rmu = kzalloc(sizeof(struct fsl_rmu), GFP_KERNEL); 1123 + if (!rmu) 1124 + return -ENOMEM; 1125 + 1126 + priv = mport->priv; 1127 + priv->rmm_handle = rmu; 1128 + rmu->dbell_atmu_regs = priv->atmu_regs + 2; 1129 + rmu->msg_regs = (struct rio_msg_regs *)(priv->regs_win + 1130 + ((mport->phy_type == RIO_PHY_SERIAL) ? 1131 + RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET)); 1132 + 1133 + rmu->bellirq = irq_of_parse_and_map(node, 2); 1134 + rmu->txirq = irq_of_parse_and_map(node, 3); 1135 + rmu->rxirq = irq_of_parse_and_map(node, 4); 1136 + dev_info(priv->dev, "bellirq: %d, txirq: %d, rxirq %d\n", 1137 + rmu->bellirq, rmu->txirq, rmu->rxirq); 1138 + 1139 + ops = mport->ops; 1140 + 1141 + ops->dsend = fsl_rio_doorbell_send; 1142 + ops->open_outb_mbox = fsl_open_outb_mbox; 1143 + ops->open_inb_mbox = fsl_open_inb_mbox; 1144 + ops->close_outb_mbox = fsl_close_outb_mbox; 1145 + ops->close_inb_mbox = fsl_close_inb_mbox; 1146 + ops->add_outb_message = fsl_add_outb_message; 1147 + ops->add_inb_buffer = fsl_add_inb_buffer; 1148 + ops->get_inb_message = fsl_get_inb_message; 1149 + 1150 + rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 1151 + rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0); 1152 + rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); 1153 + 1154 + /* Configure outbound doorbell window */ 1155 + out_be32(&rmu->dbell_atmu_regs->rowbar, 1156 + (mport->iores.start + RIO_MAINT_WIN_SIZE) >> 12); 1157 + /* 4k window size */ 1158 + out_be32(&rmu->dbell_atmu_regs->rowar, 0x8004200b); 1159 + 1160 + fsl_rio_doorbell_init(mport); 1161 + 1162 + return 0; 1163 + }