···731731config SPARSE_IRQ732732 def_bool y733733 depends on SUPERH32 && !SH_DREAMCAST && !SH_HIGHLANDER && \734734- !SH_RTS7751R2D && !HD64461734734+ !SH_RTS7751R2D735735 help736736 This enables support for sparse irqs. This is useful in general737737 as most CPUs have a fairly sparse array of IRQ vectors, which
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arch/sh/cchips/hd6446x/hd64461.c
···73737474int __init setup_hd64461(void)7575{7676- int i;7676+ int i, nid = cpu_to_node(boot_cpu_data);77777878 if (!MACH_HD64461)7979 return 0;···9090 __raw_writew(0xffff, HD64461_NIMR);91919292 /* IRQ 80 -> 95 belongs to HD64461 */9393- for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++)9393+ for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) {9494+ unsigned int irq;9595+9696+ irq = create_irq_nr(i, nid);9797+ if (unlikely(irq == 0)) {9898+ pr_err("%s: failed hooking irq %d for HD64461\n",9999+ __func__, i);100100+ return -EBUSY;101101+ }102102+103103+ if (unlikely(irq != i)) {104104+ pr_err("%s: got irq %d but wanted %d, bailing.\n",105105+ __func__, irq, i);106106+ destroy_irq(irq);107107+ return -EINVAL;108108+ }109109+94110 set_irq_chip_and_handler(i, &hd64461_irq_chip,95111 handle_level_irq);112112+ }9611397114 set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);98115 set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);