commit 6e5a32754c67f0d156c2f196d604b2e9129a1fd5 · tjh.dev/kernel

+1 -1

arch/sparc64/kernel/auxio.c

··· 16 16 #include <asm/ebus.h> 17 17 #include <asm/auxio.h> 18 18 19 - /* This cannot be static, as it is referenced in entry.S */ 19 + /* This cannot be static, as it is referenced in irq.c */ 20 20 void __iomem *auxio_register = NULL; 21 21 22 22 enum auxio_type {

+4 -112

arch/sparc64/kernel/entry.S

··· 271 271 fmuld %f0, %f2, %f26 272 272 faddd %f0, %f2, %f28 273 273 fmuld %f0, %f2, %f30 274 + membar #Sync 274 275 b,pt %xcc, fpdis_exit 275 - membar #Sync 276 + nop 276 277 2: andcc %g5, FPRS_DU, %g0 277 278 bne,pt %icc, 3f 278 279 fzero %f32 ··· 302 301 fmuld %f32, %f34, %f58 303 302 faddd %f32, %f34, %f60 304 303 fmuld %f32, %f34, %f62 304 + membar #Sync 305 305 ba,pt %xcc, fpdis_exit 306 - membar #Sync 306 + nop 307 307 3: mov SECONDARY_CONTEXT, %g3 308 308 add %g6, TI_FPREGS, %g1 309 309 ldxa [%g3] ASI_DMMU, %g5 ··· 700 698 add %sp, PTREGS_OFF, %o0 701 699 ba,pt %xcc, rtrap 702 700 clr %l6 703 - 704 - #ifdef CONFIG_BLK_DEV_FD 705 - .globl floppy_hardint 706 - floppy_hardint: 707 - wr %g0, (1 << 11), %clear_softint 708 - sethi %hi(doing_pdma), %g1 709 - ld [%g1 + %lo(doing_pdma)], %g2 710 - brz,pn %g2, floppy_dosoftint 711 - sethi %hi(fdc_status), %g3 712 - ldx [%g3 + %lo(fdc_status)], %g3 713 - sethi %hi(pdma_vaddr), %g5 714 - ldx [%g5 + %lo(pdma_vaddr)], %g4 715 - sethi %hi(pdma_size), %g5 716 - ldx [%g5 + %lo(pdma_size)], %g5 717 - 718 - next_byte: 719 - lduba [%g3] ASI_PHYS_BYPASS_EC_E, %g7 720 - andcc %g7, 0x80, %g0 721 - be,pn %icc, floppy_fifo_emptied 722 - andcc %g7, 0x20, %g0 723 - be,pn %icc, floppy_overrun 724 - andcc %g7, 0x40, %g0 725 - be,pn %icc, floppy_write 726 - sub %g5, 1, %g5 727 - 728 - inc %g3 729 - lduba [%g3] ASI_PHYS_BYPASS_EC_E, %g7 730 - dec %g3 731 - orcc %g0, %g5, %g0 732 - stb %g7, [%g4] 733 - bne,pn %xcc, next_byte 734 - add %g4, 1, %g4 735 - 736 - b,pt %xcc, floppy_tdone 737 - nop 738 - 739 - floppy_write: 740 - ldub [%g4], %g7 741 - orcc %g0, %g5, %g0 742 - inc %g3 743 - stba %g7, [%g3] ASI_PHYS_BYPASS_EC_E 744 - dec %g3 745 - bne,pn %xcc, next_byte 746 - add %g4, 1, %g4 747 - 748 - floppy_tdone: 749 - sethi %hi(pdma_vaddr), %g1 750 - stx %g4, [%g1 + %lo(pdma_vaddr)] 751 - sethi %hi(pdma_size), %g1 752 - stx %g5, [%g1 + %lo(pdma_size)] 753 - sethi %hi(auxio_register), %g1 754 - ldx [%g1 + %lo(auxio_register)], %g7 755 - lduba [%g7] ASI_PHYS_BYPASS_EC_E, %g5 756 - or %g5, AUXIO_AUX1_FTCNT, %g5 757 - /* andn %g5, AUXIO_AUX1_MASK, %g5 */ 758 - stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E 759 - andn %g5, AUXIO_AUX1_FTCNT, %g5 760 - /* andn %g5, AUXIO_AUX1_MASK, %g5 */ 761 - 762 - nop; nop; nop; nop; nop; nop; 763 - nop; nop; nop; nop; nop; nop; 764 - 765 - stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E 766 - sethi %hi(doing_pdma), %g1 767 - b,pt %xcc, floppy_dosoftint 768 - st %g0, [%g1 + %lo(doing_pdma)] 769 - 770 - floppy_fifo_emptied: 771 - sethi %hi(pdma_vaddr), %g1 772 - stx %g4, [%g1 + %lo(pdma_vaddr)] 773 - sethi %hi(pdma_size), %g1 774 - stx %g5, [%g1 + %lo(pdma_size)] 775 - sethi %hi(irq_action), %g1 776 - or %g1, %lo(irq_action), %g1 777 - ldx [%g1 + (11 << 3)], %g3 ! irqaction[floppy_irq] 778 - ldx [%g3 + 0x08], %g4 ! action->flags>>48==ino 779 - sethi %hi(ivector_table), %g3 780 - srlx %g4, 48, %g4 781 - or %g3, %lo(ivector_table), %g3 782 - sllx %g4, 5, %g4 783 - ldx [%g3 + %g4], %g4 ! &ivector_table[ino] 784 - ldx [%g4 + 0x10], %g4 ! bucket->iclr 785 - stwa %g0, [%g4] ASI_PHYS_BYPASS_EC_E ! ICLR_IDLE 786 - membar #Sync ! probably not needed... 787 - retry 788 - 789 - floppy_overrun: 790 - sethi %hi(pdma_vaddr), %g1 791 - stx %g4, [%g1 + %lo(pdma_vaddr)] 792 - sethi %hi(pdma_size), %g1 793 - stx %g5, [%g1 + %lo(pdma_size)] 794 - sethi %hi(doing_pdma), %g1 795 - st %g0, [%g1 + %lo(doing_pdma)] 796 - 797 - floppy_dosoftint: 798 - rdpr %pil, %g2 799 - wrpr %g0, 15, %pil 800 - sethi %hi(109f), %g7 801 - b,pt %xcc, etrap_irq 802 - 109: or %g7, %lo(109b), %g7 803 - 804 - mov 11, %o0 805 - mov 0, %o1 806 - call sparc_floppy_irq 807 - add %sp, PTREGS_OFF, %o2 808 - 809 - b,pt %xcc, rtrap_irq 810 - nop 811 - 812 - #endif /* CONFIG_BLK_DEV_FD */ 813 701 814 702 /* XXX Here is stuff we still need to write... -DaveM XXX */ 815 703 .globl netbsd_syscall

+50 -121

arch/sparc64/kernel/irq.c

··· 37 37 #include <asm/uaccess.h> 38 38 #include <asm/cache.h> 39 39 #include <asm/cpudata.h> 40 + #include <asm/auxio.h> 40 41 41 42 #ifdef CONFIG_SMP 42 43 static void distribute_irqs(void); ··· 835 834 } 836 835 837 836 #ifdef CONFIG_BLK_DEV_FD 838 - extern void floppy_interrupt(int irq, void *dev_cookie, struct pt_regs *regs); 837 + extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);; 839 838 840 - void sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs) 839 + /* XXX No easy way to include asm/floppy.h XXX */ 840 + extern unsigned char *pdma_vaddr; 841 + extern unsigned long pdma_size; 842 + extern volatile int doing_pdma; 843 + extern unsigned long fdc_status; 844 + 845 + irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs) 841 846 { 842 - struct irqaction *action = *(irq + irq_action); 843 - struct ino_bucket *bucket; 844 - int cpu = smp_processor_id(); 847 + if (likely(doing_pdma)) { 848 + void __iomem *stat = (void __iomem *) fdc_status; 849 + unsigned char *vaddr = pdma_vaddr; 850 + unsigned long size = pdma_size; 851 + u8 val; 845 852 846 - irq_enter(); 847 - kstat_this_cpu.irqs[irq]++; 853 + while (size) { 854 + val = readb(stat); 855 + if (unlikely(!(val & 0x80))) { 856 + pdma_vaddr = vaddr; 857 + pdma_size = size; 858 + return IRQ_HANDLED; 859 + } 860 + if (unlikely(!(val & 0x20))) { 861 + pdma_vaddr = vaddr; 862 + pdma_size = size; 863 + doing_pdma = 0; 864 + goto main_interrupt; 865 + } 866 + if (val & 0x40) { 867 + /* read */ 868 + *vaddr++ = readb(stat + 1); 869 + } else { 870 + unsigned char data = *vaddr++; 848 871 849 - *(irq_work(cpu, irq)) = 0; 850 - bucket = get_ino_in_irqaction(action) + ivector_table; 872 + /* write */ 873 + writeb(data, stat + 1); 874 + } 875 + size--; 876 + } 851 877 852 - bucket->flags |= IBF_INPROGRESS; 878 + pdma_vaddr = vaddr; 879 + pdma_size = size; 853 880 854 - floppy_interrupt(irq, dev_cookie, regs); 855 - upa_writel(ICLR_IDLE, bucket->iclr); 881 + /* Send Terminal Count pulse to floppy controller. */ 882 + val = readb(auxio_register); 883 + val |= AUXIO_AUX1_FTCNT; 884 + writeb(val, auxio_register); 885 + val &= AUXIO_AUX1_FTCNT; 886 + writeb(val, auxio_register); 856 887 857 - bucket->flags &= ~IBF_INPROGRESS; 888 + doing_pdma = 0; 889 + } 858 890 859 - irq_exit(); 891 + main_interrupt: 892 + return floppy_interrupt(irq, dev_cookie, regs); 860 893 } 894 + EXPORT_SYMBOL(sparc_floppy_irq); 861 895 #endif 862 - 863 - /* The following assumes that the branch lies before the place we 864 - * are branching to. This is the case for a trap vector... 865 - * You have been warned. 866 - */ 867 - #define SPARC_BRANCH(dest_addr, inst_addr) \ 868 - (0x10800000 | ((((dest_addr)-(inst_addr))>>2)&0x3fffff)) 869 - 870 - #define SPARC_NOP (0x01000000) 871 - 872 - static void install_fast_irq(unsigned int cpu_irq, 873 - irqreturn_t (*handler)(int, void *, struct pt_regs *)) 874 - { 875 - extern unsigned long sparc64_ttable_tl0; 876 - unsigned long ttent = (unsigned long) &sparc64_ttable_tl0; 877 - unsigned int *insns; 878 - 879 - ttent += 0x820; 880 - ttent += (cpu_irq - 1) << 5; 881 - insns = (unsigned int *) ttent; 882 - insns[0] = SPARC_BRANCH(((unsigned long) handler), 883 - ((unsigned long)&insns[0])); 884 - insns[1] = SPARC_NOP; 885 - __asm__ __volatile__("membar #StoreStore; flush %0" : : "r" (ttent)); 886 - } 887 - 888 - int request_fast_irq(unsigned int irq, 889 - irqreturn_t (*handler)(int, void *, struct pt_regs *), 890 - unsigned long irqflags, const char *name, void *dev_id) 891 - { 892 - struct irqaction *action; 893 - struct ino_bucket *bucket = __bucket(irq); 894 - unsigned long flags; 895 - 896 - /* No pil0 dummy buckets allowed here. */ 897 - if (bucket < &ivector_table[0] || 898 - bucket >= &ivector_table[NUM_IVECS]) { 899 - unsigned int *caller; 900 - 901 - __asm__ __volatile__("mov %%i7, %0" : "=r" (caller)); 902 - printk(KERN_CRIT "request_fast_irq: Old style IRQ registry attempt " 903 - "from %p, irq %08x.\n", caller, irq); 904 - return -EINVAL; 905 - } 906 - 907 - if (!handler) 908 - return -EINVAL; 909 - 910 - if ((bucket->pil == 0) || (bucket->pil == 14)) { 911 - printk("request_fast_irq: Trying to register shared IRQ 0 or 14.\n"); 912 - return -EBUSY; 913 - } 914 - 915 - spin_lock_irqsave(&irq_action_lock, flags); 916 - 917 - action = *(bucket->pil + irq_action); 918 - if (action) { 919 - if (action->flags & SA_SHIRQ) 920 - panic("Trying to register fast irq when already shared.\n"); 921 - if (irqflags & SA_SHIRQ) 922 - panic("Trying to register fast irq as shared.\n"); 923 - printk("request_fast_irq: Trying to register yet already owned.\n"); 924 - spin_unlock_irqrestore(&irq_action_lock, flags); 925 - return -EBUSY; 926 - } 927 - 928 - /* 929 - * We do not check for SA_SAMPLE_RANDOM in this path. Neither do we 930 - * support smp intr affinity in this path. 931 - */ 932 - if (irqflags & SA_STATIC_ALLOC) { 933 - if (static_irq_count < MAX_STATIC_ALLOC) 934 - action = &static_irqaction[static_irq_count++]; 935 - else 936 - printk("Request for IRQ%d (%s) SA_STATIC_ALLOC failed " 937 - "using kmalloc\n", bucket->pil, name); 938 - } 939 - if (action == NULL) 940 - action = (struct irqaction *)kmalloc(sizeof(struct irqaction), 941 - GFP_ATOMIC); 942 - if (!action) { 943 - spin_unlock_irqrestore(&irq_action_lock, flags); 944 - return -ENOMEM; 945 - } 946 - install_fast_irq(bucket->pil, handler); 947 - 948 - bucket->irq_info = action; 949 - bucket->flags |= IBF_ACTIVE; 950 - 951 - action->handler = handler; 952 - action->flags = irqflags; 953 - action->dev_id = NULL; 954 - action->name = name; 955 - action->next = NULL; 956 - put_ino_in_irqaction(action, irq); 957 - put_smpaff_in_irqaction(action, CPU_MASK_NONE); 958 - 959 - *(bucket->pil + irq_action) = action; 960 - enable_irq(irq); 961 - 962 - spin_unlock_irqrestore(&irq_action_lock, flags); 963 - 964 - #ifdef CONFIG_SMP 965 - distribute_irqs(); 966 - #endif 967 - return 0; 968 - } 969 896 970 897 /* We really don't need these at all on the Sparc. We only have 971 898 * stubs here because they are exported to modules.

+8 -4

arch/sparc64/kernel/semaphore.c

··· 32 32 " add %1, %4, %1\n" 33 33 " cas [%3], %0, %1\n" 34 34 " cmp %0, %1\n" 35 + " membar #StoreLoad | #StoreStore\n" 35 36 " bne,pn %%icc, 1b\n" 36 - " membar #StoreLoad | #StoreStore\n" 37 + " nop\n" 37 38 : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) 38 39 : "r" (&sem->count), "r" (incr), "m" (sem->count) 39 40 : "cc"); ··· 72 71 " cmp %%g1, %%g7\n" 73 72 " bne,pn %%icc, 1b\n" 74 73 " addcc %%g7, 1, %%g0\n" 74 + " membar #StoreLoad | #StoreStore\n" 75 75 " ble,pn %%icc, 3f\n" 76 - " membar #StoreLoad | #StoreStore\n" 76 + " nop\n" 77 77 "2:\n" 78 78 " .subsection 2\n" 79 79 "3: mov %0, %%g1\n" ··· 130 128 " cmp %%g1, %%g7\n" 131 129 " bne,pn %%icc, 1b\n" 132 130 " cmp %%g7, 1\n" 131 + " membar #StoreLoad | #StoreStore\n" 133 132 " bl,pn %%icc, 3f\n" 134 - " membar #StoreLoad | #StoreStore\n" 133 + " nop\n" 135 134 "2:\n" 136 135 " .subsection 2\n" 137 136 "3: mov %0, %%g1\n" ··· 236 233 " cmp %%g1, %%g7\n" 237 234 " bne,pn %%icc, 1b\n" 238 235 " cmp %%g7, 1\n" 236 + " membar #StoreLoad | #StoreStore\n" 239 237 " bl,pn %%icc, 3f\n" 240 - " membar #StoreLoad | #StoreStore\n" 238 + " nop\n" 241 239 "2:\n" 242 240 " .subsection 2\n" 243 241 "3: mov %2, %%g1\n"

-1

arch/sparc64/kernel/sparc64_ksyms.c

··· 227 227 228 228 EXPORT_SYMBOL(mostek_lock); 229 229 EXPORT_SYMBOL(mstk48t02_regs); 230 - EXPORT_SYMBOL(request_fast_irq); 231 230 #ifdef CONFIG_SUN_AUXIO 232 231 EXPORT_SYMBOL(auxio_set_led); 233 232 EXPORT_SYMBOL(auxio_set_lte);

+2 -1

arch/sparc64/kernel/trampoline.S

··· 98 98 99 99 sethi %hi(prom_entry_lock), %g2 100 100 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1 101 + membar #StoreLoad | #StoreStore 101 102 brnz,pn %g1, 1b 102 - membar #StoreLoad | #StoreStore 103 + nop 103 104 104 105 sethi %hi(p1275buf), %g2 105 106 or %g2, %lo(p1275buf), %g2

+53 -50

arch/sparc64/lib/U1memcpy.S

··· 87 87 #define LOOP_CHUNK3(src, dest, len, branch_dest) \ 88 88 MAIN_LOOP_CHUNK(src, dest, f32, f48, len, branch_dest) 89 89 90 + #define DO_SYNC membar #Sync; 90 91 #define STORE_SYNC(dest, fsrc) \ 91 92 EX_ST(STORE_BLK(%fsrc, %dest)); \ 92 - add %dest, 0x40, %dest; 93 + add %dest, 0x40, %dest; \ 94 + DO_SYNC 93 95 94 96 #define STORE_JUMP(dest, fsrc, target) \ 95 97 EX_ST(STORE_BLK(%fsrc, %dest)); \ 96 98 add %dest, 0x40, %dest; \ 97 - ba,pt %xcc, target; 99 + ba,pt %xcc, target; \ 100 + nop; 98 101 99 102 #define FINISH_VISCHUNK(dest, f0, f1, left) \ 100 103 subcc %left, 8, %left;\ ··· 242 239 ba,pt %xcc, 1b+4 243 240 faligndata %f0, %f2, %f48 244 241 1: FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32) 245 - STORE_SYNC(o0, f48) membar #Sync 242 + STORE_SYNC(o0, f48) 246 243 FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0) 247 - STORE_JUMP(o0, f48, 40f) membar #Sync 244 + STORE_JUMP(o0, f48, 40f) 248 245 2: FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0) 249 - STORE_SYNC(o0, f48) membar #Sync 246 + STORE_SYNC(o0, f48) 250 247 FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16) 251 - STORE_JUMP(o0, f48, 48f) membar #Sync 248 + STORE_JUMP(o0, f48, 48f) 252 249 3: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16) 253 - STORE_SYNC(o0, f48) membar #Sync 250 + STORE_SYNC(o0, f48) 254 251 FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32) 255 - STORE_JUMP(o0, f48, 56f) membar #Sync 252 + STORE_JUMP(o0, f48, 56f) 256 253 257 254 1: FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18) 258 255 LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) ··· 263 260 ba,pt %xcc, 1b+4 264 261 faligndata %f2, %f4, %f48 265 262 1: FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34) 266 - STORE_SYNC(o0, f48) membar #Sync 263 + STORE_SYNC(o0, f48) 267 264 FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2) 268 - STORE_JUMP(o0, f48, 41f) membar #Sync 265 + STORE_JUMP(o0, f48, 41f) 269 266 2: FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2) 270 - STORE_SYNC(o0, f48) membar #Sync 267 + STORE_SYNC(o0, f48) 271 268 FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18) 272 - STORE_JUMP(o0, f48, 49f) membar #Sync 269 + STORE_JUMP(o0, f48, 49f) 273 270 3: FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18) 274 - STORE_SYNC(o0, f48) membar #Sync 271 + STORE_SYNC(o0, f48) 275 272 FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34) 276 - STORE_JUMP(o0, f48, 57f) membar #Sync 273 + STORE_JUMP(o0, f48, 57f) 277 274 278 275 1: FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20) 279 276 LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) ··· 284 281 ba,pt %xcc, 1b+4 285 282 faligndata %f4, %f6, %f48 286 283 1: FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36) 287 - STORE_SYNC(o0, f48) membar #Sync 284 + STORE_SYNC(o0, f48) 288 285 FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4) 289 - STORE_JUMP(o0, f48, 42f) membar #Sync 286 + STORE_JUMP(o0, f48, 42f) 290 287 2: FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4) 291 - STORE_SYNC(o0, f48) membar #Sync 288 + STORE_SYNC(o0, f48) 292 289 FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20) 293 - STORE_JUMP(o0, f48, 50f) membar #Sync 290 + STORE_JUMP(o0, f48, 50f) 294 291 3: FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20) 295 - STORE_SYNC(o0, f48) membar #Sync 292 + STORE_SYNC(o0, f48) 296 293 FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36) 297 - STORE_JUMP(o0, f48, 58f) membar #Sync 294 + STORE_JUMP(o0, f48, 58f) 298 295 299 296 1: FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22) 300 297 LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) ··· 305 302 ba,pt %xcc, 1b+4 306 303 faligndata %f6, %f8, %f48 307 304 1: FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38) 308 - STORE_SYNC(o0, f48) membar #Sync 305 + STORE_SYNC(o0, f48) 309 306 FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6) 310 - STORE_JUMP(o0, f48, 43f) membar #Sync 307 + STORE_JUMP(o0, f48, 43f) 311 308 2: FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6) 312 - STORE_SYNC(o0, f48) membar #Sync 309 + STORE_SYNC(o0, f48) 313 310 FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22) 314 - STORE_JUMP(o0, f48, 51f) membar #Sync 311 + STORE_JUMP(o0, f48, 51f) 315 312 3: FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22) 316 - STORE_SYNC(o0, f48) membar #Sync 313 + STORE_SYNC(o0, f48) 317 314 FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38) 318 - STORE_JUMP(o0, f48, 59f) membar #Sync 315 + STORE_JUMP(o0, f48, 59f) 319 316 320 317 1: FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24) 321 318 LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) ··· 326 323 ba,pt %xcc, 1b+4 327 324 faligndata %f8, %f10, %f48 328 325 1: FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40) 329 - STORE_SYNC(o0, f48) membar #Sync 326 + STORE_SYNC(o0, f48) 330 327 FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8) 331 - STORE_JUMP(o0, f48, 44f) membar #Sync 328 + STORE_JUMP(o0, f48, 44f) 332 329 2: FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8) 333 - STORE_SYNC(o0, f48) membar #Sync 330 + STORE_SYNC(o0, f48) 334 331 FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24) 335 - STORE_JUMP(o0, f48, 52f) membar #Sync 332 + STORE_JUMP(o0, f48, 52f) 336 333 3: FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24) 337 - STORE_SYNC(o0, f48) membar #Sync 334 + STORE_SYNC(o0, f48) 338 335 FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40) 339 - STORE_JUMP(o0, f48, 60f) membar #Sync 336 + STORE_JUMP(o0, f48, 60f) 340 337 341 338 1: FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26) 342 339 LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) ··· 347 344 ba,pt %xcc, 1b+4 348 345 faligndata %f10, %f12, %f48 349 346 1: FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42) 350 - STORE_SYNC(o0, f48) membar #Sync 347 + STORE_SYNC(o0, f48) 351 348 FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10) 352 - STORE_JUMP(o0, f48, 45f) membar #Sync 349 + STORE_JUMP(o0, f48, 45f) 353 350 2: FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10) 354 - STORE_SYNC(o0, f48) membar #Sync 351 + STORE_SYNC(o0, f48) 355 352 FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26) 356 - STORE_JUMP(o0, f48, 53f) membar #Sync 353 + STORE_JUMP(o0, f48, 53f) 357 354 3: FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26) 358 - STORE_SYNC(o0, f48) membar #Sync 355 + STORE_SYNC(o0, f48) 359 356 FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42) 360 - STORE_JUMP(o0, f48, 61f) membar #Sync 357 + STORE_JUMP(o0, f48, 61f) 361 358 362 359 1: FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28) 363 360 LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) ··· 368 365 ba,pt %xcc, 1b+4 369 366 faligndata %f12, %f14, %f48 370 367 1: FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44) 371 - STORE_SYNC(o0, f48) membar #Sync 368 + STORE_SYNC(o0, f48) 372 369 FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12) 373 - STORE_JUMP(o0, f48, 46f) membar #Sync 370 + STORE_JUMP(o0, f48, 46f) 374 371 2: FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12) 375 - STORE_SYNC(o0, f48) membar #Sync 372 + STORE_SYNC(o0, f48) 376 373 FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28) 377 - STORE_JUMP(o0, f48, 54f) membar #Sync 374 + STORE_JUMP(o0, f48, 54f) 378 375 3: FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28) 379 - STORE_SYNC(o0, f48) membar #Sync 376 + STORE_SYNC(o0, f48) 380 377 FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44) 381 - STORE_JUMP(o0, f48, 62f) membar #Sync 378 + STORE_JUMP(o0, f48, 62f) 382 379 383 380 1: FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30) 384 381 LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) ··· 389 386 ba,pt %xcc, 1b+4 390 387 faligndata %f14, %f16, %f48 391 388 1: FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46) 392 - STORE_SYNC(o0, f48) membar #Sync 389 + STORE_SYNC(o0, f48) 393 390 FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14) 394 - STORE_JUMP(o0, f48, 47f) membar #Sync 391 + STORE_JUMP(o0, f48, 47f) 395 392 2: FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14) 396 - STORE_SYNC(o0, f48) membar #Sync 393 + STORE_SYNC(o0, f48) 397 394 FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30) 398 - STORE_JUMP(o0, f48, 55f) membar #Sync 395 + STORE_JUMP(o0, f48, 55f) 399 396 3: FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30) 400 - STORE_SYNC(o0, f48) membar #Sync 397 + STORE_SYNC(o0, f48) 401 398 FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46) 402 - STORE_JUMP(o0, f48, 63f) membar #Sync 399 + STORE_JUMP(o0, f48, 63f) 403 400 404 401 40: FINISH_VISCHUNK(o0, f0, f2, g3) 405 402 41: FINISH_VISCHUNK(o0, f2, f4, g3)

+13 -2

arch/sparc64/lib/VISsave.S

··· 72 72 73 73 stda %f48, [%g3 + %g1] ASI_BLK_P 74 74 5: membar #Sync 75 - jmpl %g7 + %g0, %g0 75 + ba,pt %xcc, 80f 76 + nop 77 + 78 + .align 32 79 + 80: jmpl %g7 + %g0, %g0 76 80 nop 77 81 78 82 6: ldub [%g3 + TI_FPSAVED], %o5 ··· 91 87 stda %f32, [%g2 + %g1] ASI_BLK_P 92 88 stda %f48, [%g3 + %g1] ASI_BLK_P 93 89 membar #Sync 94 - jmpl %g7 + %g0, %g0 90 + ba,pt %xcc, 80f 91 + nop 95 92 93 + .align 32 94 + 80: jmpl %g7 + %g0, %g0 96 95 nop 97 96 98 97 .align 32 ··· 133 126 stda %f0, [%g2 + %g1] ASI_BLK_P 134 127 stda %f16, [%g3 + %g1] ASI_BLK_P 135 128 membar #Sync 129 + ba,pt %xcc, 4f 130 + nop 131 + 132 + .align 32 136 133 4: and %o5, FPRS_DU, %o5 137 134 jmpl %g7 + %g0, %g0 138 135 wr %o5, FPRS_FEF, %fprs

+26 -16

arch/sparc64/lib/atomic.S

··· 7 7 #include <linux/config.h> 8 8 #include <asm/asi.h> 9 9 10 - /* On SMP we need to use memory barriers to ensure 11 - * correct memory operation ordering, nop these out 12 - * for uniprocessor. 13 - */ 14 - #ifdef CONFIG_SMP 15 - #define ATOMIC_PRE_BARRIER membar #StoreLoad | #LoadLoad 16 - #define ATOMIC_POST_BARRIER membar #StoreLoad | #StoreStore 17 - #else 18 - #define ATOMIC_PRE_BARRIER nop 19 - #define ATOMIC_POST_BARRIER nop 20 - #endif 21 - 22 10 .text 23 11 24 12 /* Two versions of the atomic routines, one that ··· 40 52 nop 41 53 .size atomic_sub, .-atomic_sub 42 54 55 + /* On SMP we need to use memory barriers to ensure 56 + * correct memory operation ordering, nop these out 57 + * for uniprocessor. 58 + */ 59 + #ifdef CONFIG_SMP 60 + 61 + #define ATOMIC_PRE_BARRIER membar #StoreLoad | #LoadLoad; 62 + #define ATOMIC_POST_BARRIER \ 63 + ba,pt %xcc, 80b; \ 64 + membar #StoreLoad | #StoreStore 65 + 66 + 80: retl 67 + nop 68 + #else 69 + #define ATOMIC_PRE_BARRIER 70 + #define ATOMIC_POST_BARRIER 71 + #endif 72 + 43 73 .globl atomic_add_ret 44 74 .type atomic_add_ret,#function 45 75 atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ ··· 68 62 cmp %g1, %g7 69 63 bne,pn %icc, 1b 70 64 add %g7, %o0, %g7 65 + sra %g7, 0, %o0 71 66 ATOMIC_POST_BARRIER 72 67 retl 73 - sra %g7, 0, %o0 68 + nop 74 69 .size atomic_add_ret, .-atomic_add_ret 75 70 76 71 .globl atomic_sub_ret ··· 84 77 cmp %g1, %g7 85 78 bne,pn %icc, 1b 86 79 sub %g7, %o0, %g7 80 + sra %g7, 0, %o0 87 81 ATOMIC_POST_BARRIER 88 82 retl 89 - sra %g7, 0, %o0 83 + nop 90 84 .size atomic_sub_ret, .-atomic_sub_ret 91 85 92 86 .globl atomic64_add ··· 126 118 cmp %g1, %g7 127 119 bne,pn %xcc, 1b 128 120 add %g7, %o0, %g7 121 + mov %g7, %o0 129 122 ATOMIC_POST_BARRIER 130 123 retl 131 - mov %g7, %o0 124 + nop 132 125 .size atomic64_add_ret, .-atomic64_add_ret 133 126 134 127 .globl atomic64_sub_ret ··· 142 133 cmp %g1, %g7 143 134 bne,pn %xcc, 1b 144 135 sub %g7, %o0, %g7 136 + mov %g7, %o0 145 137 ATOMIC_POST_BARRIER 146 138 retl 147 - mov %g7, %o0 139 + nop 148 140 .size atomic64_sub_ret, .-atomic64_sub_ret

+21 -12

arch/sparc64/lib/bitops.S

··· 7 7 #include <linux/config.h> 8 8 #include <asm/asi.h> 9 9 10 + .text 11 + 10 12 /* On SMP we need to use memory barriers to ensure 11 13 * correct memory operation ordering, nop these out 12 14 * for uniprocessor. 13 15 */ 16 + 14 17 #ifdef CONFIG_SMP 15 18 #define BITOP_PRE_BARRIER membar #StoreLoad | #LoadLoad 16 - #define BITOP_POST_BARRIER membar #StoreLoad | #StoreStore 17 - #else 18 - #define BITOP_PRE_BARRIER nop 19 - #define BITOP_POST_BARRIER nop 20 - #endif 19 + #define BITOP_POST_BARRIER \ 20 + ba,pt %xcc, 80b; \ 21 + membar #StoreLoad | #StoreStore 21 22 22 - .text 23 + 80: retl 24 + nop 25 + #else 26 + #define BITOP_PRE_BARRIER 27 + #define BITOP_POST_BARRIER 28 + #endif 23 29 24 30 .globl test_and_set_bit 25 31 .type test_and_set_bit,#function ··· 43 37 cmp %g7, %g1 44 38 bne,pn %xcc, 1b 45 39 and %g7, %o2, %g2 46 - BITOP_POST_BARRIER 47 40 clr %o0 41 + movrne %g2, 1, %o0 42 + BITOP_POST_BARRIER 48 43 retl 49 - movrne %g2, 1, %o0 44 + nop 50 45 .size test_and_set_bit, .-test_and_set_bit 51 46 52 47 .globl test_and_clear_bit ··· 66 59 cmp %g7, %g1 67 60 bne,pn %xcc, 1b 68 61 and %g7, %o2, %g2 69 - BITOP_POST_BARRIER 70 62 clr %o0 63 + movrne %g2, 1, %o0 64 + BITOP_POST_BARRIER 71 65 retl 72 - movrne %g2, 1, %o0 66 + nop 73 67 .size test_and_clear_bit, .-test_and_clear_bit 74 68 75 69 .globl test_and_change_bit ··· 89 81 cmp %g7, %g1 90 82 bne,pn %xcc, 1b 91 83 and %g7, %o2, %g2 92 - BITOP_POST_BARRIER 93 84 clr %o0 85 + movrne %g2, 1, %o0 86 + BITOP_POST_BARRIER 94 87 retl 95 - movrne %g2, 1, %o0 88 + nop 96 89 .size test_and_change_bit, .-test_and_change_bit 97 90 98 91 .globl set_bit

+4 -2

arch/sparc64/lib/debuglocks.c

··· 252 252 " andn %%g1, %%g3, %%g7\n" 253 253 " casx [%0], %%g1, %%g7\n" 254 254 " cmp %%g1, %%g7\n" 255 + " membar #StoreLoad | #StoreStore\n" 255 256 " bne,pn %%xcc, 1b\n" 256 - " membar #StoreLoad | #StoreStore" 257 + " nop" 257 258 : /* no outputs */ 258 259 : "r" (&(rw->lock)) 259 260 : "g3", "g1", "g7", "cc", "memory"); ··· 352 351 " andn %%g1, %%g3, %%g7\n" 353 352 " casx [%0], %%g1, %%g7\n" 354 353 " cmp %%g1, %%g7\n" 354 + " membar #StoreLoad | #StoreStore\n" 355 355 " bne,pn %%xcc, 1b\n" 356 - " membar #StoreLoad | #StoreStore" 356 + " nop" 357 357 : /* no outputs */ 358 358 : "r" (&(rw->lock)) 359 359 : "g3", "g1", "g7", "cc", "memory");

+4 -2

arch/sparc64/lib/dec_and_lock.S

··· 48 48 #endif 49 49 to_zero: 50 50 ldstub [%o1], %g3 51 + membar #StoreLoad | #StoreStore 51 52 brnz,pn %g3, spin_on_lock 52 - membar #StoreLoad | #StoreStore 53 + nop 53 54 loop2: cas [%o0], %g2, %g7 /* ASSERT(g7 == 0) */ 54 55 cmp %g2, %g7 55 56 ··· 72 71 nop 73 72 spin_on_lock: 74 73 ldub [%o1], %g3 74 + membar #LoadLoad 75 75 brnz,pt %g3, spin_on_lock 76 - membar #LoadLoad 76 + nop 77 77 ba,pt %xcc, to_zero 78 78 nop 79 79 nop

+10 -5

arch/sparc64/lib/rwsem.S

··· 17 17 bne,pn %icc, 1b 18 18 add %g7, 1, %g7 19 19 cmp %g7, 0 20 + membar #StoreLoad | #StoreStore 20 21 bl,pn %icc, 3f 21 - membar #StoreLoad | #StoreStore 22 + nop 22 23 2: 23 24 retl 24 25 nop ··· 58 57 cmp %g3, %g7 59 58 bne,pn %icc, 1b 60 59 cmp %g7, 0 60 + membar #StoreLoad | #StoreStore 61 61 bne,pn %icc, 3f 62 - membar #StoreLoad | #StoreStore 62 + nop 63 63 2: retl 64 64 nop 65 65 3: ··· 99 97 cmp %g1, %g7 100 98 bne,pn %icc, 1b 101 99 cmp %g7, 0 100 + membar #StoreLoad | #StoreStore 102 101 bl,pn %icc, 3f 103 - membar #StoreLoad | #StoreStore 102 + nop 104 103 2: retl 105 104 nop 106 105 3: sethi %hi(RWSEM_ACTIVE_MASK), %g1 ··· 129 126 bne,pn %icc, 1b 130 127 sub %g7, %g1, %g7 131 128 cmp %g7, 0 129 + membar #StoreLoad | #StoreStore 132 130 bl,pn %icc, 3f 133 - membar #StoreLoad | #StoreStore 131 + nop 134 132 2: 135 133 retl 136 134 nop ··· 155 151 bne,pn %icc, 1b 156 152 sub %g7, %g1, %g7 157 153 cmp %g7, 0 154 + membar #StoreLoad | #StoreStore 158 155 bl,pn %icc, 3f 159 - membar #StoreLoad | #StoreStore 156 + nop 160 157 2: 161 158 retl 162 159 nop

+4 -2

arch/sparc64/mm/init.c

··· 136 136 "or %%g1, %0, %%g1\n\t" 137 137 "casx [%2], %%g7, %%g1\n\t" 138 138 "cmp %%g7, %%g1\n\t" 139 + "membar #StoreLoad | #StoreStore\n\t" 139 140 "bne,pn %%xcc, 1b\n\t" 140 - " membar #StoreLoad | #StoreStore" 141 + " nop" 141 142 : /* no outputs */ 142 143 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) 143 144 : "g1", "g7"); ··· 158 157 " andn %%g7, %1, %%g1\n\t" 159 158 "casx [%2], %%g7, %%g1\n\t" 160 159 "cmp %%g7, %%g1\n\t" 160 + "membar #StoreLoad | #StoreStore\n\t" 161 161 "bne,pn %%xcc, 1b\n\t" 162 - " membar #StoreLoad | #StoreStore\n" 162 + " nop\n" 163 163 "2:" 164 164 : /* no outputs */ 165 165 : "r" (cpu), "r" (mask), "r" (&page->flags),

+2 -1

arch/sparc64/mm/ultra.S

··· 266 266 andn %o3, 1, %o3 267 267 stxa %g0, [%o3] ASI_IMMU_DEMAP 268 268 2: stxa %g0, [%o3] ASI_DMMU_DEMAP 269 + membar #Sync 269 270 brnz,pt %o1, 1b 270 - membar #Sync 271 + nop 271 272 stxa %g2, [%o4] ASI_DMMU 272 273 flush %g6 273 274 wrpr %g0, 0, %tl

+2

include/asm-sparc64/auxio.h

··· 75 75 76 76 #ifndef __ASSEMBLY__ 77 77 78 + extern void __iomem *auxio_register; 79 + 78 80 #define AUXIO_LTE_ON 1 79 81 #define AUXIO_LTE_OFF 0 80 82

+8 -8

include/asm-sparc64/floppy.h

··· 159 159 * underruns. If non-zero, doing_pdma encodes the direction of 160 160 * the transfer for debugging. 1=read 2=write 161 161 */ 162 - char *pdma_vaddr; 162 + unsigned char *pdma_vaddr; 163 163 unsigned long pdma_size; 164 164 volatile int doing_pdma = 0; 165 165 ··· 209 209 pdma_areasize = pdma_size; 210 210 } 211 211 212 - /* Our low-level entry point in arch/sparc/kernel/entry.S */ 213 - extern irqreturn_t floppy_hardint(int irq, void *unused, struct pt_regs *regs); 212 + extern irqreturn_t sparc_floppy_irq(int, void *, struct pt_regs *); 214 213 215 214 static int sun_fd_request_irq(void) 216 215 { ··· 219 220 if(!once) { 220 221 once = 1; 221 222 222 - error = request_fast_irq(FLOPPY_IRQ, floppy_hardint, 223 - SA_INTERRUPT, "floppy", NULL); 223 + error = request_irq(FLOPPY_IRQ, sparc_floppy_irq, 224 + SA_INTERRUPT, "floppy", NULL); 224 225 225 226 return ((error == 0) ? 0 : -1); 226 227 } ··· 614 615 struct linux_ebus *ebus; 615 616 struct linux_ebus_device *edev = NULL; 616 617 unsigned long config = 0; 617 - unsigned long auxio_reg; 618 + void __iomem *auxio_reg; 618 619 619 620 for_each_ebus(ebus) { 620 621 for_each_ebusdev(edev, ebus) { ··· 641 642 /* Make sure the high density bit is set, some systems 642 643 * (most notably Ultra5/Ultra10) come up with it clear. 643 644 */ 644 - auxio_reg = edev->resource[2].start; 645 + auxio_reg = (void __iomem *) edev->resource[2].start; 645 646 writel(readl(auxio_reg)|0x2, auxio_reg); 646 647 647 648 sun_pci_ebus_dev = ebus->self; ··· 649 650 spin_lock_init(&sun_pci_fd_ebus_dma.lock); 650 651 651 652 /* XXX ioremap */ 652 - sun_pci_fd_ebus_dma.regs = edev->resource[1].start; 653 + sun_pci_fd_ebus_dma.regs = (void __iomem *) 654 + edev->resource[1].start; 653 655 if (!sun_pci_fd_ebus_dma.regs) 654 656 return 0; 655 657

+1 -6

include/asm-sparc64/irq.h

··· 19 19 /* You should not mess with this directly. That's the job of irq.c. 20 20 * 21 21 * If you make changes here, please update hand coded assembler of 22 - * SBUS/floppy interrupt handler in entry.S -DaveM 22 + * the vectored interrupt trap handler in entry.S -DaveM 23 23 * 24 24 * This is currently one DCACHE line, two buckets per L2 cache 25 25 * line. Keep this in mind please. ··· 121 121 extern void enable_irq(unsigned int); 122 122 extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap); 123 123 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino); 124 - 125 - extern int request_fast_irq(unsigned int irq, 126 - irqreturn_t (*handler)(int, void *, struct pt_regs *), 127 - unsigned long flags, __const__ char *devname, 128 - void *dev_id); 129 124 130 125 static __inline__ void set_softint(unsigned long bits) 131 126 {

+2 -1

include/asm-sparc64/rwsem.h

··· 55 55 "add %%g1, %1, %%g7\n\t" 56 56 "cas [%2], %%g1, %%g7\n\t" 57 57 "cmp %%g1, %%g7\n\t" 58 + "membar #StoreLoad | #StoreStore\n\t" 58 59 "bne,pn %%icc, 1b\n\t" 59 - " membar #StoreLoad | #StoreStore\n\t" 60 + " nop\n\t" 60 61 "mov %%g7, %0\n\t" 61 62 : "=&r" (tmp) 62 63 : "0" (tmp), "r" (sem)

+19 -10

include/asm-sparc64/spinlock.h

··· 52 52 53 53 __asm__ __volatile__( 54 54 "1: ldstub [%1], %0\n" 55 + " membar #StoreLoad | #StoreStore\n" 55 56 " brnz,pn %0, 2f\n" 56 - " membar #StoreLoad | #StoreStore\n" 57 + " nop\n" 57 58 " .subsection 2\n" 58 59 "2: ldub [%1], %0\n" 60 + " membar #LoadLoad\n" 59 61 " brnz,pt %0, 2b\n" 60 - " membar #LoadLoad\n" 62 + " nop\n" 61 63 " ba,a,pt %%xcc, 1b\n" 62 64 " .previous" 63 65 : "=&r" (tmp) ··· 97 95 98 96 __asm__ __volatile__( 99 97 "1: ldstub [%2], %0\n" 100 - " brnz,pn %0, 2f\n" 101 98 " membar #StoreLoad | #StoreStore\n" 99 + " brnz,pn %0, 2f\n" 100 + " nop\n" 102 101 " .subsection 2\n" 103 102 "2: rdpr %%pil, %1\n" 104 103 " wrpr %3, %%pil\n" 105 104 "3: ldub [%2], %0\n" 106 - " brnz,pt %0, 3b\n" 107 105 " membar #LoadLoad\n" 106 + " brnz,pt %0, 3b\n" 107 + " nop\n" 108 108 " ba,pt %%xcc, 1b\n" 109 - " wrpr %1, %%pil\n" 109 + " wrpr %1, %%pil\n" 110 110 " .previous" 111 111 : "=&r" (tmp1), "=&r" (tmp2) 112 112 : "r"(lock), "r"(flags) ··· 166 162 "4: add %0, 1, %1\n" 167 163 " cas [%2], %0, %1\n" 168 164 " cmp %0, %1\n" 165 + " membar #StoreLoad | #StoreStore\n" 169 166 " bne,pn %%icc, 1b\n" 170 - " membar #StoreLoad | #StoreStore\n" 167 + " nop\n" 171 168 " .subsection 2\n" 172 169 "2: ldsw [%2], %0\n" 170 + " membar #LoadLoad\n" 173 171 " brlz,pt %0, 2b\n" 174 - " membar #LoadLoad\n" 172 + " nop\n" 175 173 " ba,a,pt %%xcc, 4b\n" 176 174 " .previous" 177 175 : "=&r" (tmp1), "=&r" (tmp2) ··· 210 204 "4: or %0, %3, %1\n" 211 205 " cas [%2], %0, %1\n" 212 206 " cmp %0, %1\n" 207 + " membar #StoreLoad | #StoreStore\n" 213 208 " bne,pn %%icc, 1b\n" 214 - " membar #StoreLoad | #StoreStore\n" 209 + " nop\n" 215 210 " .subsection 2\n" 216 211 "2: lduw [%2], %0\n" 212 + " membar #LoadLoad\n" 217 213 " brnz,pt %0, 2b\n" 218 - " membar #LoadLoad\n" 214 + " nop\n" 219 215 " ba,a,pt %%xcc, 4b\n" 220 216 " .previous" 221 217 : "=&r" (tmp1), "=&r" (tmp2) ··· 248 240 " or %0, %4, %1\n" 249 241 " cas [%3], %0, %1\n" 250 242 " cmp %0, %1\n" 243 + " membar #StoreLoad | #StoreStore\n" 251 244 " bne,pn %%icc, 1b\n" 252 - " membar #StoreLoad | #StoreStore\n" 245 + " nop\n" 253 246 " mov 1, %2\n" 254 247 "2:" 255 248 : "=&r" (tmp1), "=&r" (tmp2), "=&r" (result)

-1

include/asm-sparc64/spitfire.h

··· 111 111 "membar #Sync" 112 112 : /* No outputs */ 113 113 : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG)); 114 - __asm__ __volatile__ ("membar #Sync" : : : "memory"); 115 114 } 116 115 117 116 /* The instruction cache lines are flushed with this, but note that