tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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os
linux
Merge tag 'renesas-clock-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into clk-next-shmobile2
Renesas ARM based SoC Clock updates for v3.14
Add support for using emev2 SMU clocks with DT
+203
-1
+98
Documentation/devicetree/bindings/clock/emev2-clock.txt
+98
Documentation/devicetree/bindings/clock/emev2-clock.txt
···
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Device tree Clock bindings for Renesas EMMA Mobile EV2
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This binding uses the common clock binding.
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* SMU
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System Management Unit described in user's manual R19UH0037EJ1000_SMU.
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This is not a clock provider, but clocks under SMU depend on it.
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Required properties:
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- compatible: Should be "renesas,emev2-smu"
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- reg: Address and Size of SMU registers
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* SMU_CLKDIV
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Function block with an input mux and a divider, which corresponds to
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"Serial clock generator" in fig."Clock System Overview" of the manual,
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and "xxx frequency division setting register" (XXXCLKDIV) registers.
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This makes internal (neither input nor output) clock that is provided
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to input of xxxGCLK block.
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Required properties:
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- compatible: Should be "renesas,emev2-smu-clkdiv"
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- reg: Byte offset from SMU base and Bit position in the register
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- clocks: Parent clocks. Input clocks as described in clock-bindings.txt
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- #clock-cells: Should be <0>
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* SMU_GCLK
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Clock gating node shown as "Clock stop processing block" in the
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fig."Clock System Overview" of the manual.
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Registers are "xxx clock gate control register" (XXXGCLKCTRL).
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Required properties:
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- compatible: Should be "renesas,emev2-smu-gclk"
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- reg: Byte offset from SMU base and Bit position in the register
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- clocks: Input clock as described in clock-bindings.txt
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- #clock-cells: Should be <0>
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Example of provider:
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usia_u0_sclkdiv: usia_u0_sclkdiv {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x610 0>;
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clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
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#clock-cells = <0>;
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};
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usia_u0_sclk: usia_u0_sclk {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x4a0 1>;
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clocks = <&usia_u0_sclkdiv>;
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#clock-cells = <0>;
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};
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Example of consumer:
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uart@e1020000 {
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compatible = "renesas,em-uart";
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reg = <0xe1020000 0x38>;
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interrupts = <0 8 0>;
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clocks = <&usia_u0_sclk>;
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clock-names = "sclk";
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};
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Example of clock-tree description:
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This describes a clock path in the clock tree
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c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
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smu@e0110000 {
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compatible = "renesas,emev2-smu";
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reg = <0xe0110000 0x10000>;
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#address-cells = <2>;
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#size-cells = <0>;
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c32ki: c32ki {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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pll3_fo: pll3_fo {
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compatible = "fixed-factor-clock";
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clocks = <&c32ki>;
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clock-div = <1>;
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clock-mult = <7000>;
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#clock-cells = <0>;
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};
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usia_u0_sclkdiv: usia_u0_sclkdiv {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x610 0>;
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clocks = <&pll3_fo>;
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#clock-cells = <0>;
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};
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usia_u0_sclk: usia_u0_sclk {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x4a0 1>;
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clocks = <&usia_u0_sclkdiv>;
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#clock-cells = <0>;
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};
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};
+1
-1
drivers/clk/shmobile/Makefile
+1
-1
drivers/clk/shmobile/Makefile
···
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obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
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obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
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obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
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obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o
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obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o
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-
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# for emply built-in.o
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obj-n := dummy
+104
drivers/clk/shmobile/clk-emev2.c
+104
drivers/clk/shmobile/clk-emev2.c
···
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/*
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* EMMA Mobile EV2 common clock framework support
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*
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* Copyright (C) 2013 Takashi Yoshii <takashi.yoshii.ze@renesas.com>
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* Copyright (C) 2012 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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/* EMEV2 SMU registers */
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#define USIAU0_RSTCTRL 0x094
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#define USIBU1_RSTCTRL 0x0ac
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#define USIBU2_RSTCTRL 0x0b0
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#define USIBU3_RSTCTRL 0x0b4
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#define STI_RSTCTRL 0x124
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#define STI_CLKSEL 0x688
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static DEFINE_SPINLOCK(lock);
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/* not pretty, but hey */
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void __iomem *smu_base;
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static void __init emev2_smu_write(unsigned long value, int offs)
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{
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BUG_ON(!smu_base || (offs >= PAGE_SIZE));
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writel_relaxed(value, smu_base + offs);
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}
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static const struct of_device_id smu_id[] __initconst = {
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{ .compatible = "renesas,emev2-smu", },
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{},
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};
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static void __init emev2_smu_init(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, smu_id);
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BUG_ON(!np);
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smu_base = of_iomap(np, 0);
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BUG_ON(!smu_base);
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of_node_put(np);
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/* setup STI timer to run on 32.768 kHz and deassert reset */
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emev2_smu_write(0, STI_CLKSEL);
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emev2_smu_write(1, STI_RSTCTRL);
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/* deassert reset for UART0->UART3 */
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emev2_smu_write(2, USIAU0_RSTCTRL);
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emev2_smu_write(2, USIBU1_RSTCTRL);
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emev2_smu_write(2, USIBU2_RSTCTRL);
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emev2_smu_write(2, USIBU3_RSTCTRL);
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}
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static void __init emev2_smu_clkdiv_init(struct device_node *np)
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{
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u32 reg[2];
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struct clk *clk;
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const char *parent_name = of_clk_get_parent_name(np, 0);
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if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
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return;
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if (!smu_base)
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emev2_smu_init();
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clk = clk_register_divider(NULL, np->name, parent_name, 0,
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smu_base + reg[0], reg[1], 8, 0, &lock);
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, np->name, NULL);
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pr_debug("## %s %s %p\n", __func__, np->name, clk);
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}
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CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
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emev2_smu_clkdiv_init);
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static void __init emev2_smu_gclk_init(struct device_node *np)
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{
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u32 reg[2];
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struct clk *clk;
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const char *parent_name = of_clk_get_parent_name(np, 0);
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if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
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return;
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if (!smu_base)
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emev2_smu_init();
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clk = clk_register_gate(NULL, np->name, parent_name, 0,
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smu_base + reg[0], reg[1], 0, &lock);
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, np->name, NULL);
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pr_debug("## %s %s %p\n", __func__, np->name, clk);
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}
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CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);