Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

+1 -5

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

··· 1944 1944 1945 1945 dce_v6_0_lock_cursor(crtc, true); 1946 1946 1947 - if (width != amdgpu_crtc->cursor_width || 1948 - height != amdgpu_crtc->cursor_height || 1949 - hot_x != amdgpu_crtc->cursor_hot_x || 1947 + if (hot_x != amdgpu_crtc->cursor_hot_x || 1950 1948 hot_y != amdgpu_crtc->cursor_hot_y) { 1951 1949 int x, y; 1952 1950 ··· 1953 1955 1954 1956 dce_v6_0_cursor_move_locked(crtc, x, y); 1955 1957 1956 - amdgpu_crtc->cursor_width = width; 1957 - amdgpu_crtc->cursor_height = height; 1958 1958 amdgpu_crtc->cursor_hot_x = hot_x; 1959 1959 amdgpu_crtc->cursor_hot_y = hot_y; 1960 1960 }

-2

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

··· 2438 2438 2439 2439 dce_v8_0_cursor_move_locked(crtc, x, y); 2440 2440 2441 - amdgpu_crtc->cursor_width = width; 2442 - amdgpu_crtc->cursor_height = height; 2443 2441 amdgpu_crtc->cursor_hot_x = hot_x; 2444 2442 amdgpu_crtc->cursor_hot_y = hot_y; 2445 2443 }

+736 -341

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

··· 411 411 break; 412 412 } 413 413 414 - if (adev->asic_type == CHIP_VERDE || 415 - adev->asic_type == CHIP_OLAND || 414 + if (adev->asic_type == CHIP_VERDE) { 415 + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 416 + switch (reg_offset) { 417 + case 0: 418 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 419 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 420 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 421 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 422 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 423 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 424 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 425 + NUM_BANKS(ADDR_SURF_16_BANK)); 426 + break; 427 + case 1: 428 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 429 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 430 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 431 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 432 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 433 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 434 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 435 + NUM_BANKS(ADDR_SURF_16_BANK)); 436 + break; 437 + case 2: 438 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 439 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 440 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 441 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 442 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 443 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 444 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 445 + NUM_BANKS(ADDR_SURF_16_BANK)); 446 + break; 447 + case 3: 448 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 449 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 450 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 451 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 452 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 453 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 454 + NUM_BANKS(ADDR_SURF_8_BANK) | 455 + TILE_SPLIT(split_equal_to_row_size)); 456 + break; 457 + case 4: 458 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 459 + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 460 + PIPE_CONFIG(ADDR_SURF_P4_8x16)); 461 + break; 462 + case 5: 463 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 464 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 465 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 466 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 467 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 468 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 469 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 470 + NUM_BANKS(ADDR_SURF_4_BANK)); 471 + break; 472 + case 6: 473 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 474 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 475 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 476 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 477 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 478 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 479 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 480 + NUM_BANKS(ADDR_SURF_4_BANK)); 481 + break; 482 + case 7: 483 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 484 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 485 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 486 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 487 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 488 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 489 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 490 + NUM_BANKS(ADDR_SURF_2_BANK)); 491 + break; 492 + case 8: 493 + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); 494 + break; 495 + case 9: 496 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 497 + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 498 + PIPE_CONFIG(ADDR_SURF_P4_8x16)); 499 + break; 500 + case 10: 501 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 502 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 503 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 504 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 505 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 506 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 507 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 508 + NUM_BANKS(ADDR_SURF_16_BANK)); 509 + break; 510 + case 11: 511 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 512 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 513 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 514 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 515 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 516 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 517 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 518 + NUM_BANKS(ADDR_SURF_16_BANK)); 519 + break; 520 + case 12: 521 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 522 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 523 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 524 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 525 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 526 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 527 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 528 + NUM_BANKS(ADDR_SURF_16_BANK)); 529 + break; 530 + case 13: 531 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 532 + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 533 + PIPE_CONFIG(ADDR_SURF_P4_8x16)); 534 + break; 535 + case 14: 536 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 537 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 538 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 539 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 540 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 541 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 542 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 543 + NUM_BANKS(ADDR_SURF_16_BANK)); 544 + break; 545 + case 15: 546 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 547 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 548 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 549 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 550 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 551 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 552 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 553 + NUM_BANKS(ADDR_SURF_16_BANK)); 554 + break; 555 + case 16: 556 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 557 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 558 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 559 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 560 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 561 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 562 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 563 + NUM_BANKS(ADDR_SURF_16_BANK)); 564 + break; 565 + case 17: 566 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 567 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 568 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 569 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 570 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 571 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 572 + NUM_BANKS(ADDR_SURF_16_BANK) | 573 + TILE_SPLIT(split_equal_to_row_size)); 574 + break; 575 + case 18: 576 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 577 + ARRAY_MODE(ARRAY_1D_TILED_THICK) | 578 + PIPE_CONFIG(ADDR_SURF_P4_8x16)); 579 + break; 580 + case 19: 581 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 582 + ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 583 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 584 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 585 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 586 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 587 + NUM_BANKS(ADDR_SURF_16_BANK) | 588 + TILE_SPLIT(split_equal_to_row_size)); 589 + break; 590 + case 20: 591 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 592 + ARRAY_MODE(ARRAY_2D_TILED_THICK) | 593 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 594 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 595 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 596 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 597 + NUM_BANKS(ADDR_SURF_16_BANK) | 598 + TILE_SPLIT(split_equal_to_row_size)); 599 + break; 600 + case 21: 601 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 602 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 603 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 604 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 605 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 606 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 607 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 608 + NUM_BANKS(ADDR_SURF_8_BANK)); 609 + break; 610 + case 22: 611 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 612 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 613 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 614 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 615 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 616 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 617 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 618 + NUM_BANKS(ADDR_SURF_8_BANK)); 619 + break; 620 + case 23: 621 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 622 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 623 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 624 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 625 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 626 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 627 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 628 + NUM_BANKS(ADDR_SURF_4_BANK)); 629 + break; 630 + case 24: 631 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 632 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 633 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 634 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 635 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 636 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 637 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 638 + NUM_BANKS(ADDR_SURF_4_BANK)); 639 + break; 640 + case 25: 641 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 642 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 643 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 644 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 645 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 646 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 647 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 648 + NUM_BANKS(ADDR_SURF_2_BANK)); 649 + break; 650 + case 26: 651 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 652 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 653 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 654 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 655 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 656 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 657 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 658 + NUM_BANKS(ADDR_SURF_2_BANK)); 659 + break; 660 + case 27: 661 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 662 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 663 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 664 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 665 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 666 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 667 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 668 + NUM_BANKS(ADDR_SURF_2_BANK)); 669 + break; 670 + case 28: 671 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 672 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 673 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 674 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 675 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 676 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 677 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 678 + NUM_BANKS(ADDR_SURF_2_BANK)); 679 + break; 680 + case 29: 681 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 682 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 683 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 684 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 685 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 686 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 687 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 688 + NUM_BANKS(ADDR_SURF_2_BANK)); 689 + break; 690 + case 30: 691 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 692 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 693 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 694 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 695 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 696 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 697 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 698 + NUM_BANKS(ADDR_SURF_2_BANK)); 699 + break; 700 + default: 701 + continue; 702 + } 703 + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 704 + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 705 + } 706 + } else if (adev->asic_type == CHIP_OLAND || 416 707 adev->asic_type == CHIP_HAINAN) { 417 708 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 418 709 switch (reg_offset) { 419 710 case 0: 420 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 421 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 422 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 711 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 712 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 713 + PIPE_CONFIG(ADDR_SURF_P2) | 423 714 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 424 - NUM_BANKS(ADDR_SURF_16_BANK) | 425 715 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 426 716 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 427 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 717 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 718 + NUM_BANKS(ADDR_SURF_16_BANK)); 428 719 break; 429 720 case 1: 430 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 431 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 432 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 721 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 722 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 723 + PIPE_CONFIG(ADDR_SURF_P2) | 433 724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 434 - NUM_BANKS(ADDR_SURF_16_BANK) | 435 725 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 436 726 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 437 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 727 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 728 + NUM_BANKS(ADDR_SURF_16_BANK)); 438 729 break; 439 730 case 2: 440 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 441 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 442 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 731 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 732 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 733 + PIPE_CONFIG(ADDR_SURF_P2) | 443 734 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 444 - NUM_BANKS(ADDR_SURF_16_BANK) | 445 735 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 446 736 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 447 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 737 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 738 + NUM_BANKS(ADDR_SURF_16_BANK)); 448 739 break; 449 740 case 3: 450 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 451 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 452 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 453 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 454 - NUM_BANKS(ADDR_SURF_16_BANK) | 741 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 742 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 743 + PIPE_CONFIG(ADDR_SURF_P2) | 455 744 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 456 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 457 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 745 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 746 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 747 + NUM_BANKS(ADDR_SURF_8_BANK) | 748 + TILE_SPLIT(split_equal_to_row_size)); 458 749 break; 459 750 case 4: 460 - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 461 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 462 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 463 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 464 - NUM_BANKS(ADDR_SURF_16_BANK) | 465 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 466 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 467 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 751 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 752 + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 753 + PIPE_CONFIG(ADDR_SURF_P2)); 468 754 break; 469 755 case 5: 470 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 471 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 472 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 473 - TILE_SPLIT(split_equal_to_row_size) | 474 - NUM_BANKS(ADDR_SURF_16_BANK) | 756 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 757 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 758 + PIPE_CONFIG(ADDR_SURF_P2) | 759 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 475 760 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 476 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 477 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 761 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 762 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 763 + NUM_BANKS(ADDR_SURF_8_BANK)); 478 764 break; 479 765 case 6: 480 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 481 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 482 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 483 - TILE_SPLIT(split_equal_to_row_size) | 484 - NUM_BANKS(ADDR_SURF_16_BANK) | 766 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 767 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 768 + PIPE_CONFIG(ADDR_SURF_P2) | 769 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 485 770 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 486 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 487 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 771 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 772 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 773 + NUM_BANKS(ADDR_SURF_8_BANK)); 488 774 break; 489 775 case 7: 490 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 491 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 492 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 493 - TILE_SPLIT(split_equal_to_row_size) | 494 - NUM_BANKS(ADDR_SURF_16_BANK) | 776 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 777 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 778 + PIPE_CONFIG(ADDR_SURF_P2) | 779 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 495 780 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 496 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 497 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 781 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 782 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 783 + NUM_BANKS(ADDR_SURF_4_BANK)); 498 784 break; 499 785 case 8: 500 - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 501 - MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 502 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 503 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 504 - NUM_BANKS(ADDR_SURF_16_BANK) | 505 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 506 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 507 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 786 + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); 508 787 break; 509 788 case 9: 510 - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 511 - MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 512 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 513 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 514 - NUM_BANKS(ADDR_SURF_16_BANK) | 515 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 516 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 517 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 789 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 790 + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 791 + PIPE_CONFIG(ADDR_SURF_P2)); 518 792 break; 519 793 case 10: 520 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 521 - MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 522 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 794 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 795 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 796 + PIPE_CONFIG(ADDR_SURF_P2) | 523 797 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 524 - NUM_BANKS(ADDR_SURF_16_BANK) | 525 798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 526 799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 527 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 800 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 801 + NUM_BANKS(ADDR_SURF_16_BANK)); 528 802 break; 529 803 case 11: 530 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 531 - MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 532 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 804 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 805 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 806 + PIPE_CONFIG(ADDR_SURF_P2) | 533 807 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 534 - NUM_BANKS(ADDR_SURF_16_BANK) | 535 808 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 536 809 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 537 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 810 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 811 + NUM_BANKS(ADDR_SURF_16_BANK)); 538 812 break; 539 813 case 12: 540 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 541 - MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 542 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 814 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 815 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 816 + PIPE_CONFIG(ADDR_SURF_P2) | 543 817 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 544 - NUM_BANKS(ADDR_SURF_16_BANK) | 545 818 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 546 819 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 547 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 820 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 821 + NUM_BANKS(ADDR_SURF_16_BANK)); 548 822 break; 549 823 case 13: 550 - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 551 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 552 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 553 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 554 - NUM_BANKS(ADDR_SURF_16_BANK) | 555 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 556 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 557 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 824 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 825 + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 826 + PIPE_CONFIG(ADDR_SURF_P2)); 558 827 break; 559 828 case 14: 560 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 561 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 562 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 829 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 830 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 831 + PIPE_CONFIG(ADDR_SURF_P2) | 563 832 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 564 - NUM_BANKS(ADDR_SURF_16_BANK) | 565 833 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 566 834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 567 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 835 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 836 + NUM_BANKS(ADDR_SURF_16_BANK)); 568 837 break; 569 838 case 15: 570 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 571 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 572 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 839 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 840 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 841 + PIPE_CONFIG(ADDR_SURF_P2) | 573 842 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 574 - NUM_BANKS(ADDR_SURF_16_BANK) | 575 843 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 576 844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 577 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 845 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 846 + NUM_BANKS(ADDR_SURF_16_BANK)); 578 847 break; 579 848 case 16: 580 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 581 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 582 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 849 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 850 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 851 + PIPE_CONFIG(ADDR_SURF_P2) | 583 852 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 584 - NUM_BANKS(ADDR_SURF_16_BANK) | 585 853 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 586 854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 587 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 855 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 856 + NUM_BANKS(ADDR_SURF_16_BANK)); 588 857 break; 589 858 case 17: 590 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 591 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 592 - PIPE_CONFIG(ADDR_SURF_P4_8x16) | 593 - TILE_SPLIT(split_equal_to_row_size) | 594 - NUM_BANKS(ADDR_SURF_16_BANK) | 859 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 860 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 861 + PIPE_CONFIG(ADDR_SURF_P2) | 595 862 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 596 863 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 597 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 864 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 865 + NUM_BANKS(ADDR_SURF_16_BANK) | 866 + TILE_SPLIT(split_equal_to_row_size)); 867 + break; 868 + case 18: 869 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 870 + ARRAY_MODE(ARRAY_1D_TILED_THICK) | 871 + PIPE_CONFIG(ADDR_SURF_P2)); 872 + break; 873 + case 19: 874 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 875 + ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 876 + PIPE_CONFIG(ADDR_SURF_P2) | 877 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 878 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 879 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 880 + NUM_BANKS(ADDR_SURF_16_BANK) | 881 + TILE_SPLIT(split_equal_to_row_size)); 882 + break; 883 + case 20: 884 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 885 + ARRAY_MODE(ARRAY_2D_TILED_THICK) | 886 + PIPE_CONFIG(ADDR_SURF_P2) | 887 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 888 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 889 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 890 + NUM_BANKS(ADDR_SURF_16_BANK) | 891 + TILE_SPLIT(split_equal_to_row_size)); 598 892 break; 599 893 case 21: 600 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 601 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 602 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 894 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 895 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 896 + PIPE_CONFIG(ADDR_SURF_P2) | 603 897 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 604 - NUM_BANKS(ADDR_SURF_16_BANK) | 605 898 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 606 899 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 607 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 900 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 901 + NUM_BANKS(ADDR_SURF_8_BANK)); 608 902 break; 609 903 case 22: 610 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 611 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 612 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 904 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 905 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 906 + PIPE_CONFIG(ADDR_SURF_P2) | 613 907 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 614 - NUM_BANKS(ADDR_SURF_16_BANK) | 615 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 616 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 617 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 908 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 909 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 910 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 911 + NUM_BANKS(ADDR_SURF_8_BANK)); 618 912 break; 619 913 case 23: 620 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 621 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 622 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 914 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 915 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 916 + PIPE_CONFIG(ADDR_SURF_P2) | 623 917 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 624 - NUM_BANKS(ADDR_SURF_16_BANK) | 625 918 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 626 919 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 627 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 920 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 921 + NUM_BANKS(ADDR_SURF_8_BANK)); 628 922 break; 629 923 case 24: 630 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 631 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 632 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 924 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 925 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 926 + PIPE_CONFIG(ADDR_SURF_P2) | 633 927 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 634 - NUM_BANKS(ADDR_SURF_16_BANK) | 635 928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 636 929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 637 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 930 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 931 + NUM_BANKS(ADDR_SURF_8_BANK)); 638 932 break; 639 933 case 25: 640 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 641 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 642 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 934 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 935 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 936 + PIPE_CONFIG(ADDR_SURF_P2) | 643 937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 644 - NUM_BANKS(ADDR_SURF_8_BANK) | 938 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 939 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 940 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 941 + NUM_BANKS(ADDR_SURF_4_BANK)); 942 + break; 943 + case 26: 944 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 945 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 946 + PIPE_CONFIG(ADDR_SURF_P2) | 947 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 948 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 949 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 950 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 951 + NUM_BANKS(ADDR_SURF_4_BANK)); 952 + break; 953 + case 27: 954 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 955 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 956 + PIPE_CONFIG(ADDR_SURF_P2) | 957 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 958 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 959 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 960 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 961 + NUM_BANKS(ADDR_SURF_4_BANK)); 962 + break; 963 + case 28: 964 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 965 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 966 + PIPE_CONFIG(ADDR_SURF_P2) | 967 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 968 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 969 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 970 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 971 + NUM_BANKS(ADDR_SURF_4_BANK)); 972 + break; 973 + case 29: 974 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 975 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 976 + PIPE_CONFIG(ADDR_SURF_P2) | 977 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 978 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 979 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 980 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 981 + NUM_BANKS(ADDR_SURF_4_BANK)); 982 + break; 983 + case 30: 984 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 985 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 986 + PIPE_CONFIG(ADDR_SURF_P2) | 987 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 645 988 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 646 989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 647 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 990 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 991 + NUM_BANKS(ADDR_SURF_4_BANK)); 648 992 break; 649 993 default: 650 - gb_tile_moden = 0; 651 - break; 994 + continue; 652 995 } 653 996 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 654 997 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); ··· 999 656 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 1000 657 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1001 658 switch (reg_offset) { 1002 - case 0: /* non-AA compressed depth or any compressed stencil */ 1003 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1004 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 659 + case 0: 660 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 661 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1005 662 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1006 663 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1007 - NUM_BANKS(ADDR_SURF_16_BANK) | 1008 664 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1009 665 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1010 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 666 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 667 + NUM_BANKS(ADDR_SURF_16_BANK)); 1011 668 break; 1012 - case 1: /* 2xAA/4xAA compressed depth only */ 1013 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1014 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 669 + case 1: 670 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 671 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1015 672 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1016 673 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1017 - NUM_BANKS(ADDR_SURF_16_BANK) | 1018 674 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1019 675 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1020 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 676 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 677 + NUM_BANKS(ADDR_SURF_16_BANK)); 1021 678 break; 1022 - case 2: /* 8xAA compressed depth only */ 1023 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1024 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 679 + case 2: 680 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 681 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1025 682 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1026 683 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1027 - NUM_BANKS(ADDR_SURF_16_BANK) | 1028 684 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1029 685 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1030 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 686 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 687 + NUM_BANKS(ADDR_SURF_16_BANK)); 1031 688 break; 1032 - case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ 1033 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1034 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 689 + case 3: 690 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 691 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1035 692 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1036 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1037 - NUM_BANKS(ADDR_SURF_16_BANK) | 1038 693 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1039 694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1040 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 695 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 696 + NUM_BANKS(ADDR_SURF_4_BANK) | 697 + TILE_SPLIT(split_equal_to_row_size)); 1041 698 break; 1042 - case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ 1043 - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1044 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1045 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1046 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1047 - NUM_BANKS(ADDR_SURF_16_BANK) | 1048 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1049 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1050 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 699 + case 4: 700 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 701 + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 702 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); 1051 703 break; 1052 - case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ 1053 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1054 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1055 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1056 - TILE_SPLIT(split_equal_to_row_size) | 1057 - NUM_BANKS(ADDR_SURF_16_BANK) | 1058 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1059 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1060 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1061 - break; 1062 - case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ 1063 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1064 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1065 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1066 - TILE_SPLIT(split_equal_to_row_size) | 1067 - NUM_BANKS(ADDR_SURF_16_BANK) | 1068 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1069 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1070 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1071 - break; 1072 - case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ 1073 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1074 - MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1075 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1076 - TILE_SPLIT(split_equal_to_row_size) | 1077 - NUM_BANKS(ADDR_SURF_16_BANK) | 1078 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1079 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1080 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1081 - break; 1082 - case 8: /* 1D and 1D Array Surfaces */ 1083 - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1084 - MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1085 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1086 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1087 - NUM_BANKS(ADDR_SURF_16_BANK) | 1088 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1089 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1090 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1091 - break; 1092 - case 9: /* Displayable maps. */ 1093 - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1094 - MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1095 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1096 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1097 - NUM_BANKS(ADDR_SURF_16_BANK) | 1098 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1099 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1100 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1101 - break; 1102 - case 10: /* Display 8bpp. */ 1103 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1104 - MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1105 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1106 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1107 - NUM_BANKS(ADDR_SURF_16_BANK) | 1108 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1109 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1110 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1111 - break; 1112 - case 11: /* Display 16bpp. */ 1113 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1114 - MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1115 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1116 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1117 - NUM_BANKS(ADDR_SURF_16_BANK) | 1118 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1119 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1120 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1121 - break; 1122 - case 12: /* Display 32bpp. */ 1123 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1124 - MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 704 + case 5: 705 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 706 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1125 707 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1126 708 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1127 - NUM_BANKS(ADDR_SURF_16_BANK) | 1128 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1129 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1130 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1131 - break; 1132 - case 13: /* Thin. */ 1133 - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1134 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1135 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1136 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1137 - NUM_BANKS(ADDR_SURF_16_BANK) | 1138 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1139 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1140 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1141 - break; 1142 - case 14: /* Thin 8 bpp. */ 1143 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1144 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1145 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1146 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1147 - NUM_BANKS(ADDR_SURF_16_BANK) | 1148 709 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1149 710 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1150 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 711 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 712 + NUM_BANKS(ADDR_SURF_2_BANK)); 1151 713 break; 1152 - case 15: /* Thin 16 bpp. */ 1153 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1154 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 714 + case 6: 715 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 716 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1155 717 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1156 718 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1157 - NUM_BANKS(ADDR_SURF_16_BANK) | 1158 719 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1159 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1160 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 720 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 721 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 722 + NUM_BANKS(ADDR_SURF_2_BANK)); 1161 723 break; 1162 - case 16: /* Thin 32 bpp. */ 1163 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1164 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1165 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1166 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1167 - NUM_BANKS(ADDR_SURF_16_BANK) | 1168 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1169 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1170 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1171 - break; 1172 - case 17: /* Thin 64 bpp. */ 1173 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1174 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1175 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1176 - TILE_SPLIT(split_equal_to_row_size) | 1177 - NUM_BANKS(ADDR_SURF_16_BANK) | 1178 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1179 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1180 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1181 - break; 1182 - case 21: /* 8 bpp PRT. */ 1183 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1184 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1185 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1186 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1187 - NUM_BANKS(ADDR_SURF_16_BANK) | 1188 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1189 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1190 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1191 - break; 1192 - case 22: /* 16 bpp PRT */ 1193 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1194 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1195 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1196 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1197 - NUM_BANKS(ADDR_SURF_16_BANK) | 1198 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1199 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1200 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1201 - break; 1202 - case 23: /* 32 bpp PRT */ 1203 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1204 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1205 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1206 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1207 - NUM_BANKS(ADDR_SURF_16_BANK) | 1208 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1209 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1210 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1211 - break; 1212 - case 24: /* 64 bpp PRT */ 1213 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1214 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1215 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1216 - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1217 - NUM_BANKS(ADDR_SURF_16_BANK) | 1218 - BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1219 - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1220 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1221 - break; 1222 - case 25: /* 128 bpp PRT */ 1223 - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1224 - MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1225 - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 724 + case 7: 725 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 726 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 727 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1226 728 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1227 - NUM_BANKS(ADDR_SURF_8_BANK) | 729 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 730 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 731 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 732 + NUM_BANKS(ADDR_SURF_2_BANK)); 733 + break; 734 + case 8: 735 + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); 736 + break; 737 + case 9: 738 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 739 + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 740 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); 741 + break; 742 + case 10: 743 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 744 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 745 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 746 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 747 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 748 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 749 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 750 + NUM_BANKS(ADDR_SURF_16_BANK)); 751 + break; 752 + case 11: 753 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 754 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 755 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 756 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 757 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 758 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 759 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 760 + NUM_BANKS(ADDR_SURF_16_BANK)); 761 + break; 762 + case 12: 763 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 764 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 765 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 766 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1228 767 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1229 768 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1230 - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 769 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 770 + NUM_BANKS(ADDR_SURF_16_BANK)); 771 + break; 772 + case 13: 773 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 774 + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 775 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); 776 + break; 777 + case 14: 778 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 779 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 780 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 781 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 782 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 783 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 784 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 785 + NUM_BANKS(ADDR_SURF_16_BANK)); 786 + break; 787 + case 15: 788 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 789 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 790 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 791 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 792 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 793 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 794 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 795 + NUM_BANKS(ADDR_SURF_16_BANK)); 796 + break; 797 + case 16: 798 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 799 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 800 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 801 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 802 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 803 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 804 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 805 + NUM_BANKS(ADDR_SURF_16_BANK)); 806 + break; 807 + case 17: 808 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 809 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 810 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 811 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 812 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 813 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 814 + NUM_BANKS(ADDR_SURF_16_BANK) | 815 + TILE_SPLIT(split_equal_to_row_size)); 816 + break; 817 + case 18: 818 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 819 + ARRAY_MODE(ARRAY_1D_TILED_THICK) | 820 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); 821 + break; 822 + case 19: 823 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 824 + ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 825 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 826 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 827 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 828 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 829 + NUM_BANKS(ADDR_SURF_16_BANK) | 830 + TILE_SPLIT(split_equal_to_row_size)); 831 + break; 832 + case 20: 833 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 834 + ARRAY_MODE(ARRAY_2D_TILED_THICK) | 835 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 836 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 837 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 838 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 839 + NUM_BANKS(ADDR_SURF_16_BANK) | 840 + TILE_SPLIT(split_equal_to_row_size)); 841 + break; 842 + case 21: 843 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 844 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 845 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 846 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 847 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 848 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 849 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 850 + NUM_BANKS(ADDR_SURF_4_BANK)); 851 + break; 852 + case 22: 853 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 854 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 855 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 856 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 857 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 858 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 859 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 860 + NUM_BANKS(ADDR_SURF_4_BANK)); 861 + break; 862 + case 23: 863 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 864 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 865 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 866 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 867 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 868 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 869 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 870 + NUM_BANKS(ADDR_SURF_2_BANK)); 871 + break; 872 + case 24: 873 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 874 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 875 + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 876 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 877 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 878 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 879 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 880 + NUM_BANKS(ADDR_SURF_2_BANK)); 881 + break; 882 + case 25: 883 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 884 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 885 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 886 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 887 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 888 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 889 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 890 + NUM_BANKS(ADDR_SURF_2_BANK)); 891 + break; 892 + case 26: 893 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 894 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 895 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 896 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 897 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 898 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 899 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 900 + NUM_BANKS(ADDR_SURF_2_BANK)); 901 + break; 902 + case 27: 903 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 904 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 905 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 906 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 907 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 908 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 909 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 910 + NUM_BANKS(ADDR_SURF_2_BANK)); 911 + break; 912 + case 28: 913 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 914 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 915 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 916 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 917 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 918 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 919 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 920 + NUM_BANKS(ADDR_SURF_2_BANK)); 921 + break; 922 + case 29: 923 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 924 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 925 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 926 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 927 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 928 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 929 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 930 + NUM_BANKS(ADDR_SURF_2_BANK)); 931 + break; 932 + case 30: 933 + gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 934 + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 935 + PIPE_CONFIG(ADDR_SURF_P4_8x16) | 936 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 937 + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 938 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 939 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 940 + NUM_BANKS(ADDR_SURF_2_BANK)); 1231 941 break; 1232 942 default: 1233 - gb_tile_moden = 0; 1234 - break; 943 + continue; 1235 944 } 1236 945 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 1237 946 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);

+161 -88

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

··· 3949 3949 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0; 3950 3950 data = mmRLC_SRM_INDEX_CNTL_DATA_0; 3951 3951 for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) { 3952 - amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false); 3953 - amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false); 3952 + if (unique_indices[i] != 0) { 3953 + amdgpu_mm_wreg(adev, temp + i, 3954 + unique_indices[i] & 0x3FFFF, false); 3955 + amdgpu_mm_wreg(adev, data + i, 3956 + unique_indices[i] >> 20, false); 3957 + } 3954 3958 } 3955 3959 kfree(register_list_format); 3956 3960 ··· 3970 3966 { 3971 3967 uint32_t data; 3972 3968 3973 - if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3974 - AMD_PG_SUPPORT_GFX_SMG | 3975 - AMD_PG_SUPPORT_GFX_DMG)) { 3976 - WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60); 3969 + WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60); 3977 3970 3978 - data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10); 3979 - data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10); 3980 - data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10); 3981 - data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10); 3982 - WREG32(mmRLC_PG_DELAY, data); 3971 + data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10); 3972 + data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10); 3973 + data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10); 3974 + data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10); 3975 + WREG32(mmRLC_PG_DELAY, data); 3983 3976 3984 - WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3); 3985 - WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0); 3986 - } 3977 + WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3); 3978 + WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0); 3979 + 3987 3980 } 3988 3981 3989 3982 static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, ··· 3997 3996 3998 3997 static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable) 3999 3998 { 4000 - WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 1 : 0); 3999 + WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1); 4001 4000 } 4002 4001 4003 4002 static void gfx_v8_0_init_pg(struct amdgpu_device *adev) 4004 4003 { 4005 - if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4006 - AMD_PG_SUPPORT_GFX_SMG | 4007 - AMD_PG_SUPPORT_GFX_DMG | 4008 - AMD_PG_SUPPORT_CP | 4009 - AMD_PG_SUPPORT_GDS | 4010 - AMD_PG_SUPPORT_RLC_SMU_HS)) { 4004 + if ((adev->asic_type == CHIP_CARRIZO) || 4005 + (adev->asic_type == CHIP_STONEY)) { 4011 4006 gfx_v8_0_init_csb(adev); 4012 4007 gfx_v8_0_init_save_restore_list(adev); 4013 4008 gfx_v8_0_enable_save_restore_machine(adev); 4014 - 4015 - if ((adev->asic_type == CHIP_CARRIZO) || 4016 - (adev->asic_type == CHIP_STONEY)) { 4017 - WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 4018 - gfx_v8_0_init_power_gating(adev); 4019 - WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 4020 - if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 4021 - cz_enable_sck_slow_down_on_power_up(adev, true); 4022 - cz_enable_sck_slow_down_on_power_down(adev, true); 4023 - } else { 4024 - cz_enable_sck_slow_down_on_power_up(adev, false); 4025 - cz_enable_sck_slow_down_on_power_down(adev, false); 4026 - } 4027 - if (adev->pg_flags & AMD_PG_SUPPORT_CP) 4028 - cz_enable_cp_power_gating(adev, true); 4029 - else 4030 - cz_enable_cp_power_gating(adev, false); 4031 - } else if (adev->asic_type == CHIP_POLARIS11) { 4032 - gfx_v8_0_init_power_gating(adev); 4009 + WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 4010 + gfx_v8_0_init_power_gating(adev); 4011 + WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 4012 + if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 4013 + cz_enable_sck_slow_down_on_power_up(adev, true); 4014 + cz_enable_sck_slow_down_on_power_down(adev, true); 4015 + } else { 4016 + cz_enable_sck_slow_down_on_power_up(adev, false); 4017 + cz_enable_sck_slow_down_on_power_down(adev, false); 4033 4018 } 4019 + if (adev->pg_flags & AMD_PG_SUPPORT_CP) 4020 + cz_enable_cp_power_gating(adev, true); 4021 + else 4022 + cz_enable_cp_power_gating(adev, false); 4023 + } else if (adev->asic_type == CHIP_POLARIS11) { 4024 + gfx_v8_0_init_csb(adev); 4025 + gfx_v8_0_init_save_restore_list(adev); 4026 + gfx_v8_0_enable_save_restore_machine(adev); 4027 + gfx_v8_0_init_power_gating(adev); 4034 4028 } 4029 + 4035 4030 } 4036 4031 4037 4032 static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) ··· 5336 5339 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5337 5340 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 5338 5341 5339 - if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5340 - return 0; 5341 - 5342 5342 switch (adev->asic_type) { 5343 5343 case CHIP_CARRIZO: 5344 5344 case CHIP_STONEY: 5345 - if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) 5346 - cz_update_gfx_cg_power_gating(adev, enable); 5345 + 5346 + cz_update_gfx_cg_power_gating(adev, enable); 5347 5347 5348 5348 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 5349 5349 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true); ··· 5785 5791 static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, 5786 5792 enum amd_clockgating_state state) 5787 5793 { 5788 - uint32_t msg_id, pp_state; 5794 + uint32_t msg_id, pp_state = 0; 5795 + uint32_t pp_support_state = 0; 5789 5796 void *pp_handle = adev->powerplay.pp_handle; 5790 5797 5791 - if (state == AMD_CG_STATE_UNGATE) 5792 - pp_state = 0; 5793 - else 5794 - pp_state = PP_STATE_CG | PP_STATE_LS; 5798 + if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) { 5799 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5800 + pp_support_state = PP_STATE_SUPPORT_LS; 5801 + pp_state = PP_STATE_LS; 5802 + } 5803 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5804 + pp_support_state |= PP_STATE_SUPPORT_CG; 5805 + pp_state |= PP_STATE_CG; 5806 + } 5807 + if (state == AMD_CG_STATE_UNGATE) 5808 + pp_state = 0; 5795 5809 5796 - msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5797 - PP_BLOCK_GFX_CG, 5798 - PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5799 - pp_state); 5800 - amd_set_clockgating_by_smu(pp_handle, msg_id); 5810 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5811 + PP_BLOCK_GFX_CG, 5812 + pp_support_state, 5813 + pp_state); 5814 + amd_set_clockgating_by_smu(pp_handle, msg_id); 5815 + } 5801 5816 5802 - msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5803 - PP_BLOCK_GFX_MG, 5804 - PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5805 - pp_state); 5806 - amd_set_clockgating_by_smu(pp_handle, msg_id); 5817 + if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) { 5818 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 5819 + pp_support_state = PP_STATE_SUPPORT_LS; 5820 + pp_state = PP_STATE_LS; 5821 + } 5822 + 5823 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5824 + pp_support_state |= PP_STATE_SUPPORT_CG; 5825 + pp_state |= PP_STATE_CG; 5826 + } 5827 + 5828 + if (state == AMD_CG_STATE_UNGATE) 5829 + pp_state = 0; 5830 + 5831 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5832 + PP_BLOCK_GFX_MG, 5833 + pp_support_state, 5834 + pp_state); 5835 + amd_set_clockgating_by_smu(pp_handle, msg_id); 5836 + } 5807 5837 5808 5838 return 0; 5809 5839 } ··· 5835 5817 static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, 5836 5818 enum amd_clockgating_state state) 5837 5819 { 5838 - uint32_t msg_id, pp_state; 5820 + 5821 + uint32_t msg_id, pp_state = 0; 5822 + uint32_t pp_support_state = 0; 5839 5823 void *pp_handle = adev->powerplay.pp_handle; 5840 5824 5841 - if (state == AMD_CG_STATE_UNGATE) 5842 - pp_state = 0; 5843 - else 5844 - pp_state = PP_STATE_CG | PP_STATE_LS; 5825 + if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) { 5826 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5827 + pp_support_state = PP_STATE_SUPPORT_LS; 5828 + pp_state = PP_STATE_LS; 5829 + } 5830 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5831 + pp_support_state |= PP_STATE_SUPPORT_CG; 5832 + pp_state |= PP_STATE_CG; 5833 + } 5834 + if (state == AMD_CG_STATE_UNGATE) 5835 + pp_state = 0; 5845 5836 5846 - msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5847 - PP_BLOCK_GFX_CG, 5848 - PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5849 - pp_state); 5850 - amd_set_clockgating_by_smu(pp_handle, msg_id); 5837 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5838 + PP_BLOCK_GFX_CG, 5839 + pp_support_state, 5840 + pp_state); 5841 + amd_set_clockgating_by_smu(pp_handle, msg_id); 5842 + } 5851 5843 5852 - msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5853 - PP_BLOCK_GFX_3D, 5854 - PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5855 - pp_state); 5856 - amd_set_clockgating_by_smu(pp_handle, msg_id); 5844 + if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) { 5845 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5846 + pp_support_state = PP_STATE_SUPPORT_LS; 5847 + pp_state = PP_STATE_LS; 5848 + } 5849 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5850 + pp_support_state |= PP_STATE_SUPPORT_CG; 5851 + pp_state |= PP_STATE_CG; 5852 + } 5853 + if (state == AMD_CG_STATE_UNGATE) 5854 + pp_state = 0; 5857 5855 5858 - msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5859 - PP_BLOCK_GFX_MG, 5860 - PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5861 - pp_state); 5862 - amd_set_clockgating_by_smu(pp_handle, msg_id); 5856 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5857 + PP_BLOCK_GFX_3D, 5858 + pp_support_state, 5859 + pp_state); 5860 + amd_set_clockgating_by_smu(pp_handle, msg_id); 5861 + } 5863 5862 5864 - msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5865 - PP_BLOCK_GFX_RLC, 5866 - PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5867 - pp_state); 5868 - amd_set_clockgating_by_smu(pp_handle, msg_id); 5863 + if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) { 5864 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 5865 + pp_support_state = PP_STATE_SUPPORT_LS; 5866 + pp_state = PP_STATE_LS; 5867 + } 5869 5868 5870 - msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5869 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5870 + pp_support_state |= PP_STATE_SUPPORT_CG; 5871 + pp_state |= PP_STATE_CG; 5872 + } 5873 + 5874 + if (state == AMD_CG_STATE_UNGATE) 5875 + pp_state = 0; 5876 + 5877 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5878 + PP_BLOCK_GFX_MG, 5879 + pp_support_state, 5880 + pp_state); 5881 + amd_set_clockgating_by_smu(pp_handle, msg_id); 5882 + } 5883 + 5884 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 5885 + pp_support_state = PP_STATE_SUPPORT_LS; 5886 + 5887 + if (state == AMD_CG_STATE_UNGATE) 5888 + pp_state = 0; 5889 + else 5890 + pp_state = PP_STATE_LS; 5891 + 5892 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5893 + PP_BLOCK_GFX_RLC, 5894 + pp_support_state, 5895 + pp_state); 5896 + amd_set_clockgating_by_smu(pp_handle, msg_id); 5897 + } 5898 + 5899 + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 5900 + pp_support_state = PP_STATE_SUPPORT_LS; 5901 + 5902 + if (state == AMD_CG_STATE_UNGATE) 5903 + pp_state = 0; 5904 + else 5905 + pp_state = PP_STATE_LS; 5906 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5871 5907 PP_BLOCK_GFX_CP, 5872 - PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5908 + pp_support_state, 5873 5909 pp_state); 5874 - amd_set_clockgating_by_smu(pp_handle, msg_id); 5910 + amd_set_clockgating_by_smu(pp_handle, msg_id); 5911 + } 5875 5912 5876 5913 return 0; 5877 5914 }

+227 -215

drivers/gpu/drm/amd/amdgpu/si.c

··· 43 43 44 44 static const u32 tahiti_golden_registers[] = 45 45 { 46 + 0x17bc, 0x00000030, 0x00000011, 46 47 0x2684, 0x00010000, 0x00018208, 47 48 0x260c, 0xffffffff, 0x00000000, 48 49 0x260d, 0xf00fffff, 0x00000400, 49 50 0x260e, 0x0002021c, 0x00020200, 50 51 0x031e, 0x00000080, 0x00000000, 51 - 0x340c, 0x000300c0, 0x00800040, 52 - 0x360c, 0x000300c0, 0x00800040, 52 + 0x340c, 0x000000c0, 0x00800040, 53 + 0x360c, 0x000000c0, 0x00800040, 53 54 0x16ec, 0x000000f0, 0x00000070, 54 55 0x16f0, 0x00200000, 0x50100000, 55 56 0x1c0c, 0x31000311, 0x00000011, ··· 61 60 0x22c4, 0x0000ff0f, 0x00000000, 62 61 0xa293, 0x07ffffff, 0x4e000000, 63 62 0xa0d4, 0x3f3f3fff, 0x2a00126a, 64 - 0x000c, 0x000000ff, 0x0040, 63 + 0x000c, 0xffffffff, 0x0040, 65 64 0x000d, 0x00000040, 0x00004040, 66 65 0x2440, 0x07ffffff, 0x03000000, 67 66 0x23a2, 0x01ff1f3f, 0x00000000, ··· 74 73 0x2234, 0xffffffff, 0x000fff40, 75 74 0x2235, 0x0000001f, 0x00000010, 76 75 0x0504, 0x20000000, 0x20fffed8, 77 - 0x0570, 0x000c0fc0, 0x000c0400 76 + 0x0570, 0x000c0fc0, 0x000c0400, 77 + 0x052c, 0x0fffffff, 0xffffffff, 78 + 0x052d, 0x0fffffff, 0x0fffffff, 79 + 0x052e, 0x0fffffff, 0x0fffffff, 80 + 0x052f, 0x0fffffff, 0x0fffffff 78 81 }; 79 82 80 83 static const u32 tahiti_golden_registers2[] = ··· 88 83 89 84 static const u32 tahiti_golden_rlc_registers[] = 90 85 { 86 + 0x263e, 0xffffffff, 0x12011003, 91 87 0x3109, 0xffffffff, 0x00601005, 92 88 0x311f, 0xffffffff, 0x10104040, 93 89 0x3122, 0xffffffff, 0x0100000a, 94 90 0x30c5, 0xffffffff, 0x00000800, 95 91 0x30c3, 0xffffffff, 0x800000f4, 96 - 0x3d2a, 0xffffffff, 0x00000000 92 + 0x3d2a, 0x00000008, 0x00000000 97 93 }; 98 94 99 95 static const u32 pitcairn_golden_registers[] = 100 96 { 97 + 0x17bc, 0x00000030, 0x00000011, 101 98 0x2684, 0x00010000, 0x00018208, 102 99 0x260c, 0xffffffff, 0x00000000, 103 100 0x260d, 0xf00fffff, 0x00000400, ··· 117 110 0x22c4, 0x0000ff0f, 0x00000000, 118 111 0xa293, 0x07ffffff, 0x4e000000, 119 112 0xa0d4, 0x3f3f3fff, 0x2a00126a, 120 - 0x000c, 0x000000ff, 0x0040, 113 + 0x000c, 0xffffffff, 0x0040, 121 114 0x000d, 0x00000040, 0x00004040, 122 115 0x2440, 0x07ffffff, 0x03000000, 123 116 0x2418, 0x0000007f, 0x00000020, ··· 126 119 0x2b04, 0xffffffff, 0x00000000, 127 120 0x2b03, 0xffffffff, 0x32761054, 128 121 0x2235, 0x0000001f, 0x00000010, 129 - 0x0570, 0x000c0fc0, 0x000c0400 122 + 0x0570, 0x000c0fc0, 0x000c0400, 123 + 0x052c, 0x0fffffff, 0xffffffff, 124 + 0x052d, 0x0fffffff, 0x0fffffff, 125 + 0x052e, 0x0fffffff, 0x0fffffff, 126 + 0x052f, 0x0fffffff, 0x0fffffff 130 127 }; 131 128 132 129 static const u32 pitcairn_golden_rlc_registers[] = 133 130 { 131 + 0x263e, 0xffffffff, 0x12011003, 134 132 0x3109, 0xffffffff, 0x00601004, 135 133 0x311f, 0xffffffff, 0x10102020, 136 134 0x3122, 0xffffffff, 0x01000020, ··· 145 133 146 134 static const u32 verde_pg_init[] = 147 135 { 148 - 0xd4f, 0xffffffff, 0x40000, 149 - 0xd4e, 0xffffffff, 0x200010ff, 150 - 0xd4f, 0xffffffff, 0x0, 151 - 0xd4f, 0xffffffff, 0x0, 152 - 0xd4f, 0xffffffff, 0x0, 153 - 0xd4f, 0xffffffff, 0x0, 154 - 0xd4f, 0xffffffff, 0x0, 155 - 0xd4f, 0xffffffff, 0x7007, 156 - 0xd4e, 0xffffffff, 0x300010ff, 157 - 0xd4f, 0xffffffff, 0x0, 158 - 0xd4f, 0xffffffff, 0x0, 159 - 0xd4f, 0xffffffff, 0x0, 160 - 0xd4f, 0xffffffff, 0x0, 161 - 0xd4f, 0xffffffff, 0x0, 162 - 0xd4f, 0xffffffff, 0x400000, 163 - 0xd4e, 0xffffffff, 0x100010ff, 164 - 0xd4f, 0xffffffff, 0x0, 165 - 0xd4f, 0xffffffff, 0x0, 166 - 0xd4f, 0xffffffff, 0x0, 167 - 0xd4f, 0xffffffff, 0x0, 168 - 0xd4f, 0xffffffff, 0x0, 169 - 0xd4f, 0xffffffff, 0x120200, 170 - 0xd4e, 0xffffffff, 0x500010ff, 171 - 0xd4f, 0xffffffff, 0x0, 172 - 0xd4f, 0xffffffff, 0x0, 173 - 0xd4f, 0xffffffff, 0x0, 174 - 0xd4f, 0xffffffff, 0x0, 175 - 0xd4f, 0xffffffff, 0x0, 176 - 0xd4f, 0xffffffff, 0x1e1e16, 177 - 0xd4e, 0xffffffff, 0x600010ff, 178 - 0xd4f, 0xffffffff, 0x0, 179 - 0xd4f, 0xffffffff, 0x0, 180 - 0xd4f, 0xffffffff, 0x0, 181 - 0xd4f, 0xffffffff, 0x0, 182 - 0xd4f, 0xffffffff, 0x0, 183 - 0xd4f, 0xffffffff, 0x171f1e, 184 - 0xd4e, 0xffffffff, 0x700010ff, 185 - 0xd4f, 0xffffffff, 0x0, 186 - 0xd4f, 0xffffffff, 0x0, 187 - 0xd4f, 0xffffffff, 0x0, 188 - 0xd4f, 0xffffffff, 0x0, 189 - 0xd4f, 0xffffffff, 0x0, 190 - 0xd4f, 0xffffffff, 0x0, 191 - 0xd4e, 0xffffffff, 0x9ff, 192 - 0xd40, 0xffffffff, 0x0, 193 - 0xd41, 0xffffffff, 0x10000800, 194 - 0xd41, 0xffffffff, 0xf, 195 - 0xd41, 0xffffffff, 0xf, 196 - 0xd40, 0xffffffff, 0x4, 197 - 0xd41, 0xffffffff, 0x1000051e, 198 - 0xd41, 0xffffffff, 0xffff, 199 - 0xd41, 0xffffffff, 0xffff, 200 - 0xd40, 0xffffffff, 0x8, 201 - 0xd41, 0xffffffff, 0x80500, 202 - 0xd40, 0xffffffff, 0x12, 203 - 0xd41, 0xffffffff, 0x9050c, 204 - 0xd40, 0xffffffff, 0x1d, 205 - 0xd41, 0xffffffff, 0xb052c, 206 - 0xd40, 0xffffffff, 0x2a, 207 - 0xd41, 0xffffffff, 0x1053e, 208 - 0xd40, 0xffffffff, 0x2d, 209 - 0xd41, 0xffffffff, 0x10546, 210 - 0xd40, 0xffffffff, 0x30, 211 - 0xd41, 0xffffffff, 0xa054e, 212 - 0xd40, 0xffffffff, 0x3c, 213 - 0xd41, 0xffffffff, 0x1055f, 214 - 0xd40, 0xffffffff, 0x3f, 215 - 0xd41, 0xffffffff, 0x10567, 216 - 0xd40, 0xffffffff, 0x42, 217 - 0xd41, 0xffffffff, 0x1056f, 218 - 0xd40, 0xffffffff, 0x45, 219 - 0xd41, 0xffffffff, 0x10572, 220 - 0xd40, 0xffffffff, 0x48, 221 - 0xd41, 0xffffffff, 0x20575, 222 - 0xd40, 0xffffffff, 0x4c, 223 - 0xd41, 0xffffffff, 0x190801, 224 - 0xd40, 0xffffffff, 0x67, 225 - 0xd41, 0xffffffff, 0x1082a, 226 - 0xd40, 0xffffffff, 0x6a, 227 - 0xd41, 0xffffffff, 0x1b082d, 228 - 0xd40, 0xffffffff, 0x87, 229 - 0xd41, 0xffffffff, 0x310851, 230 - 0xd40, 0xffffffff, 0xba, 231 - 0xd41, 0xffffffff, 0x891, 232 - 0xd40, 0xffffffff, 0xbc, 233 - 0xd41, 0xffffffff, 0x893, 234 - 0xd40, 0xffffffff, 0xbe, 235 - 0xd41, 0xffffffff, 0x20895, 236 - 0xd40, 0xffffffff, 0xc2, 237 - 0xd41, 0xffffffff, 0x20899, 238 - 0xd40, 0xffffffff, 0xc6, 239 - 0xd41, 0xffffffff, 0x2089d, 240 - 0xd40, 0xffffffff, 0xca, 241 - 0xd41, 0xffffffff, 0x8a1, 242 - 0xd40, 0xffffffff, 0xcc, 243 - 0xd41, 0xffffffff, 0x8a3, 244 - 0xd40, 0xffffffff, 0xce, 245 - 0xd41, 0xffffffff, 0x308a5, 246 - 0xd40, 0xffffffff, 0xd3, 247 - 0xd41, 0xffffffff, 0x6d08cd, 248 - 0xd40, 0xffffffff, 0x142, 249 - 0xd41, 0xffffffff, 0x2000095a, 250 - 0xd41, 0xffffffff, 0x1, 251 - 0xd40, 0xffffffff, 0x144, 252 - 0xd41, 0xffffffff, 0x301f095b, 253 - 0xd40, 0xffffffff, 0x165, 254 - 0xd41, 0xffffffff, 0xc094d, 255 - 0xd40, 0xffffffff, 0x173, 256 - 0xd41, 0xffffffff, 0xf096d, 257 - 0xd40, 0xffffffff, 0x184, 258 - 0xd41, 0xffffffff, 0x15097f, 259 - 0xd40, 0xffffffff, 0x19b, 260 - 0xd41, 0xffffffff, 0xc0998, 261 - 0xd40, 0xffffffff, 0x1a9, 262 - 0xd41, 0xffffffff, 0x409a7, 263 - 0xd40, 0xffffffff, 0x1af, 264 - 0xd41, 0xffffffff, 0xcdc, 265 - 0xd40, 0xffffffff, 0x1b1, 266 - 0xd41, 0xffffffff, 0x800, 267 - 0xd42, 0xffffffff, 0x6c9b2000, 268 - 0xd44, 0xfc00, 0x2000, 269 - 0xd51, 0xffffffff, 0xfc0, 270 - 0xa35, 0x00000100, 0x100 136 + 0x0d4f, 0xffffffff, 0x40000, 137 + 0x0d4e, 0xffffffff, 0x200010ff, 138 + 0x0d4f, 0xffffffff, 0x0, 139 + 0x0d4f, 0xffffffff, 0x0, 140 + 0x0d4f, 0xffffffff, 0x0, 141 + 0x0d4f, 0xffffffff, 0x0, 142 + 0x0d4f, 0xffffffff, 0x0, 143 + 0x0d4f, 0xffffffff, 0x7007, 144 + 0x0d4e, 0xffffffff, 0x300010ff, 145 + 0x0d4f, 0xffffffff, 0x0, 146 + 0x0d4f, 0xffffffff, 0x0, 147 + 0x0d4f, 0xffffffff, 0x0, 148 + 0x0d4f, 0xffffffff, 0x0, 149 + 0x0d4f, 0xffffffff, 0x0, 150 + 0x0d4f, 0xffffffff, 0x400000, 151 + 0x0d4e, 0xffffffff, 0x100010ff, 152 + 0x0d4f, 0xffffffff, 0x0, 153 + 0x0d4f, 0xffffffff, 0x0, 154 + 0x0d4f, 0xffffffff, 0x0, 155 + 0x0d4f, 0xffffffff, 0x0, 156 + 0x0d4f, 0xffffffff, 0x0, 157 + 0x0d4f, 0xffffffff, 0x120200, 158 + 0x0d4e, 0xffffffff, 0x500010ff, 159 + 0x0d4f, 0xffffffff, 0x0, 160 + 0x0d4f, 0xffffffff, 0x0, 161 + 0x0d4f, 0xffffffff, 0x0, 162 + 0x0d4f, 0xffffffff, 0x0, 163 + 0x0d4f, 0xffffffff, 0x0, 164 + 0x0d4f, 0xffffffff, 0x1e1e16, 165 + 0x0d4e, 0xffffffff, 0x600010ff, 166 + 0x0d4f, 0xffffffff, 0x0, 167 + 0x0d4f, 0xffffffff, 0x0, 168 + 0x0d4f, 0xffffffff, 0x0, 169 + 0x0d4f, 0xffffffff, 0x0, 170 + 0x0d4f, 0xffffffff, 0x0, 171 + 0x0d4f, 0xffffffff, 0x171f1e, 172 + 0x0d4e, 0xffffffff, 0x700010ff, 173 + 0x0d4f, 0xffffffff, 0x0, 174 + 0x0d4f, 0xffffffff, 0x0, 175 + 0x0d4f, 0xffffffff, 0x0, 176 + 0x0d4f, 0xffffffff, 0x0, 177 + 0x0d4f, 0xffffffff, 0x0, 178 + 0x0d4f, 0xffffffff, 0x0, 179 + 0x0d4e, 0xffffffff, 0x9ff, 180 + 0x0d40, 0xffffffff, 0x0, 181 + 0x0d41, 0xffffffff, 0x10000800, 182 + 0x0d41, 0xffffffff, 0xf, 183 + 0x0d41, 0xffffffff, 0xf, 184 + 0x0d40, 0xffffffff, 0x4, 185 + 0x0d41, 0xffffffff, 0x1000051e, 186 + 0x0d41, 0xffffffff, 0xffff, 187 + 0x0d41, 0xffffffff, 0xffff, 188 + 0x0d40, 0xffffffff, 0x8, 189 + 0x0d41, 0xffffffff, 0x80500, 190 + 0x0d40, 0xffffffff, 0x12, 191 + 0x0d41, 0xffffffff, 0x9050c, 192 + 0x0d40, 0xffffffff, 0x1d, 193 + 0x0d41, 0xffffffff, 0xb052c, 194 + 0x0d40, 0xffffffff, 0x2a, 195 + 0x0d41, 0xffffffff, 0x1053e, 196 + 0x0d40, 0xffffffff, 0x2d, 197 + 0x0d41, 0xffffffff, 0x10546, 198 + 0x0d40, 0xffffffff, 0x30, 199 + 0x0d41, 0xffffffff, 0xa054e, 200 + 0x0d40, 0xffffffff, 0x3c, 201 + 0x0d41, 0xffffffff, 0x1055f, 202 + 0x0d40, 0xffffffff, 0x3f, 203 + 0x0d41, 0xffffffff, 0x10567, 204 + 0x0d40, 0xffffffff, 0x42, 205 + 0x0d41, 0xffffffff, 0x1056f, 206 + 0x0d40, 0xffffffff, 0x45, 207 + 0x0d41, 0xffffffff, 0x10572, 208 + 0x0d40, 0xffffffff, 0x48, 209 + 0x0d41, 0xffffffff, 0x20575, 210 + 0x0d40, 0xffffffff, 0x4c, 211 + 0x0d41, 0xffffffff, 0x190801, 212 + 0x0d40, 0xffffffff, 0x67, 213 + 0x0d41, 0xffffffff, 0x1082a, 214 + 0x0d40, 0xffffffff, 0x6a, 215 + 0x0d41, 0xffffffff, 0x1b082d, 216 + 0x0d40, 0xffffffff, 0x87, 217 + 0x0d41, 0xffffffff, 0x310851, 218 + 0x0d40, 0xffffffff, 0xba, 219 + 0x0d41, 0xffffffff, 0x891, 220 + 0x0d40, 0xffffffff, 0xbc, 221 + 0x0d41, 0xffffffff, 0x893, 222 + 0x0d40, 0xffffffff, 0xbe, 223 + 0x0d41, 0xffffffff, 0x20895, 224 + 0x0d40, 0xffffffff, 0xc2, 225 + 0x0d41, 0xffffffff, 0x20899, 226 + 0x0d40, 0xffffffff, 0xc6, 227 + 0x0d41, 0xffffffff, 0x2089d, 228 + 0x0d40, 0xffffffff, 0xca, 229 + 0x0d41, 0xffffffff, 0x8a1, 230 + 0x0d40, 0xffffffff, 0xcc, 231 + 0x0d41, 0xffffffff, 0x8a3, 232 + 0x0d40, 0xffffffff, 0xce, 233 + 0x0d41, 0xffffffff, 0x308a5, 234 + 0x0d40, 0xffffffff, 0xd3, 235 + 0x0d41, 0xffffffff, 0x6d08cd, 236 + 0x0d40, 0xffffffff, 0x142, 237 + 0x0d41, 0xffffffff, 0x2000095a, 238 + 0x0d41, 0xffffffff, 0x1, 239 + 0x0d40, 0xffffffff, 0x144, 240 + 0x0d41, 0xffffffff, 0x301f095b, 241 + 0x0d40, 0xffffffff, 0x165, 242 + 0x0d41, 0xffffffff, 0xc094d, 243 + 0x0d40, 0xffffffff, 0x173, 244 + 0x0d41, 0xffffffff, 0xf096d, 245 + 0x0d40, 0xffffffff, 0x184, 246 + 0x0d41, 0xffffffff, 0x15097f, 247 + 0x0d40, 0xffffffff, 0x19b, 248 + 0x0d41, 0xffffffff, 0xc0998, 249 + 0x0d40, 0xffffffff, 0x1a9, 250 + 0x0d41, 0xffffffff, 0x409a7, 251 + 0x0d40, 0xffffffff, 0x1af, 252 + 0x0d41, 0xffffffff, 0xcdc, 253 + 0x0d40, 0xffffffff, 0x1b1, 254 + 0x0d41, 0xffffffff, 0x800, 255 + 0x0d42, 0xffffffff, 0x6c9b2000, 256 + 0x0d44, 0xfc00, 0x2000, 257 + 0x0d51, 0xffffffff, 0xfc0, 258 + 0x0a35, 0x00000100, 0x100 271 259 }; 272 260 273 261 static const u32 verde_golden_rlc_registers[] = 274 262 { 263 + 0x263e, 0xffffffff, 0x02010002, 275 264 0x3109, 0xffffffff, 0x033f1005, 276 265 0x311f, 0xffffffff, 0x10808020, 277 266 0x3122, 0xffffffff, 0x00800008, ··· 282 269 283 270 static const u32 verde_golden_registers[] = 284 271 { 272 + 0x17bc, 0x00000030, 0x00000011, 285 273 0x2684, 0x00010000, 0x00018208, 286 274 0x260c, 0xffffffff, 0x00000000, 287 275 0x260d, 0xf00fffff, 0x00000400, 288 276 0x260e, 0x0002021c, 0x00020200, 289 277 0x031e, 0x00000080, 0x00000000, 290 278 0x340c, 0x000300c0, 0x00800040, 291 - 0x340c, 0x000300c0, 0x00800040, 292 - 0x360c, 0x000300c0, 0x00800040, 293 279 0x360c, 0x000300c0, 0x00800040, 294 280 0x16ec, 0x000000f0, 0x00000070, 295 281 0x16f0, 0x00200000, 0x50100000, 296 - 297 282 0x1c0c, 0x31000311, 0x00000011, 298 283 0x0ab9, 0x00073ffe, 0x000022a2, 299 - 0x0ab9, 0x00073ffe, 0x000022a2, 300 - 0x0ab9, 0x00073ffe, 0x000022a2, 301 - 0x0903, 0x000007ff, 0x00000000, 302 - 0x0903, 0x000007ff, 0x00000000, 303 284 0x0903, 0x000007ff, 0x00000000, 304 285 0x2285, 0xf000001f, 0x00000007, 305 - 0x2285, 0xf000001f, 0x00000007, 306 - 0x2285, 0xf000001f, 0x00000007, 307 - 0x2285, 0xffffffff, 0x00ffffff, 286 + 0x22c9, 0xffffffff, 0x00ffffff, 308 287 0x22c4, 0x0000ff0f, 0x00000000, 309 - 310 288 0xa293, 0x07ffffff, 0x4e000000, 311 289 0xa0d4, 0x3f3f3fff, 0x0000124a, 312 - 0xa0d4, 0x3f3f3fff, 0x0000124a, 313 - 0xa0d4, 0x3f3f3fff, 0x0000124a, 314 - 0x000c, 0x000000ff, 0x0040, 290 + 0x000c, 0xffffffff, 0x0040, 315 291 0x000d, 0x00000040, 0x00004040, 316 292 0x2440, 0x07ffffff, 0x03000000, 317 - 0x2440, 0x07ffffff, 0x03000000, 318 293 0x23a2, 0x01ff1f3f, 0x00000000, 319 - 0x23a3, 0x01ff1f3f, 0x00000000, 320 - 0x23a2, 0x01ff1f3f, 0x00000000, 321 - 0x23a1, 0x01ff1f3f, 0x00000000, 322 - 0x23a1, 0x01ff1f3f, 0x00000000, 323 - 324 294 0x23a1, 0x01ff1f3f, 0x00000000, 325 295 0x2418, 0x0000007f, 0x00000020, 326 296 0x2542, 0x00010000, 0x00010000, 327 - 0x2b01, 0x000003ff, 0x00000003, 328 - 0x2b05, 0x000003ff, 0x00000003, 329 297 0x2b05, 0x000003ff, 0x00000003, 330 298 0x2b04, 0xffffffff, 0x00000000, 331 - 0x2b04, 0xffffffff, 0x00000000, 332 - 0x2b04, 0xffffffff, 0x00000000, 333 - 0x2b03, 0xffffffff, 0x00001032, 334 - 0x2b03, 0xffffffff, 0x00001032, 335 299 0x2b03, 0xffffffff, 0x00001032, 336 300 0x2235, 0x0000001f, 0x00000010, 337 - 0x2235, 0x0000001f, 0x00000010, 338 - 0x2235, 0x0000001f, 0x00000010, 339 - 0x0570, 0x000c0fc0, 0x000c0400 301 + 0x0570, 0x000c0fc0, 0x000c0400, 302 + 0x052c, 0x0fffffff, 0xffffffff, 303 + 0x052d, 0x0fffffff, 0x0fffffff, 304 + 0x052e, 0x0fffffff, 0x0fffffff, 305 + 0x052f, 0x0fffffff, 0x0fffffff 340 306 }; 341 307 342 308 static const u32 oland_golden_registers[] = 343 309 { 310 + 0x17bc, 0x00000030, 0x00000011, 344 311 0x2684, 0x00010000, 0x00018208, 345 312 0x260c, 0xffffffff, 0x00000000, 346 313 0x260d, 0xf00fffff, 0x00000400, ··· 329 336 0x340c, 0x000300c0, 0x00800040, 330 337 0x360c, 0x000300c0, 0x00800040, 331 338 0x16ec, 0x000000f0, 0x00000070, 332 - 0x16f9, 0x00200000, 0x50100000, 339 + 0x16f0, 0x00200000, 0x50100000, 333 340 0x1c0c, 0x31000311, 0x00000011, 334 341 0x0ab9, 0x00073ffe, 0x000022a2, 335 342 0x0903, 0x000007ff, 0x00000000, ··· 338 345 0x22c4, 0x0000ff0f, 0x00000000, 339 346 0xa293, 0x07ffffff, 0x4e000000, 340 347 0xa0d4, 0x3f3f3fff, 0x00000082, 341 - 0x000c, 0x000000ff, 0x0040, 348 + 0x000c, 0xffffffff, 0x0040, 342 349 0x000d, 0x00000040, 0x00004040, 343 350 0x2440, 0x07ffffff, 0x03000000, 344 351 0x2418, 0x0000007f, 0x00000020, ··· 347 354 0x2b04, 0xffffffff, 0x00000000, 348 355 0x2b03, 0xffffffff, 0x00003210, 349 356 0x2235, 0x0000001f, 0x00000010, 350 - 0x0570, 0x000c0fc0, 0x000c0400 357 + 0x0570, 0x000c0fc0, 0x000c0400, 358 + 0x052c, 0x0fffffff, 0xffffffff, 359 + 0x052d, 0x0fffffff, 0x0fffffff, 360 + 0x052e, 0x0fffffff, 0x0fffffff, 361 + 0x052f, 0x0fffffff, 0x0fffffff 351 362 }; 352 363 353 364 static const u32 oland_golden_rlc_registers[] = 354 365 { 366 + 0x263e, 0xffffffff, 0x02010002, 355 367 0x3109, 0xffffffff, 0x00601005, 356 368 0x311f, 0xffffffff, 0x10104040, 357 369 0x3122, 0xffffffff, 0x0100000a, ··· 366 368 367 369 static const u32 hainan_golden_registers[] = 368 370 { 371 + 0x17bc, 0x00000030, 0x00000011, 369 372 0x2684, 0x00010000, 0x00018208, 370 373 0x260c, 0xffffffff, 0x00000000, 371 374 0x260d, 0xf00fffff, 0x00000400, 372 375 0x260e, 0x0002021c, 0x00020200, 373 - 0x4595, 0xff000fff, 0x00000100, 376 + 0x031e, 0x00000080, 0x00000000, 377 + 0x3430, 0xff000fff, 0x00000100, 374 378 0x340c, 0x000300c0, 0x00800040, 375 379 0x3630, 0xff000fff, 0x00000100, 376 380 0x360c, 0x000300c0, 0x00800040, 381 + 0x16ec, 0x000000f0, 0x00000070, 382 + 0x16f0, 0x00200000, 0x50100000, 383 + 0x1c0c, 0x31000311, 0x00000011, 377 384 0x0ab9, 0x00073ffe, 0x000022a2, 378 385 0x0903, 0x000007ff, 0x00000000, 379 386 0x2285, 0xf000001f, 0x00000007, 380 387 0x22c9, 0xffffffff, 0x00ffffff, 381 388 0x22c4, 0x0000ff0f, 0x00000000, 382 - 0xa393, 0x07ffffff, 0x4e000000, 389 + 0xa293, 0x07ffffff, 0x4e000000, 383 390 0xa0d4, 0x3f3f3fff, 0x00000000, 384 - 0x000c, 0x000000ff, 0x0040, 391 + 0x000c, 0xffffffff, 0x0040, 385 392 0x000d, 0x00000040, 0x00004040, 386 393 0x2440, 0x03e00000, 0x03600000, 387 394 0x2418, 0x0000007f, 0x00000020, ··· 395 392 0x2b04, 0xffffffff, 0x00000000, 396 393 0x2b03, 0xffffffff, 0x00003210, 397 394 0x2235, 0x0000001f, 0x00000010, 398 - 0x0570, 0x000c0fc0, 0x000c0400 395 + 0x0570, 0x000c0fc0, 0x000c0400, 396 + 0x052c, 0x0fffffff, 0xffffffff, 397 + 0x052d, 0x0fffffff, 0x0fffffff, 398 + 0x052e, 0x0fffffff, 0x0fffffff, 399 + 0x052f, 0x0fffffff, 0x0fffffff 399 400 }; 400 401 401 402 static const u32 hainan_golden_registers2[] = 402 403 { 403 - 0x263e, 0xffffffff, 0x02010001 404 + 0x263e, 0xffffffff, 0x2011003 404 405 }; 405 406 406 407 static const u32 tahiti_mgcg_cgcg_init[] = ··· 520 513 0x21c2, 0xffffffff, 0x00900100, 521 514 0x311e, 0xffffffff, 0x00000080, 522 515 0x3101, 0xffffffff, 0x0020003f, 523 - 0xc, 0xffffffff, 0x0000001c, 524 - 0xd, 0x000f0000, 0x000f0000, 525 - 0x583, 0xffffffff, 0x00000100, 526 - 0x409, 0xffffffff, 0x00000100, 527 - 0x40b, 0x00000101, 0x00000000, 528 - 0x82a, 0xffffffff, 0x00000104, 529 - 0x993, 0x000c0000, 0x000c0000, 530 - 0x992, 0x000c0000, 0x000c0000, 516 + 0x000c, 0xffffffff, 0x0000001c, 517 + 0x000d, 0x000f0000, 0x000f0000, 518 + 0x0583, 0xffffffff, 0x00000100, 519 + 0x0409, 0xffffffff, 0x00000100, 520 + 0x040b, 0x00000101, 0x00000000, 521 + 0x082a, 0xffffffff, 0x00000104, 522 + 0x0993, 0x000c0000, 0x000c0000, 523 + 0x0992, 0x000c0000, 0x000c0000, 531 524 0x1579, 0xff000fff, 0x00000100, 532 525 0x157a, 0x00000001, 0x00000001, 533 - 0xbd4, 0x00000001, 0x00000001, 534 - 0xc33, 0xc0000fff, 0x00000104, 526 + 0x0bd4, 0x00000001, 0x00000001, 527 + 0x0c33, 0xc0000fff, 0x00000104, 535 528 0x3079, 0x00000001, 0x00000001, 536 529 0x3430, 0xfffffff0, 0x00000100, 537 530 0x3630, 0xfffffff0, 0x00000100 ··· 619 612 0x21c2, 0xffffffff, 0x00900100, 620 613 0x311e, 0xffffffff, 0x00000080, 621 614 0x3101, 0xffffffff, 0x0020003f, 622 - 0xc, 0xffffffff, 0x0000001c, 623 - 0xd, 0x000f0000, 0x000f0000, 624 - 0x583, 0xffffffff, 0x00000100, 625 - 0x409, 0xffffffff, 0x00000100, 626 - 0x40b, 0x00000101, 0x00000000, 627 - 0x82a, 0xffffffff, 0x00000104, 615 + 0x000c, 0xffffffff, 0x0000001c, 616 + 0x000d, 0x000f0000, 0x000f0000, 617 + 0x0583, 0xffffffff, 0x00000100, 618 + 0x0409, 0xffffffff, 0x00000100, 619 + 0x040b, 0x00000101, 0x00000000, 620 + 0x082a, 0xffffffff, 0x00000104, 628 621 0x1579, 0xff000fff, 0x00000100, 629 622 0x157a, 0x00000001, 0x00000001, 630 - 0xbd4, 0x00000001, 0x00000001, 631 - 0xc33, 0xc0000fff, 0x00000104, 623 + 0x0bd4, 0x00000001, 0x00000001, 624 + 0x0c33, 0xc0000fff, 0x00000104, 632 625 0x3079, 0x00000001, 0x00000001, 633 626 0x3430, 0xfffffff0, 0x00000100, 634 627 0x3630, 0xfffffff0, 0x00000100 ··· 716 709 0x21c2, 0xffffffff, 0x00900100, 717 710 0x311e, 0xffffffff, 0x00000080, 718 711 0x3101, 0xffffffff, 0x0020003f, 719 - 0xc, 0xffffffff, 0x0000001c, 720 - 0xd, 0x000f0000, 0x000f0000, 721 - 0x583, 0xffffffff, 0x00000100, 722 - 0x409, 0xffffffff, 0x00000100, 723 - 0x40b, 0x00000101, 0x00000000, 724 - 0x82a, 0xffffffff, 0x00000104, 725 - 0x993, 0x000c0000, 0x000c0000, 726 - 0x992, 0x000c0000, 0x000c0000, 712 + 0x000c, 0xffffffff, 0x0000001c, 713 + 0x000d, 0x000f0000, 0x000f0000, 714 + 0x0583, 0xffffffff, 0x00000100, 715 + 0x0409, 0xffffffff, 0x00000100, 716 + 0x040b, 0x00000101, 0x00000000, 717 + 0x082a, 0xffffffff, 0x00000104, 718 + 0x0993, 0x000c0000, 0x000c0000, 719 + 0x0992, 0x000c0000, 0x000c0000, 727 720 0x1579, 0xff000fff, 0x00000100, 728 721 0x157a, 0x00000001, 0x00000001, 729 - 0xbd4, 0x00000001, 0x00000001, 730 - 0xc33, 0xc0000fff, 0x00000104, 722 + 0x0bd4, 0x00000001, 0x00000001, 723 + 0x0c33, 0xc0000fff, 0x00000104, 731 724 0x3079, 0x00000001, 0x00000001, 732 725 0x3430, 0xfffffff0, 0x00000100, 733 726 0x3630, 0xfffffff0, 0x00000100 ··· 795 788 0x21c2, 0xffffffff, 0x00900100, 796 789 0x311e, 0xffffffff, 0x00000080, 797 790 0x3101, 0xffffffff, 0x0020003f, 798 - 0xc, 0xffffffff, 0x0000001c, 799 - 0xd, 0x000f0000, 0x000f0000, 800 - 0x583, 0xffffffff, 0x00000100, 801 - 0x409, 0xffffffff, 0x00000100, 802 - 0x40b, 0x00000101, 0x00000000, 803 - 0x82a, 0xffffffff, 0x00000104, 804 - 0x993, 0x000c0000, 0x000c0000, 805 - 0x992, 0x000c0000, 0x000c0000, 791 + 0x000c, 0xffffffff, 0x0000001c, 792 + 0x000d, 0x000f0000, 0x000f0000, 793 + 0x0583, 0xffffffff, 0x00000100, 794 + 0x0409, 0xffffffff, 0x00000100, 795 + 0x040b, 0x00000101, 0x00000000, 796 + 0x082a, 0xffffffff, 0x00000104, 797 + 0x0993, 0x000c0000, 0x000c0000, 798 + 0x0992, 0x000c0000, 0x000c0000, 806 799 0x1579, 0xff000fff, 0x00000100, 807 800 0x157a, 0x00000001, 0x00000001, 808 - 0xbd4, 0x00000001, 0x00000001, 809 - 0xc33, 0xc0000fff, 0x00000104, 801 + 0x0bd4, 0x00000001, 0x00000001, 802 + 0x0c33, 0xc0000fff, 0x00000104, 810 803 0x3079, 0x00000001, 0x00000001, 811 804 0x3430, 0xfffffff0, 0x00000100, 812 805 0x3630, 0xfffffff0, 0x00000100 ··· 874 867 0x21c2, 0xffffffff, 0x00900100, 875 868 0x311e, 0xffffffff, 0x00000080, 876 869 0x3101, 0xffffffff, 0x0020003f, 877 - 0xc, 0xffffffff, 0x0000001c, 878 - 0xd, 0x000f0000, 0x000f0000, 879 - 0x583, 0xffffffff, 0x00000100, 880 - 0x409, 0xffffffff, 0x00000100, 881 - 0x82a, 0xffffffff, 0x00000104, 882 - 0x993, 0x000c0000, 0x000c0000, 883 - 0x992, 0x000c0000, 0x000c0000, 884 - 0xbd4, 0x00000001, 0x00000001, 885 - 0xc33, 0xc0000fff, 0x00000104, 870 + 0x000c, 0xffffffff, 0x0000001c, 871 + 0x000d, 0x000f0000, 0x000f0000, 872 + 0x0583, 0xffffffff, 0x00000100, 873 + 0x0409, 0xffffffff, 0x00000100, 874 + 0x082a, 0xffffffff, 0x00000104, 875 + 0x0993, 0x000c0000, 0x000c0000, 876 + 0x0992, 0x000c0000, 0x000c0000, 877 + 0x0bd4, 0x00000001, 0x00000001, 878 + 0x0c33, 0xc0000fff, 0x00000104, 886 879 0x3079, 0x00000001, 0x00000001, 887 880 0x3430, 0xfffffff0, 0x00000100, 888 881 0x3630, 0xfffffff0, 0x00000100 ··· 1186 1179 AMD_CG_SUPPORT_HDP_LS | 1187 1180 AMD_CG_SUPPORT_HDP_MGCG; 1188 1181 adev->pg_flags = 0; 1182 + adev->external_rev_id = (adev->rev_id == 0) ? 1 : 1183 + (adev->rev_id == 1) ? 5 : 6; 1189 1184 break; 1190 1185 case CHIP_PITCAIRN: 1191 1186 adev->cg_flags = ··· 1207 1198 AMD_CG_SUPPORT_HDP_LS | 1208 1199 AMD_CG_SUPPORT_HDP_MGCG; 1209 1200 adev->pg_flags = 0; 1201 + adev->external_rev_id = adev->rev_id + 20; 1210 1202 break; 1211 1203 1212 1204 case CHIP_VERDE: ··· 1229 1219 AMD_CG_SUPPORT_HDP_MGCG; 1230 1220 adev->pg_flags = 0; 1231 1221 //??? 1232 - adev->external_rev_id = adev->rev_id + 0x14; 1222 + adev->external_rev_id = adev->rev_id + 40; 1233 1223 break; 1234 1224 case CHIP_OLAND: 1235 1225 adev->cg_flags = ··· 1248 1238 AMD_CG_SUPPORT_HDP_LS | 1249 1239 AMD_CG_SUPPORT_HDP_MGCG; 1250 1240 adev->pg_flags = 0; 1241 + adev->external_rev_id = 60; 1251 1242 break; 1252 1243 case CHIP_HAINAN: 1253 1244 adev->cg_flags = ··· 1266 1255 AMD_CG_SUPPORT_HDP_LS | 1267 1256 AMD_CG_SUPPORT_HDP_MGCG; 1268 1257 adev->pg_flags = 0; 1258 + adev->external_rev_id = 70; 1269 1259 break; 1270 1260 1271 1261 default:

+153 -44

drivers/gpu/drm/amd/amdgpu/vi.c

··· 932 932 adev->external_rev_id = adev->rev_id + 0x3c; 933 933 break; 934 934 case CHIP_TONGA: 935 - adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; 936 - adev->pg_flags = AMD_PG_SUPPORT_UVD; 935 + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 936 + AMD_CG_SUPPORT_GFX_CGCG | 937 + AMD_CG_SUPPORT_GFX_CGLS | 938 + AMD_CG_SUPPORT_SDMA_MGCG | 939 + AMD_CG_SUPPORT_SDMA_LS | 940 + AMD_CG_SUPPORT_BIF_LS | 941 + AMD_CG_SUPPORT_HDP_MGCG | 942 + AMD_CG_SUPPORT_HDP_LS | 943 + AMD_CG_SUPPORT_ROM_MGCG | 944 + AMD_CG_SUPPORT_MC_MGCG | 945 + AMD_CG_SUPPORT_MC_LS | 946 + AMD_CG_SUPPORT_DRM_LS | 947 + AMD_CG_SUPPORT_UVD_MGCG; 948 + adev->pg_flags = 0; 937 949 adev->external_rev_id = adev->rev_id + 0x14; 938 950 break; 939 951 case CHIP_POLARIS11: 940 - adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 952 + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 953 + AMD_CG_SUPPORT_GFX_RLC_LS | 954 + AMD_CG_SUPPORT_GFX_CP_LS | 955 + AMD_CG_SUPPORT_GFX_CGCG | 956 + AMD_CG_SUPPORT_GFX_CGLS | 957 + AMD_CG_SUPPORT_GFX_3D_CGCG | 958 + AMD_CG_SUPPORT_GFX_3D_CGLS | 959 + AMD_CG_SUPPORT_SDMA_MGCG | 960 + AMD_CG_SUPPORT_SDMA_LS | 961 + AMD_CG_SUPPORT_BIF_MGCG | 962 + AMD_CG_SUPPORT_BIF_LS | 963 + AMD_CG_SUPPORT_HDP_MGCG | 964 + AMD_CG_SUPPORT_HDP_LS | 965 + AMD_CG_SUPPORT_ROM_MGCG | 966 + AMD_CG_SUPPORT_MC_MGCG | 967 + AMD_CG_SUPPORT_MC_LS | 968 + AMD_CG_SUPPORT_DRM_LS | 969 + AMD_CG_SUPPORT_UVD_MGCG | 941 970 AMD_CG_SUPPORT_VCE_MGCG; 942 971 adev->pg_flags = 0; 943 972 adev->external_rev_id = adev->rev_id + 0x5A; 944 973 break; 945 974 case CHIP_POLARIS10: 946 - adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 975 + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 976 + AMD_CG_SUPPORT_GFX_RLC_LS | 977 + AMD_CG_SUPPORT_GFX_CP_LS | 978 + AMD_CG_SUPPORT_GFX_CGCG | 979 + AMD_CG_SUPPORT_GFX_CGLS | 980 + AMD_CG_SUPPORT_GFX_3D_CGCG | 981 + AMD_CG_SUPPORT_GFX_3D_CGLS | 982 + AMD_CG_SUPPORT_SDMA_MGCG | 983 + AMD_CG_SUPPORT_SDMA_LS | 984 + AMD_CG_SUPPORT_BIF_MGCG | 985 + AMD_CG_SUPPORT_BIF_LS | 986 + AMD_CG_SUPPORT_HDP_MGCG | 987 + AMD_CG_SUPPORT_HDP_LS | 988 + AMD_CG_SUPPORT_ROM_MGCG | 989 + AMD_CG_SUPPORT_MC_MGCG | 990 + AMD_CG_SUPPORT_MC_LS | 991 + AMD_CG_SUPPORT_DRM_LS | 992 + AMD_CG_SUPPORT_UVD_MGCG | 947 993 AMD_CG_SUPPORT_VCE_MGCG; 948 994 adev->pg_flags = 0; 949 995 adev->external_rev_id = adev->rev_id + 0x50; ··· 1017 971 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1018 972 AMD_PG_SUPPORT_GFX_SMG | 1019 973 AMD_PG_SUPPORT_GFX_PIPELINE | 974 + AMD_PG_SUPPORT_CP | 1020 975 AMD_PG_SUPPORT_UVD | 1021 976 AMD_PG_SUPPORT_VCE; 1022 977 } ··· 1043 996 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1044 997 AMD_PG_SUPPORT_GFX_SMG | 1045 998 AMD_PG_SUPPORT_GFX_PIPELINE | 999 + AMD_PG_SUPPORT_CP | 1046 1000 AMD_PG_SUPPORT_UVD | 1047 1001 AMD_PG_SUPPORT_VCE; 1048 1002 adev->external_rev_id = adev->rev_id + 0x61; ··· 1203 1155 static int vi_common_set_clockgating_state_by_smu(void *handle, 1204 1156 enum amd_clockgating_state state) 1205 1157 { 1206 - uint32_t msg_id, pp_state; 1158 + uint32_t msg_id, pp_state = 0; 1159 + uint32_t pp_support_state = 0; 1207 1160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1208 1161 void *pp_handle = adev->powerplay.pp_handle; 1209 1162 1210 - if (state == AMD_CG_STATE_UNGATE) 1211 - pp_state = 0; 1212 - else 1213 - pp_state = PP_STATE_CG | PP_STATE_LS; 1163 + if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) { 1164 + if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) { 1165 + pp_support_state = AMD_CG_SUPPORT_MC_LS; 1166 + pp_state = PP_STATE_LS; 1167 + } 1168 + if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) { 1169 + pp_support_state |= AMD_CG_SUPPORT_MC_MGCG; 1170 + pp_state |= PP_STATE_CG; 1171 + } 1172 + if (state == AMD_CG_STATE_UNGATE) 1173 + pp_state = 0; 1174 + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1175 + PP_BLOCK_SYS_MC, 1176 + pp_support_state, 1177 + pp_state); 1178 + amd_set_clockgating_by_smu(pp_handle, msg_id); 1179 + } 1214 1180 1215 - msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1216 - PP_BLOCK_SYS_MC, 1217 - PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 1218 - pp_state); 1219 - amd_set_clockgating_by_smu(pp_handle, msg_id); 1181 + if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) { 1182 + if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) { 1183 + pp_support_state = AMD_CG_SUPPORT_SDMA_LS; 1184 + pp_state = PP_STATE_LS; 1185 + } 1186 + if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) { 1187 + pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG; 1188 + pp_state |= PP_STATE_CG; 1189 + } 1190 + if (state == AMD_CG_STATE_UNGATE) 1191 + pp_state = 0; 1192 + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1193 + PP_BLOCK_SYS_SDMA, 1194 + pp_support_state, 1195 + pp_state); 1196 + amd_set_clockgating_by_smu(pp_handle, msg_id); 1197 + } 1220 1198 1221 - msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1222 - PP_BLOCK_SYS_SDMA, 1223 - PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 1224 - pp_state); 1225 - amd_set_clockgating_by_smu(pp_handle, msg_id); 1199 + if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) { 1200 + if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1201 + pp_support_state = AMD_CG_SUPPORT_HDP_LS; 1202 + pp_state = PP_STATE_LS; 1203 + } 1204 + if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) { 1205 + pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG; 1206 + pp_state |= PP_STATE_CG; 1207 + } 1208 + if (state == AMD_CG_STATE_UNGATE) 1209 + pp_state = 0; 1210 + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1211 + PP_BLOCK_SYS_HDP, 1212 + pp_support_state, 1213 + pp_state); 1214 + amd_set_clockgating_by_smu(pp_handle, msg_id); 1215 + } 1226 1216 1227 - msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1228 - PP_BLOCK_SYS_HDP, 1229 - PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 1230 - pp_state); 1231 - amd_set_clockgating_by_smu(pp_handle, msg_id); 1232 1217 1233 - msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1234 - PP_BLOCK_SYS_BIF, 1235 - PP_STATE_SUPPORT_LS, 1236 - pp_state); 1237 - amd_set_clockgating_by_smu(pp_handle, msg_id); 1218 + if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) { 1219 + if (state == AMD_CG_STATE_UNGATE) 1220 + pp_state = 0; 1221 + else 1222 + pp_state = PP_STATE_LS; 1238 1223 1239 - msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1240 - PP_BLOCK_SYS_BIF, 1241 - PP_STATE_SUPPORT_CG, 1242 - pp_state); 1243 - amd_set_clockgating_by_smu(pp_handle, msg_id); 1224 + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1225 + PP_BLOCK_SYS_BIF, 1226 + PP_STATE_SUPPORT_LS, 1227 + pp_state); 1228 + amd_set_clockgating_by_smu(pp_handle, msg_id); 1229 + } 1230 + if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) { 1231 + if (state == AMD_CG_STATE_UNGATE) 1232 + pp_state = 0; 1233 + else 1234 + pp_state = PP_STATE_CG; 1244 1235 1245 - msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1246 - PP_BLOCK_SYS_DRM, 1247 - PP_STATE_SUPPORT_LS, 1248 - pp_state); 1249 - amd_set_clockgating_by_smu(pp_handle, msg_id); 1236 + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1237 + PP_BLOCK_SYS_BIF, 1238 + PP_STATE_SUPPORT_CG, 1239 + pp_state); 1240 + amd_set_clockgating_by_smu(pp_handle, msg_id); 1241 + } 1250 1242 1251 - msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1252 - PP_BLOCK_SYS_ROM, 1253 - PP_STATE_SUPPORT_CG, 1254 - pp_state); 1255 - amd_set_clockgating_by_smu(pp_handle, msg_id); 1243 + if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) { 1256 1244 1245 + if (state == AMD_CG_STATE_UNGATE) 1246 + pp_state = 0; 1247 + else 1248 + pp_state = PP_STATE_LS; 1249 + 1250 + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1251 + PP_BLOCK_SYS_DRM, 1252 + PP_STATE_SUPPORT_LS, 1253 + pp_state); 1254 + amd_set_clockgating_by_smu(pp_handle, msg_id); 1255 + } 1256 + 1257 + if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) { 1258 + 1259 + if (state == AMD_CG_STATE_UNGATE) 1260 + pp_state = 0; 1261 + else 1262 + pp_state = PP_STATE_CG; 1263 + 1264 + msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1265 + PP_BLOCK_SYS_ROM, 1266 + PP_STATE_SUPPORT_CG, 1267 + pp_state); 1268 + amd_set_clockgating_by_smu(pp_handle, msg_id); 1269 + } 1257 1270 return 0; 1258 1271 } 1259 1272

+4

drivers/gpu/drm/amd/include/amd_shared.h

··· 126 126 #define AMD_CG_SUPPORT_HDP_LS (1 << 15) 127 127 #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) 128 128 #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) 129 + #define AMD_CG_SUPPORT_DRM_LS (1 << 18) 130 + #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19) 131 + #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20) 132 + #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) 129 133 130 134 /* PG flags */ 131 135 #define AMD_PG_SUPPORT_GFX_PG (1 << 0)