dt-bindings: cache: andestech,ax45mp-cache: Fix unit address in example

The unit address in the example does not match the reg property.
Correct the unit address to match reality.

Fixes: 3e7bf4685e42786d ("dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller")
Signed-off-by: Geert Uytterhoeven <[e-mail]>
Reviewed-by: Krzysztof Kozlowski <[e-mail]>
Reviewed-by: Lad Prabhakar <[e-mail]>
Link: https://lore.kernel.org/r/7b936[e-mail]
Signed-off-by: Rob Herring <[e-mail]>

Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml

···
   - |
     #include <dt-bindings/interrupt-controller/irq.h>
 
-    cache-controller@2010000 {
+    cache-controller@13400000 {
         compatible = "andestech,ax45mp-cache", "cache";
         reg = <0x13400000 0x100000>;
         interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;