Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
+4
arch/sparc64/kernel/cpu.c
+4
arch/sparc64/kernel/cpu.c
···
39
{ 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"},
40
{ 0x3e, 0x16, 0, "UltraSparc IIIi integrated FPU"},
41
{ 0x3e, 0x18, 0, "UltraSparc IV integrated FPU"},
42
};
43
44
#define NSPARCFPU (sizeof(linux_sparc_fpu)/sizeof(struct cpu_fp_info))
···
55
{ 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},
56
{ 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"},
57
{ 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"},
58
};
59
60
#define NSPARCCHIPS (sizeof(linux_sparc_chips)/sizeof(struct cpu_iu_info))
···
39
{ 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"},
40
{ 0x3e, 0x16, 0, "UltraSparc IIIi integrated FPU"},
41
{ 0x3e, 0x18, 0, "UltraSparc IV integrated FPU"},
42
+
{ 0x3e, 0x19, 0, "UltraSparc IV+ integrated FPU"},
43
+
{ 0x3e, 0x22, 0, "UltraSparc IIIi+ integrated FPU"},
44
};
45
46
#define NSPARCFPU (sizeof(linux_sparc_fpu)/sizeof(struct cpu_fp_info))
···
53
{ 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},
54
{ 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"},
55
{ 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"},
56
+
{ 0x3e, 0x19, "TI UltraSparc IV+ (Panther)"},
57
+
{ 0x3e, 0x22, "TI UltraSparc IIIi+ (Serrano)"},
58
};
59
60
#define NSPARCCHIPS (sizeof(linux_sparc_chips)/sizeof(struct cpu_iu_info))
+5
-5
arch/sparc64/kernel/unaligned.c
+5
-5
arch/sparc64/kernel/unaligned.c
···
294
295
kernel_mna_trap_fault();
296
} else {
297
-
unsigned long addr;
298
int orig_asi, asi;
299
300
addr = compute_effective_address(regs, insn,
···
319
};
320
switch (dir) {
321
case load:
322
-
do_int_load(fetch_reg_addr(((insn>>25)&0x1f), regs),
323
-
size, (unsigned long *) addr,
324
decode_signedness(insn), asi);
325
if (unlikely(asi != orig_asi)) {
326
-
unsigned long val_in = *(unsigned long *) addr;
327
switch (size) {
328
case 2:
329
val_in = swab16(val_in);
···
339
BUG();
340
break;
341
};
342
-
*(unsigned long *) addr = val_in;
343
}
344
break;
345
···
294
295
kernel_mna_trap_fault();
296
} else {
297
+
unsigned long addr, *reg_addr;
298
int orig_asi, asi;
299
300
addr = compute_effective_address(regs, insn,
···
319
};
320
switch (dir) {
321
case load:
322
+
reg_addr = fetch_reg_addr(((insn>>25)&0x1f), regs);
323
+
do_int_load(reg_addr, size, (unsigned long *) addr,
324
decode_signedness(insn), asi);
325
if (unlikely(asi != orig_asi)) {
326
+
unsigned long val_in = *reg_addr;
327
switch (size) {
328
case 2:
329
val_in = swab16(val_in);
···
339
BUG();
340
break;
341
};
342
+
*reg_addr = val_in;
343
}
344
break;
345
+4
-1
arch/sparc64/kernel/us3_cpufreq.c
+4
-1
arch/sparc64/kernel/us3_cpufreq.c
+6
-3
include/asm-sparc64/head.h
+6
-3
include/asm-sparc64/head.h
···
12
#define __JALAPENO_ID 0x003e0016
13
14
#define CHEETAH_MANUF 0x003e
15
+
#define CHEETAH_IMPL 0x0014 /* Ultra-III */
16
+
#define CHEETAH_PLUS_IMPL 0x0015 /* Ultra-III+ */
17
+
#define JALAPENO_IMPL 0x0016 /* Ultra-IIIi */
18
+
#define JAGUAR_IMPL 0x0018 /* Ultra-IV */
19
+
#define PANTHER_IMPL 0x0019 /* Ultra-IV+ */
20
+
#define SERRANO_IMPL 0x0022 /* Ultra-IIIi+ */
21
22
#define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
23
rdpr %ver, %tmp1; \
+3
-1
include/asm-sparc64/pgtable.h
+3
-1
include/asm-sparc64/pgtable.h
···
98
#define _PAGE_NFO _AC(0x1000000000000000,UL) /* No Fault Only */
99
#define _PAGE_IE _AC(0x0800000000000000,UL) /* Invert Endianness */
100
#define _PAGE_SOFT2 _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
101
-
#define _PAGE_RES1 _AC(0x0003000000000000,UL) /* Reserved */
102
#define _PAGE_SN _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
103
#define _PAGE_RES2 _AC(0x0000780000000000,UL) /* Reserved */
104
#define _PAGE_PADDR_SF _AC(0x000001FFFFFFE000,UL) /* (Spitfire) paddr[40:13]*/
···
98
#define _PAGE_NFO _AC(0x1000000000000000,UL) /* No Fault Only */
99
#define _PAGE_IE _AC(0x0800000000000000,UL) /* Invert Endianness */
100
#define _PAGE_SOFT2 _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
101
+
#define _PAGE_RES1 _AC(0x0002000000000000,UL) /* Reserved */
102
+
#define _PAGE_SZ32MB _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
103
+
#define _PAGE_SZ256MB _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
104
#define _PAGE_SN _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
105
#define _PAGE_RES2 _AC(0x0000780000000000,UL) /* Reserved */
106
#define _PAGE_PADDR_SF _AC(0x000001FFFFFFE000,UL) /* (Spitfire) paddr[40:13]*/