tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'sm8450-sm8550-gpucc-binding' into clk-for-6.5
Bring GPUCC DeviceTree bindings for SM8450 and SM8550 in through a topic
branch to allow sharing it with the DeviceTree source tree as well.
+191
+75
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
+75
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Graphics Clock & Reset Controller on SM8450
8
+
9
+
maintainers:
10
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
11
+
12
+
description: |
13
+
Qualcomm graphics clock control module provides the clocks, resets and power
14
+
domains on Qualcomm SoCs.
15
+
16
+
See also::
17
+
include/dt-bindings/clock/qcom,sm8450-gpucc.h
18
+
include/dt-bindings/clock/qcom,sm8550-gpucc.h
19
+
include/dt-bindings/reset/qcom,sm8450-gpucc.h
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
+
- qcom,sm8450-gpucc
25
+
- qcom,sm8550-gpucc
26
+
27
+
clocks:
28
+
items:
29
+
- description: Board XO source
30
+
- description: GPLL0 main branch source
31
+
- description: GPLL0 div branch source
32
+
33
+
'#clock-cells':
34
+
const: 1
35
+
36
+
'#reset-cells':
37
+
const: 1
38
+
39
+
'#power-domain-cells':
40
+
const: 1
41
+
42
+
reg:
43
+
maxItems: 1
44
+
45
+
required:
46
+
- compatible
47
+
- reg
48
+
- clocks
49
+
- '#clock-cells'
50
+
- '#reset-cells'
51
+
- '#power-domain-cells'
52
+
53
+
additionalProperties: false
54
+
55
+
examples:
56
+
- |
57
+
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
58
+
#include <dt-bindings/clock/qcom,rpmh.h>
59
+
60
+
soc {
61
+
#address-cells = <2>;
62
+
#size-cells = <2>;
63
+
64
+
clock-controller@3d90000 {
65
+
compatible = "qcom,sm8450-gpucc";
66
+
reg = <0 0x03d90000 0 0xa000>;
67
+
clocks = <&rpmhcc RPMH_CXO_CLK>,
68
+
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
69
+
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
70
+
#clock-cells = <1>;
71
+
#reset-cells = <1>;
72
+
#power-domain-cells = <1>;
73
+
};
74
+
};
75
+
...
+48
include/dt-bindings/clock/qcom,sm8450-gpucc.h
+48
include/dt-bindings/clock/qcom,sm8450-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H
8
+
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H
9
+
10
+
/* Clocks */
11
+
#define GPU_CC_AHB_CLK 0
12
+
#define GPU_CC_CRC_AHB_CLK 1
13
+
#define GPU_CC_CX_APB_CLK 2
14
+
#define GPU_CC_CX_FF_CLK 3
15
+
#define GPU_CC_CX_GMU_CLK 4
16
+
#define GPU_CC_CX_SNOC_DVM_CLK 5
17
+
#define GPU_CC_CXO_AON_CLK 6
18
+
#define GPU_CC_CXO_CLK 7
19
+
#define GPU_CC_DEMET_CLK 8
20
+
#define GPU_CC_DEMET_DIV_CLK_SRC 9
21
+
#define GPU_CC_FF_CLK_SRC 10
22
+
#define GPU_CC_FREQ_MEASURE_CLK 11
23
+
#define GPU_CC_GMU_CLK_SRC 12
24
+
#define GPU_CC_GX_FF_CLK 13
25
+
#define GPU_CC_GX_GFX3D_CLK 14
26
+
#define GPU_CC_GX_GFX3D_RDVM_CLK 15
27
+
#define GPU_CC_GX_GMU_CLK 16
28
+
#define GPU_CC_GX_VSENSE_CLK 17
29
+
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18
30
+
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 19
31
+
#define GPU_CC_HUB_AON_CLK 20
32
+
#define GPU_CC_HUB_CLK_SRC 21
33
+
#define GPU_CC_HUB_CX_INT_CLK 22
34
+
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 23
35
+
#define GPU_CC_MEMNOC_GFX_CLK 24
36
+
#define GPU_CC_MND1X_0_GFX3D_CLK 25
37
+
#define GPU_CC_MND1X_1_GFX3D_CLK 26
38
+
#define GPU_CC_PLL0 27
39
+
#define GPU_CC_PLL1 28
40
+
#define GPU_CC_SLEEP_CLK 29
41
+
#define GPU_CC_XO_CLK_SRC 30
42
+
#define GPU_CC_XO_DIV_CLK_SRC 31
43
+
44
+
/* GDSCs */
45
+
#define GPU_GX_GDSC 0
46
+
#define GPU_CX_GDSC 1
47
+
48
+
#endif
+48
include/dt-bindings/clock/qcom,sm8550-gpucc.h
+48
include/dt-bindings/clock/qcom,sm8550-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
7
+
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
8
+
9
+
/* GPU_CC clocks */
10
+
#define GPU_CC_AHB_CLK 0
11
+
#define GPU_CC_CRC_AHB_CLK 1
12
+
#define GPU_CC_CX_FF_CLK 2
13
+
#define GPU_CC_CX_GMU_CLK 3
14
+
#define GPU_CC_CXO_AON_CLK 4
15
+
#define GPU_CC_CXO_CLK 5
16
+
#define GPU_CC_DEMET_CLK 6
17
+
#define GPU_CC_DEMET_DIV_CLK_SRC 7
18
+
#define GPU_CC_FF_CLK_SRC 8
19
+
#define GPU_CC_FREQ_MEASURE_CLK 9
20
+
#define GPU_CC_GMU_CLK_SRC 10
21
+
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11
22
+
#define GPU_CC_HUB_AON_CLK 12
23
+
#define GPU_CC_HUB_CLK_SRC 13
24
+
#define GPU_CC_HUB_CX_INT_CLK 14
25
+
#define GPU_CC_MEMNOC_GFX_CLK 15
26
+
#define GPU_CC_MND1X_0_GFX3D_CLK 16
27
+
#define GPU_CC_MND1X_1_GFX3D_CLK 17
28
+
#define GPU_CC_PLL0 18
29
+
#define GPU_CC_PLL1 19
30
+
#define GPU_CC_SLEEP_CLK 20
31
+
#define GPU_CC_XO_CLK_SRC 21
32
+
#define GPU_CC_XO_DIV_CLK_SRC 22
33
+
34
+
/* GPU_CC power domains */
35
+
#define GPU_CC_CX_GDSC 0
36
+
#define GPU_CC_GX_GDSC 1
37
+
38
+
/* GPU_CC resets */
39
+
#define GPUCC_GPU_CC_ACD_BCR 0
40
+
#define GPUCC_GPU_CC_CX_BCR 1
41
+
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
42
+
#define GPUCC_GPU_CC_FF_BCR 3
43
+
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
44
+
#define GPUCC_GPU_CC_GMU_BCR 5
45
+
#define GPUCC_GPU_CC_GX_BCR 6
46
+
#define GPUCC_GPU_CC_XO_BCR 7
47
+
48
+
#endif
+20
include/dt-bindings/reset/qcom,sm8450-gpucc.h
+20
include/dt-bindings/reset/qcom,sm8450-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H
8
+
#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H
9
+
10
+
#define GPUCC_GPU_CC_ACD_BCR 0
11
+
#define GPUCC_GPU_CC_CX_BCR 1
12
+
#define GPUCC_GPU_CC_FAST_HUB_BCR 2
13
+
#define GPUCC_GPU_CC_FF_BCR 3
14
+
#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
15
+
#define GPUCC_GPU_CC_GMU_BCR 5
16
+
#define GPUCC_GPU_CC_GX_BCR 6
17
+
#define GPUCC_GPU_CC_XO_BCR 7
18
+
#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8
19
+
20
+
#endif